This paper describes an implementation method for object-oriented applications. In the common practice the base address of the current object instance is passed on the stack as a pointer from one virtual method to another. The way suggested in this paper uses a global pointer pointing to the currently active object. This pointer is implemented by using some of the CPU registers exclusively for this purpose, thus saving the time of reloading it. Provided that some instructions manipulate on the same object instance before the program switches to another object a smaller and faster executing code can be achieved and at the same time some stack space can be saved.
{"title":"Implementation of object-oriented programming via register based pointer","authors":"Andr ás Zs ót ér","doi":"10.1006/jmca.1995.0019","DOIUrl":"https://doi.org/10.1006/jmca.1995.0019","url":null,"abstract":"<div><p>This paper describes an implementation method for object-oriented applications. In the common practice the base address of the current object instance is passed on the stack as a pointer from one virtual method to another. The way suggested in this paper uses a global pointer pointing to the currently active object. This pointer is implemented by using some of the CPU registers exclusively for this purpose, thus saving the time of reloading it. Provided that some instructions manipulate on the same object instance before the program switches to another object a smaller and faster executing code can be achieved and at the same time some stack space can be saved.</p></div>","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"18 3","pages":"Pages 279-285"},"PeriodicalIF":0.0,"publicationDate":"1995-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1006/jmca.1995.0019","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71740260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes how a simulated genetic process is used to automate the configuration and training of a back propagation trained multi-layer perceptron network used for credit application vetting. The network is trained on past loan case data, and is then used to classify the suitability of issuing credit on new loan applications. A prototype scheme for using a genetic algorithm to choose the network geometry and back propagation parameters so as to optimize classification accuracy and speed of convergence is described. This optimization relies upon the genetic algorithm assessing a fitness criteria. The novel fitness criteria that has been developed for this application is described with the associated problems, and some suggestions for future research. The particular genetic algorithm used and its mechanisms are detailed. The performance of the final system is compared with the performance of a manually configured system over common data. The genetic algorithm refined system is seen to outperform the manual system in terms of accuracy, whilst requiring a minimum of operator effort by comparison. Results indicate the successful automation of this aspect of the optimization for such a credit application vetting system, although further investigation into the most suitable fitness criteria is still warranted, so as to incorporate further business information.
{"title":"Refining a neural network credit application vetting system with a genetic algorithm","authors":"A. G. Williamson","doi":"10.1006/JMCA.1995.0018","DOIUrl":"https://doi.org/10.1006/JMCA.1995.0018","url":null,"abstract":"This paper describes how a simulated genetic process is used to automate the configuration and training of a back propagation trained multi-layer perceptron network used for credit application vetting. The network is trained on past loan case data, and is then used to classify the suitability of issuing credit on new loan applications. A prototype scheme for using a genetic algorithm to choose the network geometry and back propagation parameters so as to optimize classification accuracy and speed of convergence is described. This optimization relies upon the genetic algorithm assessing a fitness criteria. The novel fitness criteria that has been developed for this application is described with the associated problems, and some suggestions for future research. The particular genetic algorithm used and its mechanisms are detailed. The performance of the final system is compared with the performance of a manually configured system over common data. The genetic algorithm refined system is seen to outperform the manual system in terms of accuracy, whilst requiring a minimum of operator effort by comparison. Results indicate the successful automation of this aspect of the optimization for such a credit application vetting system, although further investigation into the most suitable fitness criteria is still warranted, so as to incorporate further business information.","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"19 1","pages":"261-277"},"PeriodicalIF":0.0,"publicationDate":"1995-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78937926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abstract Today 's requirements for computational power are still not satisfied. One answer for this demand is expensive supercomputers. Another attempt is the collection of computational power in a network. Connected workstations operate for parallel computation. Our approach for collecting unused resources in workstation clusters enables dynamic distribution of computational load over the network. Any computer individually distinguishes the amount of server resources sharing for others in the network. Our architecture is based on the client /server model —clients divide potentially hard problems into sub problems and forward them to different servers in the network. The usage of standardized remote procedure calls (rpc) as the basic mechanism for transmission of data between the workstations allows the extension of the concept for heterogeneous environments. This article gives a discussion of our implementation for Windows NT and presents the latest benchmarks with two special parallel applications.
{"title":"Parallel computation with dynamic load distribution for locally distributed Windows NT environments","authors":"G. Eschelbeck","doi":"10.1006/JMCA.1995.0014","DOIUrl":"https://doi.org/10.1006/JMCA.1995.0014","url":null,"abstract":"Abstract Today 's requirements for computational power are still not satisfied. One answer for this demand is expensive supercomputers. Another attempt is the collection of computational power in a network. Connected workstations operate for parallel computation. Our approach for collecting unused resources in workstation clusters enables dynamic distribution of computational load over the network. Any computer individually distinguishes the amount of server resources sharing for others in the network. Our architecture is based on the client /server model —clients divide potentially hard problems into sub problems and forward them to different servers in the network. The usage of standardized remote procedure calls (rpc) as the basic mechanism for transmission of data between the workstations allows the extension of the concept for heterogeneous environments. This article gives a discussion of our implementation for Windows NT and presents the latest benchmarks with two special parallel applications.","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"101 1","pages":"193-201"},"PeriodicalIF":0.0,"publicationDate":"1995-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79336107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes how a simulated genetic process is used to automate the configuration and training of a back propagation trained multi-layer perceptron network used for credit application vetting. The network is trained on past loan case data, and is then used to classify the suitability of issuing credit on new loan applications. A prototype scheme for using a genetic algorithm to choose the network geometry and back propagation parameters so as to optimize classification accuracy and speed of convergence is described. This optimization relies upon the genetic algorithm assessing a fitness criteria. The novel fitness criteria that has been developed for this application is described with the associated problems, and some suggestions for future research. The particular genetic algorithm used and its mechanisms are detailed. The performance of the final system is compared with the performance of a manually configured system over common data. The genetic algorithm refined system is seen to outperform the manual system in terms of accuracy, whilst requiring a minimum of operator effort by comparison. Results indicate the successful automation of this aspect of the optimization for such a credit application vetting system, although further investigation into the most suitable fitness criteria is still warranted, so as to incorporate further business information.
{"title":"Refining a neural network credit application vetting system with a genetic algorithm","authors":"Williamson A.G.","doi":"10.1006/jmca.1995.0018","DOIUrl":"https://doi.org/10.1006/jmca.1995.0018","url":null,"abstract":"<div><p>This paper describes how a simulated genetic process is used to automate the configuration and training of a back propagation trained multi-layer perceptron network used for credit application vetting. The network is trained on past loan case data, and is then used to classify the suitability of issuing credit on new loan applications. A prototype scheme for using a genetic algorithm to choose the network geometry and back propagation parameters so as to optimize classification accuracy and speed of convergence is described. This optimization relies upon the genetic algorithm assessing a fitness criteria. The novel fitness criteria that has been developed for this application is described with the associated problems, and some suggestions for future research. The particular genetic algorithm used and its mechanisms are detailed. The performance of the final system is compared with the performance of a manually configured system over common data. The genetic algorithm refined system is seen to outperform the manual system in terms of accuracy, whilst requiring a minimum of operator effort by comparison. Results indicate the successful automation of this aspect of the optimization for such a credit application vetting system, although further investigation into the most suitable fitness criteria is still warranted, so as to incorporate further business information.</p></div>","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"18 3","pages":"Pages 261-277"},"PeriodicalIF":0.0,"publicationDate":"1995-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1006/jmca.1995.0018","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71740259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel and generalized open framework for multimedia information manipulation is proposed. The document system consists of functional modules for capturing, storing and presenting multimedia data. These modules work independently and communicate through aHyperDocument Interfacelayer. The modular approach has the added advantage of easy-to-maintain and the convenience for future enhancements. Hypermedia and temporal –spatial relationships between document media nodes are embedded into the data structure to support flexible presentation of multimedia information. Windows and a specially designedDocument Tree Dialogprovide an environment for efficient and user-friendly information retrieval. Other system issues such as security and customization are also addressed in the design. Based on this approach, a medical multimedia document system to handle cardiac catheterization record (CCR) was designed as a demonstration for the research idea. The proposed design can be applied and extended to cover a variety of multimedia applications.
{"title":"An open framework for a multimedia medical document system (a multimedia document system framework)","authors":"Horace H.S. Ip, Ken C.K. Law, Chan S.L.","doi":"10.1006/jmca.1996.0016","DOIUrl":"https://doi.org/10.1006/jmca.1996.0016","url":null,"abstract":"<div><p>A novel and generalized open framework for multimedia information manipulation is proposed. The document system consists of functional modules for capturing, storing and presenting multimedia data. These modules work independently and communicate through a<em>HyperDocument Interface</em>layer. The modular approach has the added advantage of easy-to-maintain and the convenience for future enhancements. Hypermedia and temporal –spatial relationships between document media nodes are embedded into the data structure to support flexible presentation of multimedia information. Windows and a specially designed<em>Document Tree Dialog</em>provide an environment for efficient and user-friendly information retrieval. Other system issues such as security and customization are also addressed in the design. Based on this approach, a medical multimedia document system to handle cardiac catheterization record (CCR) was designed as a demonstration for the research idea. The proposed design can be applied and extended to cover a variety of multimedia applications.</p></div>","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"18 3","pages":"Pages 215-232"},"PeriodicalIF":0.0,"publicationDate":"1995-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1006/jmca.1996.0016","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71740257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the structural design and the functional characteristics of a RISC processor called Hermes-RISC. The design of the Hermes-RISC processor is based on the study and evaluation of a variety of assembly instruction sets. The Hermes-RISC is a pipeline superscalar RISC processor with four superscalar units. The first stage evaluation of the Hermes-RISC performance is also presented here. This evaluation is based on the execution of a set of primitive processing tasks, such as summation, multiplication of numbers, multiplication of matrices, sorting, finding maximum values among a set of numbers, procedure calls, etc. Moreover, the performance of Hermes-RISC is compared with a variety of RISC processors.
{"title":"Design of the Hermes-RISC Processor","authors":"Mertoguno S.J., Bourbakis N.G.","doi":"10.1006/jmca.1995.0017","DOIUrl":"https://doi.org/10.1006/jmca.1995.0017","url":null,"abstract":"<div><p>This paper presents the structural design and the functional characteristics of a RISC processor called Hermes-RISC. The design of the Hermes-RISC processor is based on the study and evaluation of a variety of assembly instruction sets. The Hermes-RISC is a pipeline superscalar RISC processor with four superscalar units. The first stage evaluation of the Hermes-RISC performance is also presented here. This evaluation is based on the execution of a set of primitive processing tasks, such as summation, multiplication of numbers, multiplication of matrices, sorting, finding maximum values among a set of numbers, procedure calls, etc. Moreover, the performance of Hermes-RISC is compared with a variety of RISC processors.</p></div>","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"18 3","pages":"Pages 233-259"},"PeriodicalIF":0.0,"publicationDate":"1995-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1006/jmca.1995.0017","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71740258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes an implementation method for object-oriented applications. In the common practice the base address of the current object instance is passed on the stack as a pointer from one virtual method to another. The way suggested in this paper uses a global pointer pointing to the currently active object. This pointer is implemented by using some of the CPU registers exclusively for this purpose, thus saving the time of reloading it. Provided that some instructions manipulate on the same object instance before the program switches to another object a smaller and faster executing code can be achieved and at the same time some stack space can be saved.
{"title":"Implementation of object-oriented programming via register based pointer","authors":"A. Zsótér","doi":"10.1006/JMCA.1995.0019","DOIUrl":"https://doi.org/10.1006/JMCA.1995.0019","url":null,"abstract":"This paper describes an implementation method for object-oriented applications. In the common practice the base address of the current object instance is passed on the stack as a pointer from one virtual method to another. The way suggested in this paper uses a global pointer pointing to the currently active object. This pointer is implemented by using some of the CPU registers exclusively for this purpose, thus saving the time of reloading it. Provided that some instructions manipulate on the same object instance before the program switches to another object a smaller and faster executing code can be achieved and at the same time some stack space can be saved.","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"34 1","pages":"279-285"},"PeriodicalIF":0.0,"publicationDate":"1995-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86541161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the structural design and the functional characteristics of a RISC processor called Hermes-RISC. The design of the Hermes-RISC processor is based on the study and evaluation of a variety of assembly instruction sets. The Hermes-RISC is a pipeline superscalar RISC processor with four superscalar units. The first stage evaluation of the Hermes-RISC performance is also presented here. This evaluation is based on the execution of a set of primitive processing tasks, such as summation, multiplication of numbers, multiplication of matrices, sorting, finding maximum values among a set of numbers, procedure calls, etc. Moreover, the performance of Hermes-RISC is compared with a variety of RISC processors.
{"title":"Design of the Hermes-RISC processor","authors":"S. Mertoguno, N. Bourbakis","doi":"10.1006/JMCA.1995.0017","DOIUrl":"https://doi.org/10.1006/JMCA.1995.0017","url":null,"abstract":"This paper presents the structural design and the functional characteristics of a RISC processor called Hermes-RISC. The design of the Hermes-RISC processor is based on the study and evaluation of a variety of assembly instruction sets. The Hermes-RISC is a pipeline superscalar RISC processor with four superscalar units. The first stage evaluation of the Hermes-RISC performance is also presented here. This evaluation is based on the execution of a set of primitive processing tasks, such as summation, multiplication of numbers, multiplication of matrices, sorting, finding maximum values among a set of numbers, procedure calls, etc. Moreover, the performance of Hermes-RISC is compared with a variety of RISC processors.","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"88 1","pages":"233-259"},"PeriodicalIF":0.0,"publicationDate":"1995-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84857550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an efficient architecture for the rendering and display sections of a vehicle simulator prototype. The architecture for the rendering stage, which consists of three independent concurrent units, has been optimised to support the two-layer dynamic load balancing technique. The display stage has also been partitioned to facilitate parallel updating of the pixel data to the dual frame buffers. The design of the frame buffers and the interface logic to access them by direct memory access (DMA) controllers (via three common address and data buses) and the colour video controller are also presented. Simulation results show that the adoption of DMA based memory transfer between the local memory of the transputer nodes and the frame buffers can alleviate the communication bottleneck prevalent in an earlier prototype.
{"title":"An efficient architecture for a transputer based vehicle simulator","authors":"T. Srikanthan, K. Chan, S. K. Leong","doi":"10.1006/JMCA.1995.0015","DOIUrl":"https://doi.org/10.1006/JMCA.1995.0015","url":null,"abstract":"This paper presents an efficient architecture for the rendering and display sections of a vehicle simulator prototype. The architecture for the rendering stage, which consists of three independent concurrent units, has been optimised to support the two-layer dynamic load balancing technique. The display stage has also been partitioned to facilitate parallel updating of the pixel data to the dual frame buffers. The design of the frame buffers and the interface logic to access them by direct memory access (DMA) controllers (via three common address and data buses) and the colour video controller are also presented. Simulation results show that the adoption of DMA based memory transfer between the local memory of the transputer nodes and the frame buffers can alleviate the communication bottleneck prevalent in an earlier prototype.","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"73 4 1","pages":"203-213"},"PeriodicalIF":0.0,"publicationDate":"1995-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84722719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Today 's requirements for computational power are still not satisfied. One answer for this demand is expensive supercomputers. Another attempt is the collection of computational power in a network. Connected workstations operate for parallel computation. Our approach for collecting unused resources in workstation clusters enables dynamic distribution of computational load over the network. Any computer individually distinguishes the amount of server resources sharing for others in the network. Our architecture is based on the client /server model —clients divide potentially hard problems into sub problems and forward them to different servers in the network. The usage of standardized remote procedure calls (rpc) as the basic mechanism for transmission of data between the workstations allows the extension of the concept for heterogeneous environments. This article gives a discussion of our implementation for Windows NT and presents the latest benchmarks with two special parallel applications.
{"title":"Parallel computation with dynamic load distribution for locally distributed Windows NT environments","authors":"Gerhard Eschelbeck","doi":"10.1006/jmca.1995.0014","DOIUrl":"https://doi.org/10.1006/jmca.1995.0014","url":null,"abstract":"<div><p>Today 's requirements for computational power are still not satisfied. One answer for this demand is expensive supercomputers. Another attempt is the collection of computational power in a network. Connected workstations operate for parallel computation. Our approach for collecting unused resources in workstation clusters enables dynamic distribution of computational load over the network. Any computer individually distinguishes the amount of server resources sharing for others in the network. Our architecture is based on the client /server model —clients divide potentially hard problems into sub problems and forward them to different servers in the network. The usage of standardized remote procedure calls (rpc) as the basic mechanism for transmission of data between the workstations allows the extension of the concept for heterogeneous environments. This article gives a discussion of our implementation for Windows NT and presents the latest benchmarks with two special parallel applications.</p></div>","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"18 3","pages":"Pages 193-201"},"PeriodicalIF":0.0,"publicationDate":"1995-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1006/jmca.1995.0014","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71740255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}