Pub Date : 2005-10-10DOI: 10.1109/DCAS.2005.1611173
S. Sangameswaran, S. Yamauchi
Current sub-100 nanometer processes employ complex multilayer metallization structures with advanced dielectric materials. Closely-spaced thin, tall metal interconnects with low voltage and fast-clocking edges lead to circuit performances dominated by parasitic delays. Various issues such as noise and delay associated with cross-talk due to coupling capacitances; IR drop effects in the low power supply operating regimes; high current density causing electromigration in narrow interconnect structures; and DC path leakage currents are becoming very common effects in recent mixed-signal designs. Full-chip, post-layout simulation with extracted parasitic components is required in the design flow to accurately analyze each of these effects. Due to the presence of a large amount of parasitics, it is important to extract appropriate parasitics for the relevant process corners and perform the analysis. Fast-spice simulator-based flows are becoming prevalent due to their capacity and efficiency in handling large amounts of data. In this paper, we discuss various options available for designers using fast-spice simulators (e.g. UltraSim, NanoSim, and HSIM) for post-layout simulations, and how these options affect the end results. We have simulated the design with 2.5 million RC elements in 13 hours using a fast-spice simulator. A few examples of post-layout simulations carried out on designs will be discussed.
{"title":"Post-layout parasitic verification methodology for mixed-signal designs using fast-SPICE simulators","authors":"S. Sangameswaran, S. Yamauchi","doi":"10.1109/DCAS.2005.1611173","DOIUrl":"https://doi.org/10.1109/DCAS.2005.1611173","url":null,"abstract":"Current sub-100 nanometer processes employ complex multilayer metallization structures with advanced dielectric materials. Closely-spaced thin, tall metal interconnects with low voltage and fast-clocking edges lead to circuit performances dominated by parasitic delays. Various issues such as noise and delay associated with cross-talk due to coupling capacitances; IR drop effects in the low power supply operating regimes; high current density causing electromigration in narrow interconnect structures; and DC path leakage currents are becoming very common effects in recent mixed-signal designs. Full-chip, post-layout simulation with extracted parasitic components is required in the design flow to accurately analyze each of these effects. Due to the presence of a large amount of parasitics, it is important to extract appropriate parasitics for the relevant process corners and perform the analysis. Fast-spice simulator-based flows are becoming prevalent due to their capacity and efficiency in handling large amounts of data. In this paper, we discuss various options available for designers using fast-spice simulators (e.g. UltraSim, NanoSim, and HSIM) for post-layout simulations, and how these options affect the end results. We have simulated the design with 2.5 million RC elements in 13 hours using a fast-spice simulator. A few examples of post-layout simulations carried out on designs will be discussed.","PeriodicalId":101603,"journal":{"name":"2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123704275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-10DOI: 10.1109/DCAS.2005.1611174
I. Bashir, R. Staszewski, O. Eliezer, E. de-Obaldia
The advantages of having an on-chip system for measuring critical RF performance parameters are endless. With this capability, millions of ICs can be tested using a low cost tester while benefiting from an increase in test coverage and a reduction in test time and cost in a production environment. Another significant benefit is in the factory calibration procedures of critical device settings before deployment. Finally, this capability can allow the wireless terminal to periodically log performance results in flash memory from which they can be retrieved during the repair of a damaged unit easing debug analysis by the manufacturer. This paper presents a novel method of executing on-chip low-cost performance and compliance testing of a local oscillator and transmitter in a wireless transceiver. The presented techniques have been implemented and successfully tested in a Texas Instruments commercial 130 nm CMOS single-chip Bluetooth radio and are being redefined for the 90nm single-chip GSM radio.
{"title":"Built-in self testing (BIST) of RF performance in a system-on-chip (SoC)","authors":"I. Bashir, R. Staszewski, O. Eliezer, E. de-Obaldia","doi":"10.1109/DCAS.2005.1611174","DOIUrl":"https://doi.org/10.1109/DCAS.2005.1611174","url":null,"abstract":"The advantages of having an on-chip system for measuring critical RF performance parameters are endless. With this capability, millions of ICs can be tested using a low cost tester while benefiting from an increase in test coverage and a reduction in test time and cost in a production environment. Another significant benefit is in the factory calibration procedures of critical device settings before deployment. Finally, this capability can allow the wireless terminal to periodically log performance results in flash memory from which they can be retrieved during the repair of a damaged unit easing debug analysis by the manufacturer. This paper presents a novel method of executing on-chip low-cost performance and compliance testing of a local oscillator and transmitter in a wireless transceiver. The presented techniques have been implemented and successfully tested in a Texas Instruments commercial 130 nm CMOS single-chip Bluetooth radio and are being redefined for the 90nm single-chip GSM radio.","PeriodicalId":101603,"journal":{"name":"2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132429916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-10DOI: 10.1109/DCAS.2005.1611175
M. Kinyua, F. Maloberti, W. Gosne
This paper describes a 14-bit 20MSPS switched-capacitor pipelined ADC that employs digital background calibration to correct capacitor mismatch. The calibration concept is amenable to implementation in SOC because it is digital in nature. The calibration concept is demonstrated offline though in principle it can be included on-chip. The calibration can also be performed periodically, thus is inherently able to track the operating conditions of the device. Implementation is in a complimentary bipolar process. The prototype exhibits typical INL of /spl plusmn/ 2.0 LSB, DNL of /spl plusmn/ 0.4 LSB, SNR of 73 dB and SFDR of 85 dB with a 2 MHz input signal. Analog power is about 500 mW with 5 V supply.
{"title":"A 14-bit 20-msamples/s pipelined A/D converter with digital background calibration","authors":"M. Kinyua, F. Maloberti, W. Gosne","doi":"10.1109/DCAS.2005.1611175","DOIUrl":"https://doi.org/10.1109/DCAS.2005.1611175","url":null,"abstract":"This paper describes a 14-bit 20MSPS switched-capacitor pipelined ADC that employs digital background calibration to correct capacitor mismatch. The calibration concept is amenable to implementation in SOC because it is digital in nature. The calibration concept is demonstrated offline though in principle it can be included on-chip. The calibration can also be performed periodically, thus is inherently able to track the operating conditions of the device. Implementation is in a complimentary bipolar process. The prototype exhibits typical INL of /spl plusmn/ 2.0 LSB, DNL of /spl plusmn/ 0.4 LSB, SNR of 73 dB and SFDR of 85 dB with a 2 MHz input signal. Analog power is about 500 mW with 5 V supply.","PeriodicalId":101603,"journal":{"name":"2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126036191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-10DOI: 10.1109/DCAS.2005.1611165
M. Keating
{"title":"Toward Zero-Detect Design: Managing Functional Complexity in the Era of Multi-Million-Gate Design","authors":"M. Keating","doi":"10.1109/DCAS.2005.1611165","DOIUrl":"https://doi.org/10.1109/DCAS.2005.1611165","url":null,"abstract":"","PeriodicalId":101603,"journal":{"name":"2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs","volume":"2 3438 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134111774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-10DOI: 10.1109/DCAS.2005.1611172
V. Parikh, G. Feygin, P. Balsara, S. Rezeq, R. Staszewski, S. Vemulapalli, O. Eliezer
Digital sigma-delta modulators are used extensively in CMOS wireless SoC designs to achieve high-resolution data conversion while controlling the quantization noise spectrum. This paper presents an implementation of a 90 nm CMOS digital band-pass sigma-delta modulator (SDM), running at 900 MHz. Conventional sigma-delta structures required to achieve such noise shaping are hardware intensive and do not meet the timing requirements when synthesized in 90 nm technology using a static CMOS implementation. In this work, we present an unrolled /spl Sigma//spl Delta/ architecture to achieve the necessary rate of operation. Unrolling is achieved by running two loops at half the frequency, while maintaining algorithmic equivalency between the original and proposed structures. The proposed architecture meets timing requirements of 900 MHz across all PVT corners at the cost of increase in area. The operating frequency for most of the hardware is halved, resulting in a 20% power consumption reduction.
{"title":"Implementation of a high speed digital band-pass sigma-delta modulator for a wireless transmitter","authors":"V. Parikh, G. Feygin, P. Balsara, S. Rezeq, R. Staszewski, S. Vemulapalli, O. Eliezer","doi":"10.1109/DCAS.2005.1611172","DOIUrl":"https://doi.org/10.1109/DCAS.2005.1611172","url":null,"abstract":"Digital sigma-delta modulators are used extensively in CMOS wireless SoC designs to achieve high-resolution data conversion while controlling the quantization noise spectrum. This paper presents an implementation of a 90 nm CMOS digital band-pass sigma-delta modulator (SDM), running at 900 MHz. Conventional sigma-delta structures required to achieve such noise shaping are hardware intensive and do not meet the timing requirements when synthesized in 90 nm technology using a static CMOS implementation. In this work, we present an unrolled /spl Sigma//spl Delta/ architecture to achieve the necessary rate of operation. Unrolling is achieved by running two loops at half the frequency, while maintaining algorithmic equivalency between the original and proposed structures. The proposed architecture meets timing requirements of 900 MHz across all PVT corners at the cost of increase in area. The operating frequency for most of the hardware is halved, resulting in a 20% power consumption reduction.","PeriodicalId":101603,"journal":{"name":"2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126874465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：