Pub Date : 2014-12-01DOI: 10.1109/PCCC.2014.7017043
Hojae Lee, Beom Kwon, Seonghyun Kim, Inwoong Lee, Sanghoon Lee
In this paper, we investigate efficient multi-cell cooperation based on CoMP-joint processing and transmission (CoMP-JPT) with orthogonal beamforming. Through the use of a combinatorial optimization algorithm, the optimal user scheduling for joint transmission using multiple transmitters is accomplished. The throughput of the CoMP-JPT can be significantly improved while maintaining fairness among users over a multi-cell environment.
{"title":"Combinatorial JPT based on orthogonal beamforming for two-cell cooperation","authors":"Hojae Lee, Beom Kwon, Seonghyun Kim, Inwoong Lee, Sanghoon Lee","doi":"10.1109/PCCC.2014.7017043","DOIUrl":"https://doi.org/10.1109/PCCC.2014.7017043","url":null,"abstract":"In this paper, we investigate efficient multi-cell cooperation based on CoMP-joint processing and transmission (CoMP-JPT) with orthogonal beamforming. Through the use of a combinatorial optimization algorithm, the optimal user scheduling for joint transmission using multiple transmitters is accomplished. The throughput of the CoMP-JPT can be significantly improved while maintaining fairness among users over a multi-cell environment.","PeriodicalId":105442,"journal":{"name":"2014 IEEE 33rd International Performance Computing and Communications Conference (IPCCC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114180292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/PCCC.2014.7017069
Gilbert Breves Martins, Rosiane de Freitas, E. Souto
The traditional way to identify malicious programs is to compare the code body with a set of previously stored code patterns, also known as signatures, extracted from already identified malware code. To nullify this identification process, the malware developers can insert in their creations the ability to modify the malware code when the next contamination process takes place, using obfuscation techniques. One way to deal with this metamorphic malware behavior is the use of dependency graphs, generated by surveying dependency relationships among code elements, creating a model that is resilient to code mutations. Analog to the signature model, a matching procedure that compares these graphs with a reference graph database is used to identify a malware code. Since graph matching is a NP-hard problem, it is necessary to find ways to optimize this process, so this identification technique can be applied. Using dependency graphs extracted from binary code, we present an approach to reduce the size of the reference dependency graphs stored on the graph database, by introducing a node differentiation based on its features. This way, in conjunction with the insertion of virtual paths, it is possible to build a virtual clique used to identify and dispose of less relevant elements of the original graph. The use of dependency graph reduction also produces more stable results in the matching process. To validate these statements, we present a methodology for generating these graphs from binary programs and compare the results achieved with and without the proposed approach in the identification of the Evol and Polip metamorphic malware.
{"title":"Virtual structures and heterogeneous nodes in dependency graphs for detecting metamorphic malware","authors":"Gilbert Breves Martins, Rosiane de Freitas, E. Souto","doi":"10.1109/PCCC.2014.7017069","DOIUrl":"https://doi.org/10.1109/PCCC.2014.7017069","url":null,"abstract":"The traditional way to identify malicious programs is to compare the code body with a set of previously stored code patterns, also known as signatures, extracted from already identified malware code. To nullify this identification process, the malware developers can insert in their creations the ability to modify the malware code when the next contamination process takes place, using obfuscation techniques. One way to deal with this metamorphic malware behavior is the use of dependency graphs, generated by surveying dependency relationships among code elements, creating a model that is resilient to code mutations. Analog to the signature model, a matching procedure that compares these graphs with a reference graph database is used to identify a malware code. Since graph matching is a NP-hard problem, it is necessary to find ways to optimize this process, so this identification technique can be applied. Using dependency graphs extracted from binary code, we present an approach to reduce the size of the reference dependency graphs stored on the graph database, by introducing a node differentiation based on its features. This way, in conjunction with the insertion of virtual paths, it is possible to build a virtual clique used to identify and dispose of less relevant elements of the original graph. The use of dependency graph reduction also produces more stable results in the matching process. To validate these statements, we present a methodology for generating these graphs from binary programs and compare the results achieved with and without the proposed approach in the identification of the Evol and Polip metamorphic malware.","PeriodicalId":105442,"journal":{"name":"2014 IEEE 33rd International Performance Computing and Communications Conference (IPCCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122106215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/PCCC.2014.7017048
Chok M. Yip, A. Asaduzzaman
Both size and computational activities of Vehicular Area Network (VANET) are growing. Simulation of VANETs not only requires the simulation of network standards, but also requires the mobility of nodes. Such a dynamic system involves computations of node distances, routing protocols, application layers, data send, data receive, etc. The simulation model of VANET requires both hardware and software supports to deal with massive computational problems. Currently available network simulators, like Network Simulator 3 (NS-3), are not adequate for simulating large-scale VANET systems. In this work, we propose a Compute Unified Device Architecture (CUDA)-assisted VANET simulation model for multicore Central Processing Unit (CPU) / manycore Graphics Processing Unit (GPU) platform to increase computational throughput. The proposed VANET/GPU simulator uses NS-3 as the core engine and improves throughput by exploiting massively parallel processing on the GPU. Experimental results show that the overall computation speedup can be increased up to 129x by using the proposed VANET/GPU simulator.
{"title":"A promising CUDA-accelerated vehicular area network simulator using NS-3","authors":"Chok M. Yip, A. Asaduzzaman","doi":"10.1109/PCCC.2014.7017048","DOIUrl":"https://doi.org/10.1109/PCCC.2014.7017048","url":null,"abstract":"Both size and computational activities of Vehicular Area Network (VANET) are growing. Simulation of VANETs not only requires the simulation of network standards, but also requires the mobility of nodes. Such a dynamic system involves computations of node distances, routing protocols, application layers, data send, data receive, etc. The simulation model of VANET requires both hardware and software supports to deal with massive computational problems. Currently available network simulators, like Network Simulator 3 (NS-3), are not adequate for simulating large-scale VANET systems. In this work, we propose a Compute Unified Device Architecture (CUDA)-assisted VANET simulation model for multicore Central Processing Unit (CPU) / manycore Graphics Processing Unit (GPU) platform to increase computational throughput. The proposed VANET/GPU simulator uses NS-3 as the core engine and improves throughput by exploiting massively parallel processing on the GPU. Experimental results show that the overall computation speedup can be increased up to 129x by using the proposed VANET/GPU simulator.","PeriodicalId":105442,"journal":{"name":"2014 IEEE 33rd International Performance Computing and Communications Conference (IPCCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123967080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As the soul of the Software-Defined Networking (SDN), the quality of control plane applications determines the reliability of the networks. Unfortunately, better programmability in SDN increases the risk of bugs and challenges for testing. Because manually testing seems to be inefficient, automatic testing methods become promising alternative. Both white-box method with models and black-box method without model have limitations. In this paper, we propose a formal model for blackbox testing of SDN applications. We use a group of components to describe the data structure stored in the applications and the system behaviors. It is easier and more natural to specify applications. Based on our models, we present our work-in-progress testing framework. It can iteratively improve the design model with model verification and expose implement bugs with model-based testing.
{"title":"Test oriented formal model of SDN applications","authors":"Jiangyuan Yao, Zhiliang Wang, Xia Yin, Xingang Shi, Jianping Wu, Yahui Li","doi":"10.1109/PCCC.2014.7017024","DOIUrl":"https://doi.org/10.1109/PCCC.2014.7017024","url":null,"abstract":"As the soul of the Software-Defined Networking (SDN), the quality of control plane applications determines the reliability of the networks. Unfortunately, better programmability in SDN increases the risk of bugs and challenges for testing. Because manually testing seems to be inefficient, automatic testing methods become promising alternative. Both white-box method with models and black-box method without model have limitations. In this paper, we propose a formal model for blackbox testing of SDN applications. We use a group of components to describe the data structure stored in the applications and the system behaviors. It is easier and more natural to specify applications. Based on our models, we present our work-in-progress testing framework. It can iteratively improve the design model with model verification and expose implement bugs with model-based testing.","PeriodicalId":105442,"journal":{"name":"2014 IEEE 33rd International Performance Computing and Communications Conference (IPCCC)","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124279820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/PCCC.2014.7017040
B. Ries, Walter Unger, M. Odendahl, R. Leupers
In the past memory allocation and communication between processors and memories in current MPSoC's, due to the small design space, was not a big challenge. Through advanced MPSoC's and improving techniques to interface Dynamic RAM (DRAM), allocation of logical data buffers to physical memories is no longer manageable manually. We present a heuristic for the mapping of logical data buffers to physical memories and the routing of data flows. Our heuristic use an approximation scheme to obtain an fractional solution, and randomized rounding. We evaluate our implementation for different values of e using representative data of the Long Term Evolution Standard.
{"title":"A heuristic for logical data buffer allocation in multicore platforms","authors":"B. Ries, Walter Unger, M. Odendahl, R. Leupers","doi":"10.1109/PCCC.2014.7017040","DOIUrl":"https://doi.org/10.1109/PCCC.2014.7017040","url":null,"abstract":"In the past memory allocation and communication between processors and memories in current MPSoC's, due to the small design space, was not a big challenge. Through advanced MPSoC's and improving techniques to interface Dynamic RAM (DRAM), allocation of logical data buffers to physical memories is no longer manageable manually. We present a heuristic for the mapping of logical data buffers to physical memories and the routing of data flows. Our heuristic use an approximation scheme to obtain an fractional solution, and randomized rounding. We evaluate our implementation for different values of e using representative data of the Long Term Evolution Standard.","PeriodicalId":105442,"journal":{"name":"2014 IEEE 33rd International Performance Computing and Communications Conference (IPCCC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126296980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/PCCC.2014.7017090
Martin Alfranseder, Michael Deubzer, Benjamin Justus, J. Mottok, Christian Siemers
We present in this paper a new lock-based resource sharing protocol PWLP (Preemptable Waiting Locking Protocol) for embedded multi-core processors. It is based on the busy-wait model and works with non-preemptive critical sections while task may be preempted by tasks with a higher priority when waiting for resources. Our protocol can be applied in partitioned as well as global scheduling scenarios, in which task-fix, job-fix or dynamically assigned priorities may be used. Furthermore, the PWLP permits nested requests to shared resources. Finally, we present a case study based on event-based simulations in which the FMLP (Flexible Multiprocessor Locking Protocol) and the proposed PWLP are compared.
{"title":"An efficient spin-lock based multi-core resource sharing protocol","authors":"Martin Alfranseder, Michael Deubzer, Benjamin Justus, J. Mottok, Christian Siemers","doi":"10.1109/PCCC.2014.7017090","DOIUrl":"https://doi.org/10.1109/PCCC.2014.7017090","url":null,"abstract":"We present in this paper a new lock-based resource sharing protocol PWLP (Preemptable Waiting Locking Protocol) for embedded multi-core processors. It is based on the busy-wait model and works with non-preemptive critical sections while task may be preempted by tasks with a higher priority when waiting for resources. Our protocol can be applied in partitioned as well as global scheduling scenarios, in which task-fix, job-fix or dynamically assigned priorities may be used. Furthermore, the PWLP permits nested requests to shared resources. Finally, we present a case study based on event-based simulations in which the FMLP (Flexible Multiprocessor Locking Protocol) and the proposed PWLP are compared.","PeriodicalId":105442,"journal":{"name":"2014 IEEE 33rd International Performance Computing and Communications Conference (IPCCC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131140439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/PCCC.2014.7017062
Shuhui Li, Miao Song, P. Wan, Shangping Ren
For a time-sensitive application, the usefulness or the quality of the application's end result depends on the time when the result is delivered, or when the application is completed. A Time Utility Function (TUF) is often used to represent the dependency between an application's accrued value and its completion time. For parallel and time-sensitive applications, each application has multiple tasks that must be executed concurrently in order to produce a result. Therefore, their execution occupies resources in two dimensions: spatial, i.e., the number of processing units needed to support concurrent tasks, and temporal, i.e., time duration needed to complete the application. Because of the parallelism and time-sensitive features of the applications, the execution interference among parallel and time-sensitive applications can be both in spatial and temporal domains. In this paper, we first introduce a metric to measure the spatial-temporal interference on applications' accrued values. Second, based on the metric, we develop a scheduling algorithm, i.e., the Discounting Spatial-Temporal Interference (DSTI) scheduling algorithm, to maximize system's total accrued utility value for a given set of parallel and time-sensitive applications. Our simulation results show that the proposed DSTI algorithm results in close to optimal solutions and also has clear advantage over existing approaches in the literature in terms of system total accrued utility values and profitable application ratio. It accrues up to 164%, 150%, and 97% more system value, and up to 21%, 35%, and 18% higher profitable application ratio than the Gang EDF, the FCFS with backfilling, and the 0-1 Knapsack based scheduling algorithms, respectively.
{"title":"Maximizing system's total accrued utility value for parallel and time-sensitive applications","authors":"Shuhui Li, Miao Song, P. Wan, Shangping Ren","doi":"10.1109/PCCC.2014.7017062","DOIUrl":"https://doi.org/10.1109/PCCC.2014.7017062","url":null,"abstract":"For a time-sensitive application, the usefulness or the quality of the application's end result depends on the time when the result is delivered, or when the application is completed. A Time Utility Function (TUF) is often used to represent the dependency between an application's accrued value and its completion time. For parallel and time-sensitive applications, each application has multiple tasks that must be executed concurrently in order to produce a result. Therefore, their execution occupies resources in two dimensions: spatial, i.e., the number of processing units needed to support concurrent tasks, and temporal, i.e., time duration needed to complete the application. Because of the parallelism and time-sensitive features of the applications, the execution interference among parallel and time-sensitive applications can be both in spatial and temporal domains. In this paper, we first introduce a metric to measure the spatial-temporal interference on applications' accrued values. Second, based on the metric, we develop a scheduling algorithm, i.e., the Discounting Spatial-Temporal Interference (DSTI) scheduling algorithm, to maximize system's total accrued utility value for a given set of parallel and time-sensitive applications. Our simulation results show that the proposed DSTI algorithm results in close to optimal solutions and also has clear advantage over existing approaches in the literature in terms of system total accrued utility values and profitable application ratio. It accrues up to 164%, 150%, and 97% more system value, and up to 21%, 35%, and 18% higher profitable application ratio than the Gang EDF, the FCFS with backfilling, and the 0-1 Knapsack based scheduling algorithms, respectively.","PeriodicalId":105442,"journal":{"name":"2014 IEEE 33rd International Performance Computing and Communications Conference (IPCCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123754439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/PCCC.2014.7017091
Tosiron Adegbija, A. Gordon-Ross, M. Rawlins
Due to the memory hierarchy's large contribution to a microprocessor's total power, cache tuning is an ideal method for optimizing overall power consumption in embedded systems. Since most embedded systems are power and area constrained, the hardware and/or software that orchestrate cache tuning - the cache tuner - must not impose significant power and area overhead. Furthermore, as embedded systems increasingly trend towards multicore, inter-core data sharing, communication, and synchronization impose additional cache tuner design complexity, necessitating cross-core cache tuning coordination. In order to minimize cache tuner overhead, cache tuner design must consider these overheads and scalability. Whereas prior work proposes low-overhead cache tuners, scalability to multicore systems requires additional considerations. In this work, we present a low-overhead, scalable cache tuner and extensively evaluate various cache tuner design tradeoffs with respect to power and area for constrained multicore embedded systems. Based on our analysis, we formulate valuable insights and designer-assisted guidelines for modeling scalable and efficient cache tuners that best achieve optimization goals while maintaining power and area constraints.
{"title":"Analysis of cache tuner architectural layouts for multicore embedded systems","authors":"Tosiron Adegbija, A. Gordon-Ross, M. Rawlins","doi":"10.1109/PCCC.2014.7017091","DOIUrl":"https://doi.org/10.1109/PCCC.2014.7017091","url":null,"abstract":"Due to the memory hierarchy's large contribution to a microprocessor's total power, cache tuning is an ideal method for optimizing overall power consumption in embedded systems. Since most embedded systems are power and area constrained, the hardware and/or software that orchestrate cache tuning - the cache tuner - must not impose significant power and area overhead. Furthermore, as embedded systems increasingly trend towards multicore, inter-core data sharing, communication, and synchronization impose additional cache tuner design complexity, necessitating cross-core cache tuning coordination. In order to minimize cache tuner overhead, cache tuner design must consider these overheads and scalability. Whereas prior work proposes low-overhead cache tuners, scalability to multicore systems requires additional considerations. In this work, we present a low-overhead, scalable cache tuner and extensively evaluate various cache tuner design tradeoffs with respect to power and area for constrained multicore embedded systems. Based on our analysis, we formulate valuable insights and designer-assisted guidelines for modeling scalable and efficient cache tuners that best achieve optimization goals while maintaining power and area constraints.","PeriodicalId":105442,"journal":{"name":"2014 IEEE 33rd International Performance Computing and Communications Conference (IPCCC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127856427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/PCCC.2014.7017058
J. Niu, Shaluo Huang, Milica Stojmenovic
We investigate the group growth in online social networks, by analyzing six different user groups (two million users in total) in Douban Network. The size and longevity of posts in the Douban dataset demonstrate a power-law distribution with exponential cutoff and heavy tail, respectively. The frequency of user interactions follows a two-stage power-law distribution, which can distinguish different types of users. The growth of the number of users and the number of posts/replies generated by the users in a given and same time period, in each group, follow an exponential pattern at the initial stage and oscillate dramatically during the rest of the processes. The number of posts/replies has a power-law relation with the number of active users within a period of time. We propose an empirical growth model, Twisted Growth (TG), to portray the relation between the number of users and the amount of the contents they generated. The model derives equations based on the historical data for deciding coefficients, and the assumtion that the contents in one group will attract new users to join, which will lead to growth of users. Further, the newcomers together with original users will create new contents. We validate our TG model through theoretical analysis and simulations over real datasets.
{"title":"Patterns and modeling of group growth in online social networks","authors":"J. Niu, Shaluo Huang, Milica Stojmenovic","doi":"10.1109/PCCC.2014.7017058","DOIUrl":"https://doi.org/10.1109/PCCC.2014.7017058","url":null,"abstract":"We investigate the group growth in online social networks, by analyzing six different user groups (two million users in total) in Douban Network. The size and longevity of posts in the Douban dataset demonstrate a power-law distribution with exponential cutoff and heavy tail, respectively. The frequency of user interactions follows a two-stage power-law distribution, which can distinguish different types of users. The growth of the number of users and the number of posts/replies generated by the users in a given and same time period, in each group, follow an exponential pattern at the initial stage and oscillate dramatically during the rest of the processes. The number of posts/replies has a power-law relation with the number of active users within a period of time. We propose an empirical growth model, Twisted Growth (TG), to portray the relation between the number of users and the amount of the contents they generated. The model derives equations based on the historical data for deciding coefficients, and the assumtion that the contents in one group will attract new users to join, which will lead to growth of users. Further, the newcomers together with original users will create new contents. We validate our TG model through theoretical analysis and simulations over real datasets.","PeriodicalId":105442,"journal":{"name":"2014 IEEE 33rd International Performance Computing and Communications Conference (IPCCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130674294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/PCCC.2014.7017053
Shijie Zhou, Weirong Jiang, V. Prasanna
Software Defined Networking (SDN) has been proposed as a flexible solution for the next generation Internet provision. OpenFlow is a pioneering protocol for SDN which enables a hardware data plane to be managed by a software-based controller in a standard way. In this paper, we present a hardware-software co-design approach of an OpenFlow switch using a state-of-the-art heterogeneous system-on-chip (SoC) platform. Specifically, we implement the OpenFlow switch on a Xilinx Zynq ZC706 board. The Xilinx Zynq SoC family provides a tight coupling of field programmable gate array (FPGA) fabric and ARM processor cores, making it an attractive on-chip implementation platform for SDN switches. High-performance, yet highly-programmable, data plane processing can reside in programmable logic, while complex control software can reside in ARM processor. Our proposed architecture involves a methodology that scales across: (a) a range of possible packet throughput rates and (b) a range of possible flow table sizes. Post-place-and-route results show that our design targeted at Xilinx Zynq can achieve a total 88 Gbps throughput for a 1K flow table which supports dynamic and hitless updates. Correct operation has been demonstrated using a ZC706 board.
{"title":"A flexible and scalable high-performance OpenFlow switch on heterogeneous SoC platforms","authors":"Shijie Zhou, Weirong Jiang, V. Prasanna","doi":"10.1109/PCCC.2014.7017053","DOIUrl":"https://doi.org/10.1109/PCCC.2014.7017053","url":null,"abstract":"Software Defined Networking (SDN) has been proposed as a flexible solution for the next generation Internet provision. OpenFlow is a pioneering protocol for SDN which enables a hardware data plane to be managed by a software-based controller in a standard way. In this paper, we present a hardware-software co-design approach of an OpenFlow switch using a state-of-the-art heterogeneous system-on-chip (SoC) platform. Specifically, we implement the OpenFlow switch on a Xilinx Zynq ZC706 board. The Xilinx Zynq SoC family provides a tight coupling of field programmable gate array (FPGA) fabric and ARM processor cores, making it an attractive on-chip implementation platform for SDN switches. High-performance, yet highly-programmable, data plane processing can reside in programmable logic, while complex control software can reside in ARM processor. Our proposed architecture involves a methodology that scales across: (a) a range of possible packet throughput rates and (b) a range of possible flow table sizes. Post-place-and-route results show that our design targeted at Xilinx Zynq can achieve a total 88 Gbps throughput for a 1K flow table which supports dynamic and hitless updates. Correct operation has been demonstrated using a ZC706 board.","PeriodicalId":105442,"journal":{"name":"2014 IEEE 33rd International Performance Computing and Communications Conference (IPCCC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121372971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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