Pub Date : 1994-02-01DOI: 10.1109/STHERM.1994.288984
J. Albers
A recursion relation technique has been used in the past to determine the surface potential from the multilayer electrical Laplace equation. This has provided for a vastly simplified evaluation of the electrical spreading resistance and four-probe resistance. The isomorphism of the multilayer Laplace equation and the multilayer steady-state heat flow equation suggests the possibility of developing a recursion relation applicable to the multilayer thermal problem. This recursive technique is developed and is shown to provide the surface temperature of the multilayer steady-state heat flow equation. For the three-layer ease, the thermal recursion relation readily yields the surface results which are identical with those presented by Kokkas (1974) and the TXYZ thermal code. This recursive technique can be used with any number of layers while incurring only a small increase in computation time for each added layer. For the case of complete, uniform top surface coverage by a heat source, the technique gives rise to the generalized one-dimensional thermal resistance result. An example of the use of the new recursive method is provided by the preliminary calculations of the surface temperature of a buried oxide (SOI, SIMOX) structure containing several thicknesses of the surface silicon layers. This new technique should prove useful in the investigation and understanding of the steady-state thermal response of modern multilayer microelectronic structures.<>
{"title":"An exact solution of the steady-state surface temperature for a general multilayer structure","authors":"J. Albers","doi":"10.1109/STHERM.1994.288984","DOIUrl":"https://doi.org/10.1109/STHERM.1994.288984","url":null,"abstract":"A recursion relation technique has been used in the past to determine the surface potential from the multilayer electrical Laplace equation. This has provided for a vastly simplified evaluation of the electrical spreading resistance and four-probe resistance. The isomorphism of the multilayer Laplace equation and the multilayer steady-state heat flow equation suggests the possibility of developing a recursion relation applicable to the multilayer thermal problem. This recursive technique is developed and is shown to provide the surface temperature of the multilayer steady-state heat flow equation. For the three-layer ease, the thermal recursion relation readily yields the surface results which are identical with those presented by Kokkas (1974) and the TXYZ thermal code. This recursive technique can be used with any number of layers while incurring only a small increase in computation time for each added layer. For the case of complete, uniform top surface coverage by a heat source, the technique gives rise to the generalized one-dimensional thermal resistance result. An example of the use of the new recursive method is provided by the preliminary calculations of the surface temperature of a buried oxide (SOI, SIMOX) structure containing several thicknesses of the surface silicon layers. This new technique should prove useful in the investigation and understanding of the steady-state thermal response of modern multilayer microelectronic structures.<<ETX>>","PeriodicalId":107140,"journal":{"name":"Proceedings of 1994 IEEE/CHMT 10th Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115575604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-01DOI: 10.1109/STHERM.1994.288997
K. Azar, S. S. Pan, J. Parry, H. Rosten
Natural convection is the most desirable cooling mechanism for electronic enclosures. Limited cooling capacity with natural convection requires identification and optimization of parameters impacting cooling. A set of such parameters is circuit pack layout and board conductivity (circuit board parameters). Hence, experimental and numerical simulations were undertaken to investigate the impact of these parameters on thermal performance of an electronic component in circuit pack setting. Component thermal performance was characterized by its junction to ambient thermal resistance (R/sub ja/), where room ambient was used as the reference temperature. The numerical model was verified against the experimental data with 4 percent agreement between the two analyses. The numerical model was then expanded to include the circuit board parameters. The effects of the spacing and height of the neighboring components, and board conductivity on thermal resistance were investigated. The model consisted of an array of nine components (3/spl times/3), with the center component as the focus of the study. Three values for board conductivity, component spacing and neighboring component height were considered. The data showed that increasing k/sub board/ three folds resulted in 17 percent reduction in R/sub ja/. Similarly, a three fold increase in component spacing reduced the R/sub ja/ by 24 percent. It is deduced that the least junction to ambient thermal resistance was attained when component spacing was 0.023 m (900 mils) and board conductivity was 13.6 W/m/spl deg/K.<>
{"title":"Effect of circuit board parameters on thermal performance of electronic components in natural convection cooling","authors":"K. Azar, S. S. Pan, J. Parry, H. Rosten","doi":"10.1109/STHERM.1994.288997","DOIUrl":"https://doi.org/10.1109/STHERM.1994.288997","url":null,"abstract":"Natural convection is the most desirable cooling mechanism for electronic enclosures. Limited cooling capacity with natural convection requires identification and optimization of parameters impacting cooling. A set of such parameters is circuit pack layout and board conductivity (circuit board parameters). Hence, experimental and numerical simulations were undertaken to investigate the impact of these parameters on thermal performance of an electronic component in circuit pack setting. Component thermal performance was characterized by its junction to ambient thermal resistance (R/sub ja/), where room ambient was used as the reference temperature. The numerical model was verified against the experimental data with 4 percent agreement between the two analyses. The numerical model was then expanded to include the circuit board parameters. The effects of the spacing and height of the neighboring components, and board conductivity on thermal resistance were investigated. The model consisted of an array of nine components (3/spl times/3), with the center component as the focus of the study. Three values for board conductivity, component spacing and neighboring component height were considered. The data showed that increasing k/sub board/ three folds resulted in 17 percent reduction in R/sub ja/. Similarly, a three fold increase in component spacing reduced the R/sub ja/ by 24 percent. It is deduced that the least junction to ambient thermal resistance was attained when component spacing was 0.023 m (900 mils) and board conductivity was 13.6 W/m/spl deg/K.<<ETX>>","PeriodicalId":107140,"journal":{"name":"Proceedings of 1994 IEEE/CHMT 10th Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115839290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-01DOI: 10.1109/STHERM.1994.288991
M. Vogel
Measured thermal performance is presented for a single phase liquid-cooled module. Tape automated bonded (TAB) thermal test chips and their associated substrates are stacked in a compact, 3-dimensional liquid tight module. A dielectric liquid, polyalphaolefin (PAO) is forced to flow past the active and inactive sides of the TAB chips. At a volumetric flowrate of 0.05 gallons per minute (gpm) and an estimated pressure loss less than 0.5 psi. the measured junction-to-liquid thermal resistance is 2.0 C/W for a 0.50"/spl times/0.50"/spl times/0.015" thermal test chip. The thermal resistance was also measured for an indirect liquid cooling approach. PAO was used to cool a miniature sink mounted directly to a 0.50"/spl times/0.50" heat source. The heat source was used to simulate the thermal characteristics of a chip carrier package. Overall dimensions of the liquid heat sink measured 1.0"/spl times/1.0"/spl times/0.28". The measured junction-to-liquid thermal resistance is 0.52 C/W for a flowrate of 0.05 gpm. and for an estimated pressure loss less than 1.0 psi. Numerical computational techniques yielded results which were comparable to the measured thermal resistances for both the 3-dimensional module and the miniature heat sink. Enhanced thermal performance gained by introducing micro encapsulated phase change material to the PAO is estimated for both the 3-dimensional module and the miniature heat sink.<>
{"title":"Liquid cooling performance for a 3-dimensional multichip module and miniature heat sink","authors":"M. Vogel","doi":"10.1109/STHERM.1994.288991","DOIUrl":"https://doi.org/10.1109/STHERM.1994.288991","url":null,"abstract":"Measured thermal performance is presented for a single phase liquid-cooled module. Tape automated bonded (TAB) thermal test chips and their associated substrates are stacked in a compact, 3-dimensional liquid tight module. A dielectric liquid, polyalphaolefin (PAO) is forced to flow past the active and inactive sides of the TAB chips. At a volumetric flowrate of 0.05 gallons per minute (gpm) and an estimated pressure loss less than 0.5 psi. the measured junction-to-liquid thermal resistance is 2.0 C/W for a 0.50\"/spl times/0.50\"/spl times/0.015\" thermal test chip. The thermal resistance was also measured for an indirect liquid cooling approach. PAO was used to cool a miniature sink mounted directly to a 0.50\"/spl times/0.50\" heat source. The heat source was used to simulate the thermal characteristics of a chip carrier package. Overall dimensions of the liquid heat sink measured 1.0\"/spl times/1.0\"/spl times/0.28\". The measured junction-to-liquid thermal resistance is 0.52 C/W for a flowrate of 0.05 gpm. and for an estimated pressure loss less than 1.0 psi. Numerical computational techniques yielded results which were comparable to the measured thermal resistances for both the 3-dimensional module and the miniature heat sink. Enhanced thermal performance gained by introducing micro encapsulated phase change material to the PAO is estimated for both the 3-dimensional module and the miniature heat sink.<<ETX>>","PeriodicalId":107140,"journal":{"name":"Proceedings of 1994 IEEE/CHMT 10th Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127561549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-01DOI: 10.1109/STHERM.1994.288995
H. Shaukatullah, M. Gaynes
Surface mount electronic packages, typically a few millimeters thick, are mounted directly and very close to printed circuit cards. Due to close proximity to the card, the overall thermal performance of the package depends on the thermal conductivity of the circuit cards. For characterizing the thermal performance of surface mount packages, SEMI Specification G42-88 specifies a FR4 card with one layer of circuitry in a fan-out pattern on the package side. To determine the effect of the circuit card conductivity on the thermal performance of surface mount packages, tests were done with a number of different types of packages on two types of cards. The packages were all 28 mm 208-leaded EIAJ/JEDEC type plastic with copper and alloy 42 leadframes, plastic with exposed heat spreader, and metal quad flat packs. One of the test card designs was similar to SEMI Specification card, with only one layer of circuitry in a fan-out pattern on the package side. The other card had two internal copper planes in addition to the fan-out pattern of circuitry on the package side. This paper describes the experimental procedure and discusses the thermal performance of these various surface mount packages on these two types of cards. The data shows that the thermal performance of plastic packages with alloy 42 leadframe is relatively insensitive to the amount of copper in the circuit card. On the other hand, the thermal performance of metal packages shows the most dependence on the amount of copper in the circuit cards.<>
{"title":"Experimental determination of the effect of printed circuit card conductivity on the thermal performance of surface mount electronic packages","authors":"H. Shaukatullah, M. Gaynes","doi":"10.1109/STHERM.1994.288995","DOIUrl":"https://doi.org/10.1109/STHERM.1994.288995","url":null,"abstract":"Surface mount electronic packages, typically a few millimeters thick, are mounted directly and very close to printed circuit cards. Due to close proximity to the card, the overall thermal performance of the package depends on the thermal conductivity of the circuit cards. For characterizing the thermal performance of surface mount packages, SEMI Specification G42-88 specifies a FR4 card with one layer of circuitry in a fan-out pattern on the package side. To determine the effect of the circuit card conductivity on the thermal performance of surface mount packages, tests were done with a number of different types of packages on two types of cards. The packages were all 28 mm 208-leaded EIAJ/JEDEC type plastic with copper and alloy 42 leadframes, plastic with exposed heat spreader, and metal quad flat packs. One of the test card designs was similar to SEMI Specification card, with only one layer of circuitry in a fan-out pattern on the package side. The other card had two internal copper planes in addition to the fan-out pattern of circuitry on the package side. This paper describes the experimental procedure and discusses the thermal performance of these various surface mount packages on these two types of cards. The data shows that the thermal performance of plastic packages with alloy 42 leadframe is relatively insensitive to the amount of copper in the circuit card. On the other hand, the thermal performance of metal packages shows the most dependence on the amount of copper in the circuit cards.<<ETX>>","PeriodicalId":107140,"journal":{"name":"Proceedings of 1994 IEEE/CHMT 10th Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127462227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-01DOI: 10.1109/STHERM.1994.288992
M.R. Cosley, M. J. Marongiu
Thermal management of high power electronic components (chips) with dissipation ratings of over 2-3 W/cm/sup 2/ clearly demands non-traditional means to be successful. Many different approaches have been attempted in the past with varying degrees of success. In the last 8 years radial jet reattachment (RJR) has been proven in the laboratory to be a novel and effective mechanism for high surface heat removal rates with negligible downward force as compared with the commonly-used impinging open jets or in-line-jets. We propose in this report the use of these nozzles, either singly or in a array to cool PCB's from the top or from the bottom. Two typical arrangements for radial nozzle applications are fully discussed here in view of surface pressure and heat transfer characteristics. The discussion is supplemented with experimental work carried out at IIT to provide needed data. Our investigation indicates that high heat transfer rates are indeed achieved using radial nozzles. In general, RJR nozzles produce highest heat transfer rates when placed very close to a surface and for a wider area than for ILJ nozzles, with negligible downward (positive) forces. Typical maximum heat transfer coefficients are for gases, 300-500 W/m/sup 2/-K, and, although the experiments were performed with air, for liquids (no evaporation) the values (based on experimental Stanton numbers) range between 10000 to 50000 W/m/sup 2/-K, depending on the fluid.<>
{"title":"Studies on the use of radial jet reattachment nozzles as active heat sinks for electronic component boards","authors":"M.R. Cosley, M. J. Marongiu","doi":"10.1109/STHERM.1994.288992","DOIUrl":"https://doi.org/10.1109/STHERM.1994.288992","url":null,"abstract":"Thermal management of high power electronic components (chips) with dissipation ratings of over 2-3 W/cm/sup 2/ clearly demands non-traditional means to be successful. Many different approaches have been attempted in the past with varying degrees of success. In the last 8 years radial jet reattachment (RJR) has been proven in the laboratory to be a novel and effective mechanism for high surface heat removal rates with negligible downward force as compared with the commonly-used impinging open jets or in-line-jets. We propose in this report the use of these nozzles, either singly or in a array to cool PCB's from the top or from the bottom. Two typical arrangements for radial nozzle applications are fully discussed here in view of surface pressure and heat transfer characteristics. The discussion is supplemented with experimental work carried out at IIT to provide needed data. Our investigation indicates that high heat transfer rates are indeed achieved using radial nozzles. In general, RJR nozzles produce highest heat transfer rates when placed very close to a surface and for a wider area than for ILJ nozzles, with negligible downward (positive) forces. Typical maximum heat transfer coefficients are for gases, 300-500 W/m/sup 2/-K, and, although the experiments were performed with air, for liquids (no evaporation) the values (based on experimental Stanton numbers) range between 10000 to 50000 W/m/sup 2/-K, depending on the fluid.<<ETX>>","PeriodicalId":107140,"journal":{"name":"Proceedings of 1994 IEEE/CHMT 10th Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133699075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-01DOI: 10.1109/STHERM.1994.288983
A. Bjorneklett, T. Tuhus, H. Kristiansen
A model describing thermal fatigue of large area adhesive joints such as die bonds, has been developed. It is based on equations for crack growth rate and stress distribution in large area joints. The basic assumption of the model is that cracks grow from the edges of the area towards the center. The thermal resistance of the bond layer was calculated by assuming the cracked part of the layer had infinite thermal resistance. The thermal resistance as a function of the number of thermal cycles was predicted to be different for adhesives with low and high modulus of elasticity. Good agreement with previously reported experiments was obtained. The thermal resistance in silver filled die bond adhesives as a function of the number of thermal cycles was measured in these experiments.<>
{"title":"A model for thermal fatigue of large area adhesive joints between materials with dissimilar thermal expansion","authors":"A. Bjorneklett, T. Tuhus, H. Kristiansen","doi":"10.1109/STHERM.1994.288983","DOIUrl":"https://doi.org/10.1109/STHERM.1994.288983","url":null,"abstract":"A model describing thermal fatigue of large area adhesive joints such as die bonds, has been developed. It is based on equations for crack growth rate and stress distribution in large area joints. The basic assumption of the model is that cracks grow from the edges of the area towards the center. The thermal resistance of the bond layer was calculated by assuming the cracked part of the layer had infinite thermal resistance. The thermal resistance as a function of the number of thermal cycles was predicted to be different for adhesives with low and high modulus of elasticity. Good agreement with previously reported experiments was obtained. The thermal resistance in silver filled die bond adhesives as a function of the number of thermal cycles was measured in these experiments.<<ETX>>","PeriodicalId":107140,"journal":{"name":"Proceedings of 1994 IEEE/CHMT 10th Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124649793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-01DOI: 10.1109/STHERM.1994.288987
B. Siegal, M. Berg
Using a variety of surface mount packages, this paper reports the results of using various different methods for improving semiconductor thermal performance. Starting off with a 64-lead Quad Flat Package (QFP), data are presented for several different thermal environment conditions and for several different package variations. The environmental conditions include still-air, heat sink and tape sink. The package variations studied include die attachment thickness, internal drop-in heat spreader, and encapsulant material variations. Data are also presented for two die-on-copper-slug packages (100-lead QFP and 44-lead PLCC) and for a standard (not thermally enhanced) package (56-lead SSOP), under still-air, moving-air, heat sink and tape sink environments.<>
{"title":"An effective alternative for marginal thermal improvements of semiconductor devices","authors":"B. Siegal, M. Berg","doi":"10.1109/STHERM.1994.288987","DOIUrl":"https://doi.org/10.1109/STHERM.1994.288987","url":null,"abstract":"Using a variety of surface mount packages, this paper reports the results of using various different methods for improving semiconductor thermal performance. Starting off with a 64-lead Quad Flat Package (QFP), data are presented for several different thermal environment conditions and for several different package variations. The environmental conditions include still-air, heat sink and tape sink. The package variations studied include die attachment thickness, internal drop-in heat spreader, and encapsulant material variations. Data are also presented for two die-on-copper-slug packages (100-lead QFP and 44-lead PLCC) and for a standard (not thermally enhanced) package (56-lead SSOP), under still-air, moving-air, heat sink and tape sink environments.<<ETX>>","PeriodicalId":107140,"journal":{"name":"Proceedings of 1994 IEEE/CHMT 10th Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134485037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-01DOI: 10.1109/STHERM.1994.288989
B. Guenin
The MQUAD microelectronic package was developed to provide a high level of thermal performance for high leadcount integrated circuits./sup 1/ A numerical, lumped-parameter transient thermal model has been developed which accurately predicts the temperature of the die and other components of an MQUAD package in situations in which the power to the die changes. Examples of such situations are the power-up and power-down cycles and power excursions. The model is used to predict the behavior of a 160 lead, cavity-down MQUAD package in these situations under conditions of low and high circuit board conductivity and natural and forced convection. The predictions of the model are shown to be in good agreement with experimental values for representative situations.<>
{"title":"Transient thermal model for the MQUAD microelectronic package","authors":"B. Guenin","doi":"10.1109/STHERM.1994.288989","DOIUrl":"https://doi.org/10.1109/STHERM.1994.288989","url":null,"abstract":"The MQUAD microelectronic package was developed to provide a high level of thermal performance for high leadcount integrated circuits./sup 1/ A numerical, lumped-parameter transient thermal model has been developed which accurately predicts the temperature of the die and other components of an MQUAD package in situations in which the power to the die changes. Examples of such situations are the power-up and power-down cycles and power excursions. The model is used to predict the behavior of a 160 lead, cavity-down MQUAD package in these situations under conditions of low and high circuit board conductivity and natural and forced convection. The predictions of the model are shown to be in good agreement with experimental values for representative situations.<<ETX>>","PeriodicalId":107140,"journal":{"name":"Proceedings of 1994 IEEE/CHMT 10th Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131496970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-01DOI: 10.1109/STHERM.1994.288996
D. Edwards, Ming Hwang, B. Stearns
Plastic package thermal enhancement techniques that improve the heat dissipating capabilities of the packages are available to IC package design engineers. Evaluations of these techniques have been performed using test structure measurements and thermal FEA modeling. The techniques studied include the use of additional metal traces on the PCB to spread the heat away from the package, the use of heat slugs and heat spreaders inside the package to enhance heat transfer to the package leads and package body, and the use of high thermal conductivity mold compounds to improve thermal performance. Package types ranged from 8 pin SOIC's to 208 PQFP's with a broad range of chip sizes. Details of the measurement and modeling techniques are given with comparison of the models to the experimental results in many instances.<>
{"title":"Thermal enhancement of IC packages","authors":"D. Edwards, Ming Hwang, B. Stearns","doi":"10.1109/STHERM.1994.288996","DOIUrl":"https://doi.org/10.1109/STHERM.1994.288996","url":null,"abstract":"Plastic package thermal enhancement techniques that improve the heat dissipating capabilities of the packages are available to IC package design engineers. Evaluations of these techniques have been performed using test structure measurements and thermal FEA modeling. The techniques studied include the use of additional metal traces on the PCB to spread the heat away from the package, the use of heat slugs and heat spreaders inside the package to enhance heat transfer to the package leads and package body, and the use of high thermal conductivity mold compounds to improve thermal performance. Package types ranged from 8 pin SOIC's to 208 PQFP's with a broad range of chip sizes. Details of the measurement and modeling techniques are given with comparison of the models to the experimental results in many instances.<<ETX>>","PeriodicalId":107140,"journal":{"name":"Proceedings of 1994 IEEE/CHMT 10th Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120879968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-01DOI: 10.1109/STHERM.1994.288999
M. Vogel
Experimental procedures were used to compare thermal performance characteristics for similar shaped air-cooled heat sinks manufactured from metallic and non-metallic materials. The heat sink geometry was designed and optimized with the intent of cooling a single die which is dissipating 100 watts in a desktop, workstation environment. One of the heat sinks was fabricated by bonding a copper base to a machined, graphite fin structure which has a uni-directional thermal conductivity of 800 W/m C. At 183 air velocity of 150 linear feet per minute (lfm) and an estimated pressure loss of less than 0.039 inches of water, the measured sink-to-air thermal resistance was 0.53 C/W for this copper/graphite hybrid design. Measured junction-to-sink thermal resistances were less than 0.20 C/W when a commercially available land grid array package was used to directly attach a copper heat sink to a 0.50"/spl times/0.50"/spl times/0.015" thermal test chip. Measured heat sink thermal resistances were in relatively good agreement with predicted heat sink resistance values for sea level atmospheric conditions. A modeling simplification technique is presented which allows the numerical computational time to be reduced by at least 50 percent for heat sink optimization studies. Numerical computational techniques were used to estimate the effect of reduced air density on heat sink performance for high altitude, low air velocity environmental conditions.<>
{"title":"Thermal performance of air-cooled hybrid heat sinks for a low velocity environment","authors":"M. Vogel","doi":"10.1109/STHERM.1994.288999","DOIUrl":"https://doi.org/10.1109/STHERM.1994.288999","url":null,"abstract":"Experimental procedures were used to compare thermal performance characteristics for similar shaped air-cooled heat sinks manufactured from metallic and non-metallic materials. The heat sink geometry was designed and optimized with the intent of cooling a single die which is dissipating 100 watts in a desktop, workstation environment. One of the heat sinks was fabricated by bonding a copper base to a machined, graphite fin structure which has a uni-directional thermal conductivity of 800 W/m C. At 183 air velocity of 150 linear feet per minute (lfm) and an estimated pressure loss of less than 0.039 inches of water, the measured sink-to-air thermal resistance was 0.53 C/W for this copper/graphite hybrid design. Measured junction-to-sink thermal resistances were less than 0.20 C/W when a commercially available land grid array package was used to directly attach a copper heat sink to a 0.50\"/spl times/0.50\"/spl times/0.015\" thermal test chip. Measured heat sink thermal resistances were in relatively good agreement with predicted heat sink resistance values for sea level atmospheric conditions. A modeling simplification technique is presented which allows the numerical computational time to be reduced by at least 50 percent for heat sink optimization studies. Numerical computational techniques were used to estimate the effect of reduced air density on heat sink performance for high altitude, low air velocity environmental conditions.<<ETX>>","PeriodicalId":107140,"journal":{"name":"Proceedings of 1994 IEEE/CHMT 10th Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116168071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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