The four V's in Big data sets, Volume, Velocity, Variety, and Veracity, provides challenges in many different aspects of real-time systems. Out of these areas securing big data sets, reduction in processing time and communication bandwidth are of utmost importance. In this paper we adopt Compressive Sensing (CS) based framework to address all three issues. We implement compressive Sensing using Deterministic Random Matrix (DRM) on Artix-7 FPGA, and CS reconstruction using Orthogonal Matching Pursuit (OMP) algorithm on Virtex-7 FPGA. The results show that our implementations for CS sampling and reconstruction are 183x and 2.7x respectively faster when compared to previously published work. We also perform case study of two different applications i.e. multi-channel Seizure Detection and Image processing to demonstrate the efficiency of our proposed CS-based framework. CS-based framework allows us to reduce communication transfers up to 75% while achieving satisfactory range of quality. The results show that our proposed framework is 290x faster and has 7.9x less resource utilization as compared to previously published AES based encryption.
大数据集的四个V:体积(Volume)、速度(Velocity)、多样性(Variety)和准确性(Veracity)，给实时系统的许多不同方面带来了挑战。在这些保护大数据集的领域中，减少处理时间和通信带宽是至关重要的。在本文中，我们采用基于压缩感知(CS)的框架来解决这三个问题。我们在Artix-7 FPGA上使用确定性随机矩阵(Deterministic Random Matrix, DRM)实现压缩感知，在Virtex-7 FPGA上使用正交匹配追踪(Orthogonal Matching Pursuit, OMP)算法实现CS重构。结果表明，我们对CS采样和重建的实现分别比以前发表的工作快了183倍和2.7倍。我们还对两种不同的应用进行了案例研究，即多通道癫痫检测和图像处理，以证明我们提出的基于cs的框架的效率。基于cs的框架使我们能够在达到令人满意的质量范围的同时减少高达75%的通信传输。结果表明，与之前发布的基于AES的加密相比，我们提出的框架速度快290倍，资源利用率低7.9倍。
{"title":"CS-Based Secured Big Data Processing on FPGA","authors":"A. Kulkarni, A. Jafari, Colin Shea, T. Mohsenin","doi":"10.1109/FCCM.2016.59","DOIUrl":"https://doi.org/10.1109/FCCM.2016.59","url":null,"abstract":"The four V's in Big data sets, Volume, Velocity, Variety, and Veracity, provides challenges in many different aspects of real-time systems. Out of these areas securing big data sets, reduction in processing time and communication bandwidth are of utmost importance. In this paper we adopt Compressive Sensing (CS) based framework to address all three issues. We implement compressive Sensing using Deterministic Random Matrix (DRM) on Artix-7 FPGA, and CS reconstruction using Orthogonal Matching Pursuit (OMP) algorithm on Virtex-7 FPGA. The results show that our implementations for CS sampling and reconstruction are 183x and 2.7x respectively faster when compared to previously published work. We also perform case study of two different applications i.e. multi-channel Seizure Detection and Image processing to demonstrate the efficiency of our proposed CS-based framework. CS-based framework allows us to reduce communication transfers up to 75% while achieving satisfactory range of quality. The results show that our proposed framework is 290x faster and has 7.9x less resource utilization as compared to previously published AES based encryption.","PeriodicalId":113498,"journal":{"name":"2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131716506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work provides an empirical analysis on the fidelity of the VPR area models. Both the original minimum width transistor area model and the new COFFE model are compared against actual layouts with up to 3 metal layers of the various FPGA building blocks. We found that both models have significant variations with respect to the actual layout area. Most importantly both models offer relatively low fidelity in layout area estimation with the widely used original VPR model overestimates layout area of larger buffers and full adders by as much as 22%-34% while underestimates the layout area of smaller buffers and multiplexers by as much as -43%. The newer COFFE model also significantly overestimates the layout area of a full adder by 13% and underestimates the layout area of multiplexers by -55% to -30%. Such a variation is particularly significant considering many previous architectural studies based on these models have differentiated architectures based on the area or area delay product variations as low as a few percentage points. Our results suggest that the actual layout area must be used to achieve a highly accurate FPGA area model.
{"title":"An Empirical Analysis of the Fidelity of VPR Area Models","authors":"Farheen Fatima Khan, A. Ye","doi":"10.1109/FCCM.2016.43","DOIUrl":"https://doi.org/10.1109/FCCM.2016.43","url":null,"abstract":"This work provides an empirical analysis on the fidelity of the VPR area models. Both the original minimum width transistor area model and the new COFFE model are compared against actual layouts with up to 3 metal layers of the various FPGA building blocks. We found that both models have significant variations with respect to the actual layout area. Most importantly both models offer relatively low fidelity in layout area estimation with the widely used original VPR model overestimates layout area of larger buffers and full adders by as much as 22%-34% while underestimates the layout area of smaller buffers and multiplexers by as much as -43%. The newer COFFE model also significantly overestimates the layout area of a full adder by 13% and underestimates the layout area of multiplexers by -55% to -30%. Such a variation is particularly significant considering many previous architectural studies based on these models have differentiated architectures based on the area or area delay product variations as low as a few percentage points. Our results suggest that the actual layout area must be used to achieve a highly accurate FPGA area model.","PeriodicalId":113498,"journal":{"name":"2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117095461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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