Biologists require ways to rapidly sequence vast amounts of DNA information. An approach to satisfying the demand is to provide hardware support and leverage parallel computation. When providing hardware acceleration it is known that a custom specific circuit would provide a high performance solution. Providing a balance between delivering an application-specific circuit while achieving optimal utilization of a field programmable gate array is a difficult task. This paper presents a technique in which a custom circuit solution for a given parameter set is generated for the edit-distance problem in comparing two sequences for similarity
{"title":"Parameter-Specific FPGA Implementation of Edit-Distance Calculation","authors":"K. Kent, Ryan B. Proudfoot, Yong Zhao","doi":"10.1109/RSP.2006.26","DOIUrl":"https://doi.org/10.1109/RSP.2006.26","url":null,"abstract":"Biologists require ways to rapidly sequence vast amounts of DNA information. An approach to satisfying the demand is to provide hardware support and leverage parallel computation. When providing hardware acceleration it is known that a custom specific circuit would provide a high performance solution. Providing a balance between delivering an application-specific circuit while achieving optimal utilization of a field programmable gate array is a difficult task. This paper presents a technique in which a custom circuit solution for a given parameter set is generated for the edit-distance problem in comparing two sequences for similarity","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130922753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work studies the relations between pipeline architectures and their specification expressed in CTL. We propose a method to build pipeline structures incrementally from a simple one (already verified) to a more complex one. Moreover, we show how each increment can be integrated in a CTL specification. We define increments to model treatment delay and treatment abortion of a pipeline flow, and we formalize the composition of the different increments. In order to represent the increments added to an architecture, we derive a set of CTL formulae transformations. Finally we model a control flow of a protocol converter by composition of these increments. We show how CTL properties of the complex architecture are built by applying automatic transformations on the set of CTL properties of the simplest architecture
{"title":"Formalizing the Incremental Design and Verification Process of a Pipelined Protocol Converter","authors":"Cécile Braunstein, Emmanuelle Encrenaz-Tiphène","doi":"10.1109/RSP.2006.19","DOIUrl":"https://doi.org/10.1109/RSP.2006.19","url":null,"abstract":"This work studies the relations between pipeline architectures and their specification expressed in CTL. We propose a method to build pipeline structures incrementally from a simple one (already verified) to a more complex one. Moreover, we show how each increment can be integrated in a CTL specification. We define increments to model treatment delay and treatment abortion of a pipeline flow, and we formalize the composition of the different increments. In order to represent the increments added to an architecture, we derive a set of CTL formulae transformations. Finally we model a control flow of a protocol converter by composition of these increments. We show how CTL properties of the complex architecture are built by applying automatic transformations on the set of CTL properties of the simplest architecture","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122895553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Dwivedi, A. Kejariwal, M. Balakrishnan, Anshul Kumar
In a hardware-software co-design environment, an application is partitioned into modules. Each module is then mapped either to software or to hardware. The mapping process is driven by the hardware/software cost and performance parameters of each module. This makes hardware estimation important to evaluate the various candidate architectures. Lack of an efficient hardware estimation methodology and a supporting tool results in inefficient partitioning. In this paper, we present novel algorithms for clock period estimation and estimation of upper bound on execution time under given resource constraints which includes constraints on number of ports in the register file and memory. Experimental results on benchmarks from the high-level synthesis (HLS), MiBench and Media-bench suites, show the effectiveness of our algorithms
{"title":"Rapid Resource-Constrained Hardware Performance Estimation","authors":"B. Dwivedi, A. Kejariwal, M. Balakrishnan, Anshul Kumar","doi":"10.1109/RSP.2006.33","DOIUrl":"https://doi.org/10.1109/RSP.2006.33","url":null,"abstract":"In a hardware-software co-design environment, an application is partitioned into modules. Each module is then mapped either to software or to hardware. The mapping process is driven by the hardware/software cost and performance parameters of each module. This makes hardware estimation important to evaluate the various candidate architectures. Lack of an efficient hardware estimation methodology and a supporting tool results in inefficient partitioning. In this paper, we present novel algorithms for clock period estimation and estimation of upper bound on execution time under given resource constraints which includes constraints on number of ports in the register file and memory. Experimental results on benchmarks from the high-level synthesis (HLS), MiBench and Media-bench suites, show the effectiveness of our algorithms","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124474623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the design and implementation of a feature tracker on an embedded reconfigurable hardware system. Contrary to other works, the focus here is on the efficient hardware/software partitioning of the feature tracker algorithm, a viable data flow management as well as an efficient use of memory and processor features. The implementation is done on a Xilinx evaluation board and the results provided show the superiority of our implementation compared to the other works
{"title":"Design and Implementation of an Object Tracker on a Reconfigurable System on Chip","authors":"F. Mühlbauer, C. Bobda","doi":"10.1109/RSP.2006.13","DOIUrl":"https://doi.org/10.1109/RSP.2006.13","url":null,"abstract":"This paper presents the design and implementation of a feature tracker on an embedded reconfigurable hardware system. Contrary to other works, the focus here is on the efficient hardware/software partitioning of the feature tracker algorithm, a viable data flow management as well as an efficient use of memory and processor features. The implementation is done on a Xilinx evaluation board and the results provided show the superiority of our implementation compared to the other works","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127283638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An agile modeling methodology for building BSP called cross platform BSP framework (CPBF) is introduced in this paper. We propose an operating system independent unified cross platform BSP architecture; setup a BSP framework which mainstream embedded operating systems like Linux, WinCE, PalmOS and Symbian can build on. CPBF consists of two parts, they target at boot loader initialization and device drivers respectively. The design methodology and guidelines are discussed in detail, and then illustrated by practical audio codec design on Intel XScale development board for example. This framework can accelerate the BSP development and simplify the maintenance work of a specified processor or SOC platform remarkably
{"title":"An Agile BSP Modeling Methodology: Cross Platform BSP Framework (CPBF)","authors":"Tianzhou Chen, Yin Yan, Hongjun Dai, Hu Wei","doi":"10.1109/RSP.2006.6","DOIUrl":"https://doi.org/10.1109/RSP.2006.6","url":null,"abstract":"An agile modeling methodology for building BSP called cross platform BSP framework (CPBF) is introduced in this paper. We propose an operating system independent unified cross platform BSP architecture; setup a BSP framework which mainstream embedded operating systems like Linux, WinCE, PalmOS and Symbian can build on. CPBF consists of two parts, they target at boot loader initialization and device drivers respectively. The design methodology and guidelines are discussed in detail, and then illustrated by practical audio codec design on Intel XScale development board for example. This framework can accelerate the BSP development and simplify the maintenance work of a specified processor or SOC platform remarkably","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124716940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Model based development based on different domain specific tools and graphical notations gains increasing importance in system design of embedded electronic systems allowing fast concept-oriented prototyping from model to code. This paper describes an extension to our seamless model based development approach: An architecture for debugging models that are executed on target systems or in dedicated rapid-prototyping environments. We discuss the advantages of such an approach as opposed to simulation and describe our universal architecture. We focus on the definition of MOF-based runtime models and their synchronisation with the runtime target state. An example of debugging state-charts shows the feasibility of the approach
{"title":"Dynamic Mapping of Runtime Information Models for Debugging Embedded Software","authors":"P. Graf, K. Müller-Glaser","doi":"10.1109/RSP.2006.15","DOIUrl":"https://doi.org/10.1109/RSP.2006.15","url":null,"abstract":"Model based development based on different domain specific tools and graphical notations gains increasing importance in system design of embedded electronic systems allowing fast concept-oriented prototyping from model to code. This paper describes an extension to our seamless model based development approach: An architecture for debugging models that are executed on target systems or in dedicated rapid-prototyping environments. We discuss the advantages of such an approach as opposed to simulation and describe our universal architecture. We focus on the definition of MOF-based runtime models and their synchronisation with the runtime target state. An example of debugging state-charts shows the feasibility of the approach","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129132020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Marcio Ferreira da Silva Oliveira, L. Brisolara, L. Carro, F. Wagner
In order to quickly implement an embedded system that is mainly based on software, two orthogonal approaches have been proposed: platform-based Design, which maximizes the reuse of components; and model driven development, which rises the abstraction level by using object-oriented concepts and UML. However, with this increasing of the abstraction level, software engineers do not have an exact idea of the impact of their modeling decisions on important issues such as performance, energy, and memory footprint for a given platform. In our approach, analytical estimation of data and program memory, performance, and energy are obtained directly from UML models. Experimental results show a very small estimation error when software components are reused and their costs on the target platform are already known. Real-life applications are modeled in different ways and demonstrate the effectiveness of the estimates in an early design space exploration, allowing the designer to quickly compare different modeling solutions, with estimation errors as low as 5%
{"title":"Early Embedded Software Design Space Exploration Using UML-Based Estimation","authors":"Marcio Ferreira da Silva Oliveira, L. Brisolara, L. Carro, F. Wagner","doi":"10.1109/RSP.2006.16","DOIUrl":"https://doi.org/10.1109/RSP.2006.16","url":null,"abstract":"In order to quickly implement an embedded system that is mainly based on software, two orthogonal approaches have been proposed: platform-based Design, which maximizes the reuse of components; and model driven development, which rises the abstraction level by using object-oriented concepts and UML. However, with this increasing of the abstraction level, software engineers do not have an exact idea of the impact of their modeling decisions on important issues such as performance, energy, and memory footprint for a given platform. In our approach, analytical estimation of data and program memory, performance, and energy are obtained directly from UML models. Experimental results show a very small estimation error when software components are reused and their costs on the target platform are already known. Real-life applications are modeled in different ways and demonstrate the effectiveness of the estimates in an early design space exploration, allowing the designer to quickly compare different modeling solutions, with estimation errors as low as 5%","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133661256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Girodias, Y. Bouchebaba, G. Nicolescu, E. Aboulhamid, P. Paulin, Bruno Lavigueur
Multiprocessor system-on-chip is one of the main drivers of the semiconductor industry revolution by enabling the integration of complex functionality on a single chip. Memory is becoming a key player for significant improvements in embedded systems (power, performance and area). With the emergence of more embedded multimedia applications in the industry, this issue becomes increasingly vital. These applications often use multi-dimensional arrays to store intermediate results during multimedia processing tasks. A couple of key optimization techniques exist and have been demonstrated on SoC architecture. This paper presents these techniques and their impact on a MPSoC environment and brings forward improvements. These techniques allow for optimization of memory space, reduction of the number of cache misses and extensive improvement of processing time extensively. In this paper's case study, theses techniques yield an average increase of the data cache hit rate by 20% and an average decrease of processing time by 50%
{"title":"Application-Level Memory Optimization for MPSoC","authors":"B. Girodias, Y. Bouchebaba, G. Nicolescu, E. Aboulhamid, P. Paulin, Bruno Lavigueur","doi":"10.1109/RSP.2006.8","DOIUrl":"https://doi.org/10.1109/RSP.2006.8","url":null,"abstract":"Multiprocessor system-on-chip is one of the main drivers of the semiconductor industry revolution by enabling the integration of complex functionality on a single chip. Memory is becoming a key player for significant improvements in embedded systems (power, performance and area). With the emergence of more embedded multimedia applications in the industry, this issue becomes increasingly vital. These applications often use multi-dimensional arrays to store intermediate results during multimedia processing tasks. A couple of key optimization techniques exist and have been demonstrated on SoC architecture. This paper presents these techniques and their impact on a MPSoC environment and brings forward improvements. These techniques allow for optimization of memory space, reduction of the number of cache misses and extensive improvement of processing time extensively. In this paper's case study, theses techniques yield an average increase of the data cache hit rate by 20% and an average decrease of processing time by 50%","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127287673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Senouci, A. Bouchhima, F. Rousseau, F. Pétrot, A. Jerraya
This paper describes our experience in using the POSIX API standard for MPSoC applications prototyping on a reconfigurable multiprocessor ARM architecture. Applications running on this platform use a symmetric multiprocessor (SMP) POSIX compliant kernel named MUTEK. This work allows us to investigate and understand the complexities of the hardware/software interface design process. We propose a new generic MPSoC prototyping flow based on the POSIX standard, which allows fast prototyping of POSIX threads based applications
{"title":"Fast Prototyping of POSIX Based Applications on a Multiprocessor SoC Architecture: \"Hardware-Dependent Software Oriented Approach\"","authors":"B. Senouci, A. Bouchhima, F. Rousseau, F. Pétrot, A. Jerraya","doi":"10.1109/RSP.2006.17","DOIUrl":"https://doi.org/10.1109/RSP.2006.17","url":null,"abstract":"This paper describes our experience in using the POSIX API standard for MPSoC applications prototyping on a reconfigurable multiprocessor ARM architecture. Applications running on this platform use a symmetric multiprocessor (SMP) POSIX compliant kernel named MUTEK. This work allows us to investigate and understand the complexities of the hardware/software interface design process. We propose a new generic MPSoC prototyping flow based on the POSIX standard, which allows fast prototyping of POSIX threads based applications","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"110 S131","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113972822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
RAM-based FPGAs have become very important for electronic designs in the last years since they are very flexible, provide high configurability and allow short turn around times. Especially in the field of rapid prototyping (RP) another feature plays an important rule: their infinite reprogrammability. These features help to create freely modifiable rapid prototyping systems, which allow both, changes in the hardware architecture as well as in software. However, handling the FPGA devices in the engineering process is not an easy issue and typically requires deep knowledge of the circuits themselves, their behavior and programming languages as VHDL or Verilog. Our approach presents the combination of a flexible and versatile FPGA-based rapid prototyping system and efficient configuration methodology for Xilinx Virtex-II FPGAs supplemented by an easy to use design support for time saving functional implementation and platform configuration
{"title":"Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAs","authors":"C. Bieser, K. Müller-Glaser","doi":"10.1109/RSP.2006.32","DOIUrl":"https://doi.org/10.1109/RSP.2006.32","url":null,"abstract":"RAM-based FPGAs have become very important for electronic designs in the last years since they are very flexible, provide high configurability and allow short turn around times. Especially in the field of rapid prototyping (RP) another feature plays an important rule: their infinite reprogrammability. These features help to create freely modifiable rapid prototyping systems, which allow both, changes in the hardware architecture as well as in software. However, handling the FPGA devices in the engineering process is not an easy issue and typically requires deep knowledge of the circuits themselves, their behavior and programming languages as VHDL or Verilog. Our approach presents the combination of a flexible and versatile FPGA-based rapid prototyping system and efficient configuration methodology for Xilinx Virtex-II FPGAs supplemented by an easy to use design support for time saving functional implementation and platform configuration","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117290378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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