Isabelle Hurbain, Corinne Ancourt, F. Irigoin, M. Barreteau, N. Museux, F. Pasquier
Embedded real-time multimedia applications usually imply data parallel processing. SIMD processors embedded in SOCs are cost effective to exploit the underlying parallelism. However, programming applications for SIMD targets requires data placement and operation scheduling which are NP-complete problems. In this paper we show how our tool (based on concurrent constraint programming) can be used to explore the design space of a kernel in H.264 standard (video compression). Different cost functions are considered (e.g. execution time, memory occupancy, chip cost...) to derive different source codes from the same functional specification. Future work includes model refinement as well as full code generation for rapid prototyping of such hardware and software intensive systems
{"title":"A Case Study of Design Space Exploration for Embedded Multimedia Applications on SoCs","authors":"Isabelle Hurbain, Corinne Ancourt, F. Irigoin, M. Barreteau, N. Museux, F. Pasquier","doi":"10.1109/RSP.2006.1","DOIUrl":"https://doi.org/10.1109/RSP.2006.1","url":null,"abstract":"Embedded real-time multimedia applications usually imply data parallel processing. SIMD processors embedded in SOCs are cost effective to exploit the underlying parallelism. However, programming applications for SIMD targets requires data placement and operation scheduling which are NP-complete problems. In this paper we show how our tool (based on concurrent constraint programming) can be used to explore the design space of a kernel in H.264 standard (video compression). Different cost functions are considered (e.g. execution time, memory occupancy, chip cost...) to derive different source codes from the same functional specification. Future work includes model refinement as well as full code generation for rapid prototyping of such hardware and software intensive systems","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132055143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Over the past few years, there has been an increasing interest in using partial and run-time reconfigurable (RTR) FPGAs to develop reconfigurable systems for various applications. To support this new type of hardware, new or improved design methodologies and tools are needed that can provide sufficient support for RTR-related design and verification tasks. This paper first introduces a novel concept called run-time reconfigurable co-emulation, which extends traditional co-emulation with the RTR capability of FPGAs. It then describes and discusses how to develop hardware platforms that use the RTR co-emulation concept for transaction-level functional verification and in-circuit debugging of RTR-based FPGA designs
{"title":"Platform Development for Run-Time Reconfigurable Co-Emulation","authors":"Rawat Siripokarpirom","doi":"10.1109/RSP.2006.28","DOIUrl":"https://doi.org/10.1109/RSP.2006.28","url":null,"abstract":"Over the past few years, there has been an increasing interest in using partial and run-time reconfigurable (RTR) FPGAs to develop reconfigurable systems for various applications. To support this new type of hardware, new or improved design methodologies and tools are needed that can provide sufficient support for RTR-related design and verification tasks. This paper first introduces a novel concept called run-time reconfigurable co-emulation, which extends traditional co-emulation with the RTR capability of FPGAs. It then describes and discusses how to develop hardware platforms that use the RTR co-emulation concept for transaction-level functional verification and in-circuit debugging of RTR-based FPGA designs","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127112606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Kriaa, A. Bouchhima, W. Youssef, F. Pétrot, A. Fouilliart, A. Jerraya
This paper describes a service-based model enabling systematic design and global simulation environments for SoC design. This model, called service dependency graph (SDG) allows modeling of complex, customized (application-specific) interfaces. We also present a model generator that can automatically build hardware/software interfaces based on service and resource requirements described by the SDG. This approach has been applied successfully on the design of a software defined radio application. The results show the effectiveness of the proposed approach in modeling complex interfaces. Additionally the SDG seems to be an excellent intermediate representation for the design automation of hardware software interfaces
{"title":"Service Based Component Design Approach for Flexible Hardware/Software Interface Modeling","authors":"L. Kriaa, A. Bouchhima, W. Youssef, F. Pétrot, A. Fouilliart, A. Jerraya","doi":"10.1109/RSP.2006.35","DOIUrl":"https://doi.org/10.1109/RSP.2006.35","url":null,"abstract":"This paper describes a service-based model enabling systematic design and global simulation environments for SoC design. This model, called service dependency graph (SDG) allows modeling of complex, customized (application-specific) interfaces. We also present a model generator that can automatically build hardware/software interfaces based on service and resource requirements described by the SDG. This approach has been applied successfully on the design of a software defined radio application. The results show the effectiveness of the proposed approach in modeling complex interfaces. Additionally the SDG seems to be an excellent intermediate representation for the design automation of hardware software interfaces","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127841885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Biologists require ways to rapidly sequence vast amounts of DNA information. An approach to satisfying the demand is to provide hardware support and leverage parallel computation. When providing hardware acceleration it is known that a custom specific circuit would provide a high performance solution. Providing a balance between delivering an application-specific circuit while achieving optimal utilization of a field programmable gate array is a difficult task. This paper presents a technique in which a custom circuit solution for a given parameter set is generated for the edit-distance problem in comparing two sequences for similarity
{"title":"Parameter-Specific FPGA Implementation of Edit-Distance Calculation","authors":"K. Kent, Ryan B. Proudfoot, Yong Zhao","doi":"10.1109/RSP.2006.26","DOIUrl":"https://doi.org/10.1109/RSP.2006.26","url":null,"abstract":"Biologists require ways to rapidly sequence vast amounts of DNA information. An approach to satisfying the demand is to provide hardware support and leverage parallel computation. When providing hardware acceleration it is known that a custom specific circuit would provide a high performance solution. Providing a balance between delivering an application-specific circuit while achieving optimal utilization of a field programmable gate array is a difficult task. This paper presents a technique in which a custom circuit solution for a given parameter set is generated for the edit-distance problem in comparing two sequences for similarity","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130922753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work studies the relations between pipeline architectures and their specification expressed in CTL. We propose a method to build pipeline structures incrementally from a simple one (already verified) to a more complex one. Moreover, we show how each increment can be integrated in a CTL specification. We define increments to model treatment delay and treatment abortion of a pipeline flow, and we formalize the composition of the different increments. In order to represent the increments added to an architecture, we derive a set of CTL formulae transformations. Finally we model a control flow of a protocol converter by composition of these increments. We show how CTL properties of the complex architecture are built by applying automatic transformations on the set of CTL properties of the simplest architecture
{"title":"Formalizing the Incremental Design and Verification Process of a Pipelined Protocol Converter","authors":"Cécile Braunstein, Emmanuelle Encrenaz-Tiphène","doi":"10.1109/RSP.2006.19","DOIUrl":"https://doi.org/10.1109/RSP.2006.19","url":null,"abstract":"This work studies the relations between pipeline architectures and their specification expressed in CTL. We propose a method to build pipeline structures incrementally from a simple one (already verified) to a more complex one. Moreover, we show how each increment can be integrated in a CTL specification. We define increments to model treatment delay and treatment abortion of a pipeline flow, and we formalize the composition of the different increments. In order to represent the increments added to an architecture, we derive a set of CTL formulae transformations. Finally we model a control flow of a protocol converter by composition of these increments. We show how CTL properties of the complex architecture are built by applying automatic transformations on the set of CTL properties of the simplest architecture","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122895553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Dwivedi, A. Kejariwal, M. Balakrishnan, Anshul Kumar
In a hardware-software co-design environment, an application is partitioned into modules. Each module is then mapped either to software or to hardware. The mapping process is driven by the hardware/software cost and performance parameters of each module. This makes hardware estimation important to evaluate the various candidate architectures. Lack of an efficient hardware estimation methodology and a supporting tool results in inefficient partitioning. In this paper, we present novel algorithms for clock period estimation and estimation of upper bound on execution time under given resource constraints which includes constraints on number of ports in the register file and memory. Experimental results on benchmarks from the high-level synthesis (HLS), MiBench and Media-bench suites, show the effectiveness of our algorithms
{"title":"Rapid Resource-Constrained Hardware Performance Estimation","authors":"B. Dwivedi, A. Kejariwal, M. Balakrishnan, Anshul Kumar","doi":"10.1109/RSP.2006.33","DOIUrl":"https://doi.org/10.1109/RSP.2006.33","url":null,"abstract":"In a hardware-software co-design environment, an application is partitioned into modules. Each module is then mapped either to software or to hardware. The mapping process is driven by the hardware/software cost and performance parameters of each module. This makes hardware estimation important to evaluate the various candidate architectures. Lack of an efficient hardware estimation methodology and a supporting tool results in inefficient partitioning. In this paper, we present novel algorithms for clock period estimation and estimation of upper bound on execution time under given resource constraints which includes constraints on number of ports in the register file and memory. Experimental results on benchmarks from the high-level synthesis (HLS), MiBench and Media-bench suites, show the effectiveness of our algorithms","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124474623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the design and implementation of a feature tracker on an embedded reconfigurable hardware system. Contrary to other works, the focus here is on the efficient hardware/software partitioning of the feature tracker algorithm, a viable data flow management as well as an efficient use of memory and processor features. The implementation is done on a Xilinx evaluation board and the results provided show the superiority of our implementation compared to the other works
{"title":"Design and Implementation of an Object Tracker on a Reconfigurable System on Chip","authors":"F. Mühlbauer, C. Bobda","doi":"10.1109/RSP.2006.13","DOIUrl":"https://doi.org/10.1109/RSP.2006.13","url":null,"abstract":"This paper presents the design and implementation of a feature tracker on an embedded reconfigurable hardware system. Contrary to other works, the focus here is on the efficient hardware/software partitioning of the feature tracker algorithm, a viable data flow management as well as an efficient use of memory and processor features. The implementation is done on a Xilinx evaluation board and the results provided show the superiority of our implementation compared to the other works","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127283638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Luiza Gheorghe Iugan, F. Bouchhima, G. Nicolescu, H. Boucheneb
Continuous and discrete components may be integrated in diverse embedded systems ranging across defense, medical, communication, and automotive applications. The global validation of these systems requires new validation techniques, the main challenge being the definition of global simulation models able to accommodate the different concepts specific to continuous and discrete models. This paper presents the operational semantic for the continuous/discrete synchronization model and the formal definition of the internal architecture of simulation interfaces required for the design of a co-simulation tool for continuous/discrete systems validation
{"title":"Formal Definitions of Simulation Interfaces in a Continuous/Discrete Co-Simulation Tool","authors":"Luiza Gheorghe Iugan, F. Bouchhima, G. Nicolescu, H. Boucheneb","doi":"10.1109/RSP.2006.18","DOIUrl":"https://doi.org/10.1109/RSP.2006.18","url":null,"abstract":"Continuous and discrete components may be integrated in diverse embedded systems ranging across defense, medical, communication, and automotive applications. The global validation of these systems requires new validation techniques, the main challenge being the definition of global simulation models able to accommodate the different concepts specific to continuous and discrete models. This paper presents the operational semantic for the continuous/discrete synchronization model and the formal definition of the internal architecture of simulation interfaces required for the design of a co-simulation tool for continuous/discrete systems validation","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125134683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a system-on-chip software hardware co-design methodology for a statistical coder. We use the context adaptive binary arithmetic coder (CABAC) used in the main profile of the H.264/AVC video coding standard as a design example. The design methodology first involves performance and complexity analyses of the existing CABAC reference software, and thus the top-level CABAC software hardware architecture can be conceptualized. The design is aimed to strike a balance between software modules and hardware modules based on design constraints. Verification is performed by comparing the compressed bit stream generated by the reference CABAC SW (without any HW assisted circuitries), with that output by the top-level CABAC architecture (with HW assisted circuitries). Standard video test sequences have been used for verification purpose. The CABAC architecture is then put within the system-on-chip frame work where system bus and its signals, input/output FIFO buffers, debug structures, reset circuit, etc. are designed into. Compared to existing statistical coders, this design is aimed for significant coding time saving by balancing timing between software modules and hardware modules, is well verified with standard video test sequences, and is reusable as an IP in a SoC environment
{"title":"System-on-Chip Design Methodology for a Statistical Coder","authors":"T. M. Le, X. Tian, B. Ho, J. Nankoo, Y. Lian","doi":"10.1109/RSP.2006.40","DOIUrl":"https://doi.org/10.1109/RSP.2006.40","url":null,"abstract":"In this paper, we propose a system-on-chip software hardware co-design methodology for a statistical coder. We use the context adaptive binary arithmetic coder (CABAC) used in the main profile of the H.264/AVC video coding standard as a design example. The design methodology first involves performance and complexity analyses of the existing CABAC reference software, and thus the top-level CABAC software hardware architecture can be conceptualized. The design is aimed to strike a balance between software modules and hardware modules based on design constraints. Verification is performed by comparing the compressed bit stream generated by the reference CABAC SW (without any HW assisted circuitries), with that output by the top-level CABAC architecture (with HW assisted circuitries). Standard video test sequences have been used for verification purpose. The CABAC architecture is then put within the system-on-chip frame work where system bus and its signals, input/output FIFO buffers, debug structures, reset circuit, etc. are designed into. Compared to existing statistical coders, this design is aimed for significant coding time saving by balancing timing between software modules and hardware modules, is well verified with standard video test sequences, and is reusable as an IP in a SoC environment","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127654865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Model based development based on different domain specific tools and graphical notations gains increasing importance in system design of embedded electronic systems allowing fast concept-oriented prototyping from model to code. This paper describes an extension to our seamless model based development approach: An architecture for debugging models that are executed on target systems or in dedicated rapid-prototyping environments. We discuss the advantages of such an approach as opposed to simulation and describe our universal architecture. We focus on the definition of MOF-based runtime models and their synchronisation with the runtime target state. An example of debugging state-charts shows the feasibility of the approach
{"title":"Dynamic Mapping of Runtime Information Models for Debugging Embedded Software","authors":"P. Graf, K. Müller-Glaser","doi":"10.1109/RSP.2006.15","DOIUrl":"https://doi.org/10.1109/RSP.2006.15","url":null,"abstract":"Model based development based on different domain specific tools and graphical notations gains increasing importance in system design of embedded electronic systems allowing fast concept-oriented prototyping from model to code. This paper describes an extension to our seamless model based development approach: An architecture for debugging models that are executed on target systems or in dedicated rapid-prototyping environments. We discuss the advantages of such an approach as opposed to simulation and describe our universal architecture. We focus on the definition of MOF-based runtime models and their synchronisation with the runtime target state. An example of debugging state-charts shows the feasibility of the approach","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129132020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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