B. Girodias, Y. Bouchebaba, G. Nicolescu, E. Aboulhamid, P. Paulin, Bruno Lavigueur
Multiprocessor system-on-chip is one of the main drivers of the semiconductor industry revolution by enabling the integration of complex functionality on a single chip. Memory is becoming a key player for significant improvements in embedded systems (power, performance and area). With the emergence of more embedded multimedia applications in the industry, this issue becomes increasingly vital. These applications often use multi-dimensional arrays to store intermediate results during multimedia processing tasks. A couple of key optimization techniques exist and have been demonstrated on SoC architecture. This paper presents these techniques and their impact on a MPSoC environment and brings forward improvements. These techniques allow for optimization of memory space, reduction of the number of cache misses and extensive improvement of processing time extensively. In this paper's case study, theses techniques yield an average increase of the data cache hit rate by 20% and an average decrease of processing time by 50%
{"title":"Application-Level Memory Optimization for MPSoC","authors":"B. Girodias, Y. Bouchebaba, G. Nicolescu, E. Aboulhamid, P. Paulin, Bruno Lavigueur","doi":"10.1109/RSP.2006.8","DOIUrl":"https://doi.org/10.1109/RSP.2006.8","url":null,"abstract":"Multiprocessor system-on-chip is one of the main drivers of the semiconductor industry revolution by enabling the integration of complex functionality on a single chip. Memory is becoming a key player for significant improvements in embedded systems (power, performance and area). With the emergence of more embedded multimedia applications in the industry, this issue becomes increasingly vital. These applications often use multi-dimensional arrays to store intermediate results during multimedia processing tasks. A couple of key optimization techniques exist and have been demonstrated on SoC architecture. This paper presents these techniques and their impact on a MPSoC environment and brings forward improvements. These techniques allow for optimization of memory space, reduction of the number of cache misses and extensive improvement of processing time extensively. In this paper's case study, theses techniques yield an average increase of the data cache hit rate by 20% and an average decrease of processing time by 50%","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127287673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An agile modeling methodology for building BSP called cross platform BSP framework (CPBF) is introduced in this paper. We propose an operating system independent unified cross platform BSP architecture; setup a BSP framework which mainstream embedded operating systems like Linux, WinCE, PalmOS and Symbian can build on. CPBF consists of two parts, they target at boot loader initialization and device drivers respectively. The design methodology and guidelines are discussed in detail, and then illustrated by practical audio codec design on Intel XScale development board for example. This framework can accelerate the BSP development and simplify the maintenance work of a specified processor or SOC platform remarkably
{"title":"An Agile BSP Modeling Methodology: Cross Platform BSP Framework (CPBF)","authors":"Tianzhou Chen, Yin Yan, Hongjun Dai, Hu Wei","doi":"10.1109/RSP.2006.6","DOIUrl":"https://doi.org/10.1109/RSP.2006.6","url":null,"abstract":"An agile modeling methodology for building BSP called cross platform BSP framework (CPBF) is introduced in this paper. We propose an operating system independent unified cross platform BSP architecture; setup a BSP framework which mainstream embedded operating systems like Linux, WinCE, PalmOS and Symbian can build on. CPBF consists of two parts, they target at boot loader initialization and device drivers respectively. The design methodology and guidelines are discussed in detail, and then illustrated by practical audio codec design on Intel XScale development board for example. This framework can accelerate the BSP development and simplify the maintenance work of a specified processor or SOC platform remarkably","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124716940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Marcio Ferreira da Silva Oliveira, L. Brisolara, L. Carro, F. Wagner
In order to quickly implement an embedded system that is mainly based on software, two orthogonal approaches have been proposed: platform-based Design, which maximizes the reuse of components; and model driven development, which rises the abstraction level by using object-oriented concepts and UML. However, with this increasing of the abstraction level, software engineers do not have an exact idea of the impact of their modeling decisions on important issues such as performance, energy, and memory footprint for a given platform. In our approach, analytical estimation of data and program memory, performance, and energy are obtained directly from UML models. Experimental results show a very small estimation error when software components are reused and their costs on the target platform are already known. Real-life applications are modeled in different ways and demonstrate the effectiveness of the estimates in an early design space exploration, allowing the designer to quickly compare different modeling solutions, with estimation errors as low as 5%
{"title":"Early Embedded Software Design Space Exploration Using UML-Based Estimation","authors":"Marcio Ferreira da Silva Oliveira, L. Brisolara, L. Carro, F. Wagner","doi":"10.1109/RSP.2006.16","DOIUrl":"https://doi.org/10.1109/RSP.2006.16","url":null,"abstract":"In order to quickly implement an embedded system that is mainly based on software, two orthogonal approaches have been proposed: platform-based Design, which maximizes the reuse of components; and model driven development, which rises the abstraction level by using object-oriented concepts and UML. However, with this increasing of the abstraction level, software engineers do not have an exact idea of the impact of their modeling decisions on important issues such as performance, energy, and memory footprint for a given platform. In our approach, analytical estimation of data and program memory, performance, and energy are obtained directly from UML models. Experimental results show a very small estimation error when software components are reused and their costs on the target platform are already known. Real-life applications are modeled in different ways and demonstrate the effectiveness of the estimates in an early design space exploration, allowing the designer to quickly compare different modeling solutions, with estimation errors as low as 5%","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133661256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Senouci, A. Bouchhima, F. Rousseau, F. Pétrot, A. Jerraya
This paper describes our experience in using the POSIX API standard for MPSoC applications prototyping on a reconfigurable multiprocessor ARM architecture. Applications running on this platform use a symmetric multiprocessor (SMP) POSIX compliant kernel named MUTEK. This work allows us to investigate and understand the complexities of the hardware/software interface design process. We propose a new generic MPSoC prototyping flow based on the POSIX standard, which allows fast prototyping of POSIX threads based applications
{"title":"Fast Prototyping of POSIX Based Applications on a Multiprocessor SoC Architecture: \"Hardware-Dependent Software Oriented Approach\"","authors":"B. Senouci, A. Bouchhima, F. Rousseau, F. Pétrot, A. Jerraya","doi":"10.1109/RSP.2006.17","DOIUrl":"https://doi.org/10.1109/RSP.2006.17","url":null,"abstract":"This paper describes our experience in using the POSIX API standard for MPSoC applications prototyping on a reconfigurable multiprocessor ARM architecture. Applications running on this platform use a symmetric multiprocessor (SMP) POSIX compliant kernel named MUTEK. This work allows us to investigate and understand the complexities of the hardware/software interface design process. We propose a new generic MPSoC prototyping flow based on the POSIX standard, which allows fast prototyping of POSIX threads based applications","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"110 S131","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113972822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
RAM-based FPGAs have become very important for electronic designs in the last years since they are very flexible, provide high configurability and allow short turn around times. Especially in the field of rapid prototyping (RP) another feature plays an important rule: their infinite reprogrammability. These features help to create freely modifiable rapid prototyping systems, which allow both, changes in the hardware architecture as well as in software. However, handling the FPGA devices in the engineering process is not an easy issue and typically requires deep knowledge of the circuits themselves, their behavior and programming languages as VHDL or Verilog. Our approach presents the combination of a flexible and versatile FPGA-based rapid prototyping system and efficient configuration methodology for Xilinx Virtex-II FPGAs supplemented by an easy to use design support for time saving functional implementation and platform configuration
{"title":"Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAs","authors":"C. Bieser, K. Müller-Glaser","doi":"10.1109/RSP.2006.32","DOIUrl":"https://doi.org/10.1109/RSP.2006.32","url":null,"abstract":"RAM-based FPGAs have become very important for electronic designs in the last years since they are very flexible, provide high configurability and allow short turn around times. Especially in the field of rapid prototyping (RP) another feature plays an important rule: their infinite reprogrammability. These features help to create freely modifiable rapid prototyping systems, which allow both, changes in the hardware architecture as well as in software. However, handling the FPGA devices in the engineering process is not an easy issue and typically requires deep knowledge of the circuits themselves, their behavior and programming languages as VHDL or Verilog. Our approach presents the combination of a flexible and versatile FPGA-based rapid prototyping system and efficient configuration methodology for Xilinx Virtex-II FPGAs supplemented by an easy to use design support for time saving functional implementation and platform configuration","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117290378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the best-effort IP network, packet delay/loss is inevitably degrade the perceptual quality of real-time multimedia service, such as Voice-over-IP (VoIP), video-on-demand (VoD), etc. Modeling, prototyping, and analysis of traffic traces have always been very important and challenging topics in the area of multimedia communication. In general, packet loss/delay exhibits temporal dependence. Different prototyping tools, such as Bernoulli model, Gilbert model, Extended Gilbert model, Markov model, etc, have been proposed to model network trace. In this research, one VoD server and three clients have been setup to simulate a real VoD system. Different models have been applied to analyze and model the video transmission network traces obtained under RTP/UDP/IP protocol stack. Compared to the other tools, Markov model offers the best prototyping precision, in the sense of loss-run distribution and forward error correction (FEC) performance prediction. As a powerful fast prototyping tool, Markov model is very useful to model and analyze network traces and further improve the QoS in multimedia-over-IP
{"title":"A Prototyping Tool for Analysis and Modeling of Video Transmission Traces over IP Networks","authors":"Ming Yang, N. Bourbakis","doi":"10.1109/RSP.2006.4","DOIUrl":"https://doi.org/10.1109/RSP.2006.4","url":null,"abstract":"In the best-effort IP network, packet delay/loss is inevitably degrade the perceptual quality of real-time multimedia service, such as Voice-over-IP (VoIP), video-on-demand (VoD), etc. Modeling, prototyping, and analysis of traffic traces have always been very important and challenging topics in the area of multimedia communication. In general, packet loss/delay exhibits temporal dependence. Different prototyping tools, such as Bernoulli model, Gilbert model, Extended Gilbert model, Markov model, etc, have been proposed to model network trace. In this research, one VoD server and three clients have been setup to simulate a real VoD system. Different models have been applied to analyze and model the video transmission network traces obtained under RTP/UDP/IP protocol stack. Compared to the other tools, Markov model offers the best prototyping precision, in the sense of loss-run distribution and forward error correction (FEC) performance prediction. As a powerful fast prototyping tool, Markov model is very useful to model and analyze network traces and further improve the QoS in multimedia-over-IP","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127518391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The communication architecture template tree (CAT-tree) is an abstraction of the specific range of communication functions and architectures, which can facilitate system function capture and communication architecture refinement. In this paper, we explain a TLM-RTL-SW mixed-level simulation environment that is useful for the functional verification of partially refined system models. We employed SystemC, GNU Gdb and a HDL simulator for the simulation of CATtree-based TLM, SW and HW, respectively. We also employed a new operating system, DEOS so that each SystemC-based TLMs can be cross-compiled to be executed as software models on the target processors. We evaluated the flexibility and simulation performance of the virtual simulation environment with an H.264 decoder design example
{"title":"A Mixed-Level Virtual Prototyping Environment for Refinement-Based Design Environment","authors":"Sanggyu Park, Sang-yong Yoon, S. Chae","doi":"10.1109/RSP.2006.3","DOIUrl":"https://doi.org/10.1109/RSP.2006.3","url":null,"abstract":"The communication architecture template tree (CAT-tree) is an abstraction of the specific range of communication functions and architectures, which can facilitate system function capture and communication architecture refinement. In this paper, we explain a TLM-RTL-SW mixed-level simulation environment that is useful for the functional verification of partially refined system models. We employed SystemC, GNU Gdb and a HDL simulator for the simulation of CATtree-based TLM, SW and HW, respectively. We also employed a new operating system, DEOS so that each SystemC-based TLMs can be cross-compiled to be executed as software models on the target processors. We evaluated the flexibility and simulation performance of the virtual simulation environment with an H.264 decoder design example","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127389899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In many industries, such as finance and insurance, business processes represent products which need to be rolled out to customers within a strict deadline, e.g. new insurance policies. The products are also supposed to be modifiable during their period of service and should be verified and tested before being placed in service. In these industries, being able to create a new process or to change one quickly is providing one competitive advantage; carrying out business processes efficiently provides another. Rapid business process prototyping, in this case, is a practically motivated approach. This contribution presents a realistic business process modeling, verification, and prototyping framework by means of a formal Petri net-based specification language. By specifying process models using this language, executable process controllers can be automatically generated and smoothly integrated into a service-oriented architecture. Furthermore, formal verification techniques and tools can be used to detect errors during the design phase of the process
{"title":"Generative Business Process Prototyping Framework","authors":"Ang Chen, Didier Buchs","doi":"10.1109/RSP.2006.20","DOIUrl":"https://doi.org/10.1109/RSP.2006.20","url":null,"abstract":"In many industries, such as finance and insurance, business processes represent products which need to be rolled out to customers within a strict deadline, e.g. new insurance policies. The products are also supposed to be modifiable during their period of service and should be verified and tested before being placed in service. In these industries, being able to create a new process or to change one quickly is providing one competitive advantage; carrying out business processes efficiently provides another. Rapid business process prototyping, in this case, is a practically motivated approach. This contribution presents a realistic business process modeling, verification, and prototyping framework by means of a formal Petri net-based specification language. By specifying process models using this language, executable process controllers can be automatically generated and smoothly integrated into a service-oriented architecture. Furthermore, formal verification techniques and tools can be used to detect errors during the design phase of the process","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121766445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Metzger, F. Bastien, F. Rousseau, J. Vachon, E. Aboulhamid
A new generation of CAD tools is mandatory to cope with the growing complexity of system-on-chip. We believe that they should be built on top of a modern and standard framework. ESys.NET is a design environment based on the .NET framework. It takes advantage of advanced programming features which facilitates the integration of external tools. This paper presents a semi-formal verification tool for ESys.NET. Introspection ability is emphasized together with its capabilities to cooperate with third party tools. Introspection is used to retrieve the state of the model during simulation and to check a set of user defined rules. Neither the model nor the simulator is modified by the verification process. Experimentations on an AMBA bus model highlight the effectiveness of this approach
{"title":"Introspection Mechanisms for Semi-Formal Verification in a System-Level Design Environment","authors":"M. Metzger, F. Bastien, F. Rousseau, J. Vachon, E. Aboulhamid","doi":"10.1109/RSP.2006.22","DOIUrl":"https://doi.org/10.1109/RSP.2006.22","url":null,"abstract":"A new generation of CAD tools is mandatory to cope with the growing complexity of system-on-chip. We believe that they should be built on top of a modern and standard framework. ESys.NET is a design environment based on the .NET framework. It takes advantage of advanced programming features which facilitates the integration of external tools. This paper presents a semi-formal verification tool for ESys.NET. Introspection ability is emphasized together with its capabilities to cooperate with third party tools. Introspection is used to retrieve the state of the model during simulation and to check a set of user defined rules. Neither the model nor the simulator is modified by the verification process. Experimentations on an AMBA bus model highlight the effectiveness of this approach","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"175 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113988551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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