In the best-effort IP network, packet delay/loss is inevitably degrade the perceptual quality of real-time multimedia service, such as Voice-over-IP (VoIP), video-on-demand (VoD), etc. Modeling, prototyping, and analysis of traffic traces have always been very important and challenging topics in the area of multimedia communication. In general, packet loss/delay exhibits temporal dependence. Different prototyping tools, such as Bernoulli model, Gilbert model, Extended Gilbert model, Markov model, etc, have been proposed to model network trace. In this research, one VoD server and three clients have been setup to simulate a real VoD system. Different models have been applied to analyze and model the video transmission network traces obtained under RTP/UDP/IP protocol stack. Compared to the other tools, Markov model offers the best prototyping precision, in the sense of loss-run distribution and forward error correction (FEC) performance prediction. As a powerful fast prototyping tool, Markov model is very useful to model and analyze network traces and further improve the QoS in multimedia-over-IP
{"title":"A Prototyping Tool for Analysis and Modeling of Video Transmission Traces over IP Networks","authors":"Ming Yang, N. Bourbakis","doi":"10.1109/RSP.2006.4","DOIUrl":"https://doi.org/10.1109/RSP.2006.4","url":null,"abstract":"In the best-effort IP network, packet delay/loss is inevitably degrade the perceptual quality of real-time multimedia service, such as Voice-over-IP (VoIP), video-on-demand (VoD), etc. Modeling, prototyping, and analysis of traffic traces have always been very important and challenging topics in the area of multimedia communication. In general, packet loss/delay exhibits temporal dependence. Different prototyping tools, such as Bernoulli model, Gilbert model, Extended Gilbert model, Markov model, etc, have been proposed to model network trace. In this research, one VoD server and three clients have been setup to simulate a real VoD system. Different models have been applied to analyze and model the video transmission network traces obtained under RTP/UDP/IP protocol stack. Compared to the other tools, Markov model offers the best prototyping precision, in the sense of loss-run distribution and forward error correction (FEC) performance prediction. As a powerful fast prototyping tool, Markov model is very useful to model and analyze network traces and further improve the QoS in multimedia-over-IP","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127518391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The communication architecture template tree (CAT-tree) is an abstraction of the specific range of communication functions and architectures, which can facilitate system function capture and communication architecture refinement. In this paper, we explain a TLM-RTL-SW mixed-level simulation environment that is useful for the functional verification of partially refined system models. We employed SystemC, GNU Gdb and a HDL simulator for the simulation of CATtree-based TLM, SW and HW, respectively. We also employed a new operating system, DEOS so that each SystemC-based TLMs can be cross-compiled to be executed as software models on the target processors. We evaluated the flexibility and simulation performance of the virtual simulation environment with an H.264 decoder design example
{"title":"A Mixed-Level Virtual Prototyping Environment for Refinement-Based Design Environment","authors":"Sanggyu Park, Sang-yong Yoon, S. Chae","doi":"10.1109/RSP.2006.3","DOIUrl":"https://doi.org/10.1109/RSP.2006.3","url":null,"abstract":"The communication architecture template tree (CAT-tree) is an abstraction of the specific range of communication functions and architectures, which can facilitate system function capture and communication architecture refinement. In this paper, we explain a TLM-RTL-SW mixed-level simulation environment that is useful for the functional verification of partially refined system models. We employed SystemC, GNU Gdb and a HDL simulator for the simulation of CATtree-based TLM, SW and HW, respectively. We also employed a new operating system, DEOS so that each SystemC-based TLMs can be cross-compiled to be executed as software models on the target processors. We evaluated the flexibility and simulation performance of the virtual simulation environment with an H.264 decoder design example","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127389899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In many industries, such as finance and insurance, business processes represent products which need to be rolled out to customers within a strict deadline, e.g. new insurance policies. The products are also supposed to be modifiable during their period of service and should be verified and tested before being placed in service. In these industries, being able to create a new process or to change one quickly is providing one competitive advantage; carrying out business processes efficiently provides another. Rapid business process prototyping, in this case, is a practically motivated approach. This contribution presents a realistic business process modeling, verification, and prototyping framework by means of a formal Petri net-based specification language. By specifying process models using this language, executable process controllers can be automatically generated and smoothly integrated into a service-oriented architecture. Furthermore, formal verification techniques and tools can be used to detect errors during the design phase of the process
{"title":"Generative Business Process Prototyping Framework","authors":"Ang Chen, Didier Buchs","doi":"10.1109/RSP.2006.20","DOIUrl":"https://doi.org/10.1109/RSP.2006.20","url":null,"abstract":"In many industries, such as finance and insurance, business processes represent products which need to be rolled out to customers within a strict deadline, e.g. new insurance policies. The products are also supposed to be modifiable during their period of service and should be verified and tested before being placed in service. In these industries, being able to create a new process or to change one quickly is providing one competitive advantage; carrying out business processes efficiently provides another. Rapid business process prototyping, in this case, is a practically motivated approach. This contribution presents a realistic business process modeling, verification, and prototyping framework by means of a formal Petri net-based specification language. By specifying process models using this language, executable process controllers can be automatically generated and smoothly integrated into a service-oriented architecture. Furthermore, formal verification techniques and tools can be used to detect errors during the design phase of the process","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121766445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Metzger, F. Bastien, F. Rousseau, J. Vachon, E. Aboulhamid
A new generation of CAD tools is mandatory to cope with the growing complexity of system-on-chip. We believe that they should be built on top of a modern and standard framework. ESys.NET is a design environment based on the .NET framework. It takes advantage of advanced programming features which facilitates the integration of external tools. This paper presents a semi-formal verification tool for ESys.NET. Introspection ability is emphasized together with its capabilities to cooperate with third party tools. Introspection is used to retrieve the state of the model during simulation and to check a set of user defined rules. Neither the model nor the simulator is modified by the verification process. Experimentations on an AMBA bus model highlight the effectiveness of this approach
{"title":"Introspection Mechanisms for Semi-Formal Verification in a System-Level Design Environment","authors":"M. Metzger, F. Bastien, F. Rousseau, J. Vachon, E. Aboulhamid","doi":"10.1109/RSP.2006.22","DOIUrl":"https://doi.org/10.1109/RSP.2006.22","url":null,"abstract":"A new generation of CAD tools is mandatory to cope with the growing complexity of system-on-chip. We believe that they should be built on top of a modern and standard framework. ESys.NET is a design environment based on the .NET framework. It takes advantage of advanced programming features which facilitates the integration of external tools. This paper presents a semi-formal verification tool for ESys.NET. Introspection ability is emphasized together with its capabilities to cooperate with third party tools. Introspection is used to retrieve the state of the model during simulation and to check a set of user defined rules. Neither the model nor the simulator is modified by the verification process. Experimentations on an AMBA bus model highlight the effectiveness of this approach","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"175 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113988551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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