The method of indeterminate coefficients is a strong tool to find out finite models satisfying a system of axioms and to prove that an axiom is independent from the other axioms. We describe the results which were obtained by investigating some systems of axioms based on the method. Then we show some remained problems.
{"title":"Clarifying the Systems of Axioms Based on the Method of Indeterminate Coefficients","authors":"T. Ninomiya, M. Mukaidono","doi":"10.1109/ISMVL.2009.67","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.67","url":null,"abstract":"The method of indeterminate coefficients is a strong tool to find out finite models satisfying a system of axioms and to prove that an axiom is independent from the other axioms. We describe the results which were obtained by investigating some systems of axioms based on the method. Then we show some remained problems.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123954363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Md. Mahmud Muntakim Khan, A. Biswas, S. Chowdhury, M. Hasan, A. Khan
We present a method of synthesizing Ternary GaloisField (GF(3)) based reversible/quantum logic circuits without any ancillary trits/qutrits and hence without any garbage outputs. We realize multi input ternary Toffoli gate and square functions of GF(3) variables using linear ion trap realizable Muthukrishnan-Stroud (M-S) gates and shift gates in the absence of ancillary qutrits. Then based on the Galois Field Sum of Products (GFSOP)expression of a multi-variable GF(3) function, we synthesize the corresponding circuit.
{"title":"Synthesis of GF(3) Based Reversible/Quantum Logic Circuits without Garbage Output","authors":"Md. Mahmud Muntakim Khan, A. Biswas, S. Chowdhury, M. Hasan, A. Khan","doi":"10.1109/ISMVL.2009.73","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.73","url":null,"abstract":"We present a method of synthesizing Ternary GaloisField (GF(3)) based reversible/quantum logic circuits without any ancillary trits/qutrits and hence without any garbage outputs. We realize multi input ternary Toffoli gate and square functions of GF(3) variables using linear ion trap realizable Muthukrishnan-Stroud (M-S) gates and shift gates in the absence of ancillary qutrits. Then based on the Galois Field Sum of Products (GFSOP)expression of a multi-variable GF(3) function, we synthesize the corresponding circuit.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122936778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Masaki Murozuka, Kazumasa Ikeura, F. Adachi, K. Machida, T. Waho
Decimation filters for high-speed oversampling delta-sigma converters have been investigated by using signed-digit adders. Time-interleaved technique is introduced to a polyphase FIR filter to overcome operation speed limitation due to the setup and hold time constraint for delayed flip-flops. It is found that in this architecture, the adder tree based on ternary signed-digit full adders effectively improves the operation speed. A third-order filters with a decimation factor of 8 is designed by assuming a 0.18-μm standard CMOS technology. Signal-levelsimulation shows that the operation frequency of the present time-interleaved filter is improved by 20% compared withconventional polyphase filters.
{"title":"Time-Interleaved Polyphase Decimation Filter Using Signed-Digit Adders","authors":"Masaki Murozuka, Kazumasa Ikeura, F. Adachi, K. Machida, T. Waho","doi":"10.1109/ISMVL.2009.49","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.49","url":null,"abstract":"Decimation filters for high-speed oversampling delta-sigma converters have been investigated by using signed-digit adders. Time-interleaved technique is introduced to a polyphase FIR filter to overcome operation speed limitation due to the setup and hold time constraint for delayed flip-flops. It is found that in this architecture, the adder tree based on ternary signed-digit full adders effectively improves the operation speed. A third-order filters with a decimation factor of 8 is designed by assuming a 0.18-μm standard CMOS technology. Signal-levelsimulation shows that the operation frequency of the present time-interleaved filter is improved by 20% compared withconventional polyphase filters.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129044278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a new quantum array that can be used to control a single-qudit hermitian operator for an odd radix r ≫ 2 by n controls using Theta(n^log_2 r + 2) single-qudit controlled gates with one control and no ancilla qudits. This quantum array is more practical than existing quantum arrays of the same complexity because it does not require the use of small roots of the operation that is being implemented. Another quantum array is also presented that implements a single-qudit operator with n controls for any radix r ≫ 2 using ceiling(log_(r - 1) n) ancilla qudits and Theta(n^(log_(r - 1) 2 + 1)) single-qudit gates with one control.
本文介绍了一种新的量子阵列，通过使用θ(n^log_2 r + 2)单量子受控门，使用一个控制和无辅助量子的 n 个控制，可以用来控制奇数弧度 r ≫ 2 的单量子赫米特算子。这种量子阵列比相同复杂度的现有量子阵列更实用，因为它不需要使用小根来实现操作。本文还介绍了另一种量子阵列，它使用 ceiling(log_(r - 1) n) ancilla 量子和 Theta(n^(log_(r - 1) 2 + 1) 单控制门实现了任意弧度 r ≫ 2 的具有 n 个控制的单位运算器。
{"title":"Efficient Implementation of Controlled Operations for Multivalued Quantum Logic","authors":"David J. Rosenbaum, M. Perkowski","doi":"10.1109/ISMVL.2009.27","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.27","url":null,"abstract":"This paper presents a new quantum array that can be used to control a single-qudit hermitian operator for an odd radix r ≫ 2 by n controls using Theta(n^log_2 r + 2) single-qudit controlled gates with one control and no ancilla qudits. This quantum array is more practical than existing quantum arrays of the same complexity because it does not require the use of small roots of the operation that is being implemented. Another quantum array is also presented that implements a single-qudit operator with n controls for any radix r ≫ 2 using ceiling(log_(r - 1) n) ancilla qudits and Theta(n^(log_(r - 1) 2 + 1)) single-qudit gates with one control.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129775157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A multiple-valued reconfigurable VLSI useful for improving the utilization ratio of hardware resources is proposed. Hybrid architecture based on wired programming and dynamic data-path control can be effectively employed for high utilization ratio of hardware resources with small overhead of additional hardware resources. A 2-to-1 multiplexer is provided in each cell. Accordingly, distributed control can be realized simply, so that interconnections between arithmetic logic modules and controllers become very short. Moreover, superposition of data and control signals is introduced to reduce not only complexity of interconnections but also switch block area.
{"title":"Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals","authors":"N. Okada, M. Kameyama","doi":"10.1109/ISMVL.2009.62","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.62","url":null,"abstract":"A multiple-valued reconfigurable VLSI useful for improving the utilization ratio of hardware resources is proposed. Hybrid architecture based on wired programming and dynamic data-path control can be effectively employed for high utilization ratio of hardware resources with small overhead of additional hardware resources. A 2-to-1 multiplexer is provided in each cell. Accordingly, distributed control can be realized simply, so that interconnections between arithmetic logic modules and controllers become very short. Moreover, superposition of data and control signals is introduced to reduce not only complexity of interconnections but also switch block area.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125726729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the design of a multiple-valued adder for tamper-resistant cryptographic processors. The proposed adder is implemented in Multiple-Valued Current-Mode Logic (MV-CML). The important feature of MV-CML is that the power consumption can be constant regardless of the input values, which makes it possible to prevent power analysis attacks using dependencies between power consumption and intermediate values or operations of the executed cryptographic algorithms. In this paper, we present a multiple-valued constant-power adder based on the binary Positive-Digit (PD) number system and its application to RSA processors. The power characteristic of the proposed adder is evaluated with HSPICE simulation using 90nm process technology. The proposed design can achieve constant power consumption with low performance overhead in comparison with the conventional binary design.
{"title":"Multiple-Valued Constant-Power Adder for Cryptographic Processors","authors":"Yuichi Baba, A. Miyamoto, N. Homma, T. Aoki","doi":"10.1109/ISMVL.2009.9","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.9","url":null,"abstract":"This paper presents the design of a multiple-valued adder for tamper-resistant cryptographic processors. The proposed adder is implemented in Multiple-Valued Current-Mode Logic (MV-CML). The important feature of MV-CML is that the power consumption can be constant regardless of the input values, which makes it possible to prevent power analysis attacks using dependencies between power consumption and intermediate values or operations of the executed cryptographic algorithms. In this paper, we present a multiple-valued constant-power adder based on the binary Positive-Digit (PD) number system and its application to RSA processors. The power characteristic of the proposed adder is evaluated with HSPICE simulation using 90nm process technology. The proposed design can achieve constant power consumption with low performance overhead in comparison with the conventional binary design.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123883879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a Pulse-Width Modulation (PWM) pre-emphasis technique which utilizes time-domain information processing to increase the data rate for a given bandwidth of interconnection. The PWM pre-emphasis method does not change the pulse amplitude as for conventional FIR pre-emphasis, but instead exploits timing resolution. This fits well with recent CMOS technology trends toward higher switching speeds and lower voltage headroom. We discuss multiple-valued data transmission based on time-domain pre-emphasis techniques in consideration of higher-order channel effects.
{"title":"Multiple-Valued Data Transmission Based on Time-Domain Pre-emphasis Techniques in Consideration of Higher-Order Channel Effects","authors":"Y. Yuminaka, Yasunori Takahashi, Kenichi Henmi","doi":"10.1109/ISMVL.2009.71","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.71","url":null,"abstract":"This paper describes a Pulse-Width Modulation (PWM) pre-emphasis technique which utilizes time-domain information processing to increase the data rate for a given bandwidth of interconnection. The PWM pre-emphasis method does not change the pulse amplitude as for conventional FIR pre-emphasis, but instead exploits timing resolution. This fits well with recent CMOS technology trends toward higher switching speeds and lower voltage headroom. We discuss multiple-valued data transmission based on time-domain pre-emphasis techniques in consideration of higher-order channel effects.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125009785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Design and implementation of a novel 16-level multiple-valued memory is proposed. Each memory cell uses equivalent to one binary digit to detect the error due to leakage currents. Moreover, this feature increases the noise margin of the system by a factor of two. The refreshing circuitry is based on a series configuration of A/D and D/A converters for each data line. The error correction and storage scheme is based on a recently developed Multiple-Valued representation, calledContinuous Valued Number System (CVNS). This memory cell can be used in hardware implementation of multiple-valued neural networks based on the CVNS.
{"title":"16-level Current-Mode Multiple-Valued Dynamic Memory with Increased Noise Margin","authors":"G. Khodabandehloo, M. Mirhassani, M. Ahmadi","doi":"10.1109/ISMVL.2009.12","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.12","url":null,"abstract":"Design and implementation of a novel 16-level multiple-valued memory is proposed. Each memory cell uses equivalent to one binary digit to detect the error due to leakage currents. Moreover, this feature increases the noise margin of the system by a factor of two. The refreshing circuitry is based on a series configuration of A/D and D/A converters for each data line. The error correction and storage scheme is based on a recently developed Multiple-Valued representation, calledContinuous Valued Number System (CVNS). This memory cell can be used in hardware implementation of multiple-valued neural networks based on the CVNS.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133729024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Multiple-valued Feynman and Toffoli gates are used in GFSOP based synthesis of quantum logic circuits. These gates are macro-level gates and need to be realized using technology dependent primitive gates. In this paper, we present ancilla input free architectures for realization of d-valued (d≫=3 ) Feynman and n-qudit (n≫=3 ) Toffoli gates on the top of liquid ion-trap realizable Muthukrishnan-Stroud gates. The proposed architectures can be used for any d if GF(d) can be constructed. We show realization examples of ternary, quaternary, and quinary Feynman gates, and 3 and 4-qudit Toffoli gates. The present realizations require either less or equal primitive gates than the previously reported realizations. Moreover, in contrast to the earlier realizations, the present Toffoli gate realizations do not require any ancilla input, which reduce the register width of a synthesized quantum logic circuit.
{"title":"Quantum Realization of Multiple-Valued Feynman and Toffoli Gates without Ancilla Input","authors":"Mozammel H. A. Khan","doi":"10.1109/ISMVL.2009.17","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.17","url":null,"abstract":"Multiple-valued Feynman and Toffoli gates are used in GFSOP based synthesis of quantum logic circuits. These gates are macro-level gates and need to be realized using technology dependent primitive gates. In this paper, we present ancilla input free architectures for realization of d-valued (d≫=3 ) Feynman and n-qudit (n≫=3 ) Toffoli gates on the top of liquid ion-trap realizable Muthukrishnan-Stroud gates. The proposed architectures can be used for any d if GF(d) can be constructed. We show realization examples of ternary, quaternary, and quinary Feynman gates, and 3 and 4-qudit Toffoli gates. The present realizations require either less or equal primitive gates than the previously reported realizations. Moreover, in contrast to the earlier realizations, the present Toffoli gate realizations do not require any ancilla input, which reduce the register width of a synthesized quantum logic circuit.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133827523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We define a number of original encodings, called regular encodings, that map Max-CSP instances into Partial Max-SAT instances. First, we obtain new direct and (minimal)support encodings by modelling the at-least-one and at-most-one conditions using a regular signed encoding. This way, we obtain encodings in which the hard part is more compact. Second, even when we need to introduce auxiliary variables in the regular encodings, we prove that it is sufficient to limit branching to non-auxiliary variables. Third, we report on an experimental investigation which provides evidence that the minimal support encoding is well-suited on more structured, realistic instances (the experiments performed so far were limited to randomly generated binary CSPs), and that the regular encodings defined here have a very competitive performance profile when branching is limited to non-auxiliary variables. We show that regular encodings allow to solve more instances and more efficiently than using the existing encodings from Max-CSP into Partial Max-SAT.
{"title":"Regular Encodings from Max-CSP into Partial Max-SAT","authors":"Josep Argelich, Alba Cabiscol, I. Lynce, F. Manyà","doi":"10.1109/ISMVL.2009.23","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.23","url":null,"abstract":"We define a number of original encodings, called regular encodings, that map Max-CSP instances into Partial Max-SAT instances. First, we obtain new direct and (minimal)support encodings by modelling the at-least-one and at-most-one conditions using a regular signed encoding. This way, we obtain encodings in which the hard part is more compact. Second, even when we need to introduce auxiliary variables in the regular encodings, we prove that it is sufficient to limit branching to non-auxiliary variables. Third, we report on an experimental investigation which provides evidence that the minimal support encoding is well-suited on more structured, realistic instances (the experiments performed so far were limited to randomly generated binary CSPs), and that the regular encodings defined here have a very competitive performance profile when branching is limited to non-auxiliary variables. We show that regular encodings allow to solve more instances and more efficiently than using the existing encodings from Max-CSP into Partial Max-SAT.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129129556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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