Quaternary reversible logic is very suitable for encoded realization of binary reversible logic functions by grouping two bits together into quaternary digits. Quaternary multiplexer and demultiplexer circuits are very important building blocks of quaternary digital systems. In this paper, we show reversible realizations of 4x1 multiplexer and 1x4 demultiplexer circuits on the top of liquid ion-trap realizable 1x1 and Muthukrishnan-Stroud gates. Then we show scalable architectures for design of mx1 multiplexer and 1xm demultiplexer circuits using 4x1 multiplexers and 1x4 demultiplexers, respectively, where m ≤ 4n and n is the number of selection inputs. The proposed realizations of reversible multiplexer and demultiplexer circuits are more efficient than the earlier realizations in terms of number of primitive gates and number of ancilla inputs required.
{"title":"Scalable Architectures for Design of Reversible Quaternary Multiplexer and Demultiplexer Circuits","authors":"Mozammel H. A. Khan","doi":"10.1109/ISMVL.2009.26","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.26","url":null,"abstract":"Quaternary reversible logic is very suitable for encoded realization of binary reversible logic functions by grouping two bits together into quaternary digits. Quaternary multiplexer and demultiplexer circuits are very important building blocks of quaternary digital systems. In this paper, we show reversible realizations of 4x1 multiplexer and 1x4 demultiplexer circuits on the top of liquid ion-trap realizable 1x1 and Muthukrishnan-Stroud gates. Then we show scalable architectures for design of mx1 multiplexer and 1xm demultiplexer circuits using 4x1 multiplexers and 1x4 demultiplexers, respectively, where m ≤ 4n and n is the number of selection inputs. The proposed realizations of reversible multiplexer and demultiplexer circuits are more efficient than the earlier realizations in terms of number of primitive gates and number of ancilla inputs required.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122903882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A partial function f on a k-element set Ek is a partial Sheffer function if every partial function on Ek is definable in terms of f. Since this holds if and only if f belongs to no maximal partial clone on Ek, a characterization of partial Sheffer functions reduces to finding families of minimal coverings of maximal partial clones on Ek. We show that for each k ≫= 3 there exists a unique minimal covering.
{"title":"Minimal Coverings of Maximal Partial Clones","authors":"Karsten Schölzel","doi":"10.1109/ISMVL.2009.32","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.32","url":null,"abstract":"A partial function f on a k-element set Ek is a partial Sheffer function if every partial function on Ek is definable in terms of f. Since this holds if and only if f belongs to no maximal partial clone on Ek, a characterization of partial Sheffer functions reduces to finding families of minimal coverings of maximal partial clones on Ek. We show that for each k ≫= 3 there exists a unique minimal covering.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117235883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Several methods of rough sets that are applied to data tables containing missing values are examined from the viewpoint of the method of possible worlds. It is clarified that the previous methods do not give the same results as the method of possible worlds. This is due to that the previous methods consider either of indicernibility or discernibility of missing values.In order to improve this point, a new method, called a method of possible equivalence classes, is described. By using possible equivalence classes, both indiscernibility and discernibility of missing values are taken into account. As a result, the method of possible equivalence classes gives the same results as the method of possible worlds.In addition, by using the maximal possible equivalence classes, not all possible equivalence classes, rough approximations are efficiently obtained.
{"title":"Applying Rough Sets to Information Tables Containing Missing Values","authors":"M. Nakata, H. Sakai","doi":"10.1109/ISMVL.2009.1","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.1","url":null,"abstract":"Several methods of rough sets that are applied to data tables containing missing values are examined from the viewpoint of the method of possible worlds. It is clarified that the previous methods do not give the same results as the method of possible worlds. This is due to that the previous methods consider either of indicernibility or discernibility of missing values.In order to improve this point, a new method, called a method of possible equivalence classes, is described. By using possible equivalence classes, both indiscernibility and discernibility of missing values are taken into account. As a result, the method of possible equivalence classes gives the same results as the method of possible worlds.In addition, by using the maximal possible equivalence classes, not all possible equivalence classes, rough approximations are efficiently obtained.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"296 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121826011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a method to derive functional expressions that have an a priory specified number of product terms for various classes of multiple-valued functions. The method exploits the theory of covering codes and it can be tailored for various classes (different sets for values of variables and function values) of multiple-valued functions by selecting appropriately the underlying covering code. The number of product terms in the related functional expression is determined by the covering radius of the code. We present an algorithm to determine the coefficients in these expressions, discuss its complexity, and provide a direct construction to extend the application of this approach to multiple-valued functions for a large number of variables.
{"title":"Application of Covering Codes for Reduced Representations of Logic Functions","authors":"J. Astola, R. Stankovic","doi":"10.1109/ISMVL.2009.72","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.72","url":null,"abstract":"This paper presents a method to derive functional expressions that have an a priory specified number of product terms for various classes of multiple-valued functions. The method exploits the theory of covering codes and it can be tailored for various classes (different sets for values of variables and function values) of multiple-valued functions by selecting appropriately the underlying covering code. The number of product terms in the related functional expression is determined by the covering radius of the code. We present an algorithm to determine the coefficients in these expressions, discuss its complexity, and provide a direct construction to extend the application of this approach to multiple-valued functions for a large number of variables.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125026424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power-supply/temperature-variation-aware circuit components, such as a current source and a comparator, based on adaptive reference-voltage control are proposedfor robust multiple-valued current-mode (MVCM) circuits.Since the reference-voltage level generated by the proposed reference-voltage generator is changed in proportion to the power supply, the gate-source voltage VGS of PMOS transistor at the current source becomes almost constantagainst the power-supply variation, which results in realization of the power-supply-tolerant current source.The use of programming the gate size at the proposed reference-voltage generator makes the logical threshold voltage at the comparator changed in accordance with the input-voltage variation due to the power-supply/temperature variation, which results in correctly recognition of the multi-level current signal. As a design example of the MVCM circuits, a seven-level current-signal detector including the current source is demonstrated under a 90nm CMOS technology. As a result, the proposed circuit is correctly operated in the operation range 1.0V to 1.4V of the power supply under 25 degC $pm$ 50 degC variation of the temperature.
{"title":"Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control","authors":"N. Onizawa, T. Hanyu","doi":"10.1109/ISMVL.2009.44","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.44","url":null,"abstract":"Power-supply/temperature-variation-aware circuit components, such as a current source and a comparator, based on adaptive reference-voltage control are proposedfor robust multiple-valued current-mode (MVCM) circuits.Since the reference-voltage level generated by the proposed reference-voltage generator is changed in proportion to the power supply, the gate-source voltage VGS of PMOS transistor at the current source becomes almost constantagainst the power-supply variation, which results in realization of the power-supply-tolerant current source.The use of programming the gate size at the proposed reference-voltage generator makes the logical threshold voltage at the comparator changed in accordance with the input-voltage variation due to the power-supply/temperature variation, which results in correctly recognition of the multi-level current signal. As a design example of the MVCM circuits, a seven-level current-signal detector including the current source is demonstrated under a 90nm CMOS technology. As a result, the proposed circuit is correctly operated in the operation range 1.0V to 1.4V of the power supply under 25 degC $pm$ 50 degC variation of the temperature.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131946282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Granular reasoning proposed by Murai et al. is a mechanism for reasoning using granular computing, and the concept of "focus" has been proposed as a key concept of granular reasoning. On the other hand,the authors have redefined the concept of focus, and have proposed another concept of granularity, called visibility. However, as a result of the redefinition of focus, calculation of focus is very difficult because we need to check each atomic sentence in the visibility whether the atomic sentence is implied from the set of sentences we use in the current step of reasoning. In this paper, we propose a calculation method of focus in granular reasoning based on attribute reduction of rough set theory.
{"title":"Attribute Reduction as Calculation of Focus in Granular Reasoning","authors":"Y. Kudo, T. Murai","doi":"10.1109/ISMVL.2009.36","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.36","url":null,"abstract":"Granular reasoning proposed by Murai et al. is a mechanism for reasoning using granular computing, and the concept of \"focus\" has been proposed as a key concept of granular reasoning. On the other hand,the authors have redefined the concept of focus, and have proposed another concept of granularity, called visibility. However, as a result of the redefinition of focus, calculation of focus is very difficult because we need to check each atomic sentence in the visibility whether the atomic sentence is implied from the set of sentences we use in the current step of reasoning. In this paper, we propose a calculation method of focus in granular reasoning based on attribute reduction of rough set theory.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114995459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A power-aware voltage-scheduling heuristic with offline and online components is presented for a hard real-time multi-processor system supporting multiple voltage levels. The offline component determines a voltage configuration for each task in a graph according to the worst-case scenario of task execution, to speed up paths with tasks. Once some path is speeded up, it next chooses and speeds up one of the paths sharing tasks with that path. The online component reclaims the slack, which occurs when some task actually finishes, to slow down the execution speed of its successor. Simulations are made to show the effectiveness of the proposed heuristic.
{"title":"A Two-Pronged Approach of Power-Aware Voltage Scheduling for Real-Time Task Graphs in Multi-processor Systems","authors":"N. Kamiura, A. Saitoh, T. Isokawa, N. Matsui","doi":"10.1109/ISMVL.2009.29","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.29","url":null,"abstract":"A power-aware voltage-scheduling heuristic with offline and online components is presented for a hard real-time multi-processor system supporting multiple voltage levels. The offline component determines a voltage configuration for each task in a graph according to the worst-case scenario of task execution, to speed up paths with tasks. Once some path is speeded up, it next chooses and speeds up one of the paths sharing tasks with that path. The online component reclaims the slack, which occurs when some task actually finishes, to slow down the execution speed of its successor. Simulations are made to show the effectiveness of the proposed heuristic.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129680765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Syoji Kobashi, Y. Fujimoto, M. Ogawa, K. Ando, R. Ishikura, S. Imawaki, S. Hirota, Y. Hata
There are various cerebral diseases that deform the cerebral shape with region specificity. So it is effective to quantify the deformation change of cerebral gyri. This study introduces new index called gyral deformation index (GDI) that is defined as a ratio of area of gyrus of interest to area of cerebrum in the defined projection plane. To calculate the gyral areas, this paper proposes a gyral labeling method in the projection plane using magnetic resonance images. The new method finds the boundaries between the gyri by optimizing deformable boundary models aided by fuzzy logic. The proposed method was applied to quantify the cerebral deformation of infants on a plane which is perpendicular to the longitudinal fissure. The comparison results with the manual delineation showed that the method labels gyri with a mean sensitivity of 92.8% and a mean false positive rate of 0.1% for 14 infantile subjects (3 weeks – 4 years 3 months old).
{"title":"Fuzzy Logic Assisted Quantification of Gyral Deformation Index Using Magnetic Resonance Images for the Infantile Brain","authors":"Syoji Kobashi, Y. Fujimoto, M. Ogawa, K. Ando, R. Ishikura, S. Imawaki, S. Hirota, Y. Hata","doi":"10.1109/ISMVL.2009.14","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.14","url":null,"abstract":"There are various cerebral diseases that deform the cerebral shape with region specificity. So it is effective to quantify the deformation change of cerebral gyri. This study introduces new index called gyral deformation index (GDI) that is defined as a ratio of area of gyrus of interest to area of cerebrum in the defined projection plane. To calculate the gyral areas, this paper proposes a gyral labeling method in the projection plane using magnetic resonance images. The new method finds the boundaries between the gyri by optimizing deformable boundary models aided by fuzzy logic. The proposed method was applied to quantify the cerebral deformation of infants on a plane which is perpendicular to the longitudinal fissure. The comparison results with the manual delineation showed that the method labels gyri with a mean sensitivity of 92.8% and a mean false positive rate of 0.1% for 14 infantile subjects (3 weeks – 4 years 3 months old).","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132676836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, I will show how multi-valued logics are used for model checking. Model checking is an automatic technique to analyze correctness of hardware and software systems. A model checker is based on a temporal logic or a modal fixed point logic. That is to say, a system to be checked is formalized as a Kripke model, a property to be satisfied by the system is formalized as a temporal formula or a modal formula, and the model checker checks that the Kripke model satisfies the formula. Although most existing model checkers are based on 2-valued logics, recently new attempts have been made to extend the underlying logics of model checkers to multi-valued logics. I will show these new results.
{"title":"Multi-valued Modal Fixed Point Logics for Model Checking","authors":"Koki Nishizawa","doi":"10.1109/ISMVL.2009.57","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.57","url":null,"abstract":"In this paper, I will show how multi-valued logics are used for model checking. Model checking is an automatic technique to analyze correctness of hardware and software systems. A model checker is based on a temporal logic or a modal fixed point logic. That is to say, a system to be checked is formalized as a Kripke model, a property to be satisfied by the system is formalized as a temporal formula or a modal formula, and the model checker checks that the Kripke model satisfies the formula. Although most existing model checkers are based on 2-valued logics, recently new attempts have been made to extend the underlying logics of model checkers to multi-valued logics. I will show these new results.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131021892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Counting solutions of various combinatorial problems is a well established and intensively studied area of theoretical computer science. Its applications range from networking to statistical physics. The central question in this area is the complexity of and algorithms for problems of this type. It turns out that in many important cases these questions can be answered with aid of certain clones of functions of multi-valued logic. We show the connection between the two areas and survey recent advances in this research direction.
{"title":"Counting Problems and Clones of Functions","authors":"A. Bulatov, Amir Hedayaty","doi":"10.1109/ISMVL.2009.47","DOIUrl":"https://doi.org/10.1109/ISMVL.2009.47","url":null,"abstract":"Counting solutions of various combinatorial problems is a well established and intensively studied area of theoretical computer science. Its applications range from networking to statistical physics. The central question in this area is the complexity of and algorithms for problems of this type. It turns out that in many important cases these questions can be answered with aid of certain clones of functions of multi-valued logic. We show the connection between the two areas and survey recent advances in this research direction.","PeriodicalId":115178,"journal":{"name":"2009 39th International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130578028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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