Electronics Letters最新文献

A 12-bit 200 MS/s current-steering DAC is designed for low-voltage, low-power​ applications. By incorporating a partially randomised DEM (PRDEM) and ‘always-on’ current sources, the design simultaneously suppresses static mismatch and dynamic glitches while operating under reduced supply voltage. Measurement results show a 65.65-dB SFDR, which validates the effectiveness of the proposed techniques in achieving high dynamic range within strict power constraints.

To address the miniaturization requirement for W-band frequency modulated continuous wave radar front-ends, a transceiver chip was fabricated using 0.1 µm GaAs pHEMT technology. The design achieves 76–81 GHz broadband matching while resolving the compatibility challenge between high isolation and low loss in W-band monolithic front-ends. The chip integrates a mixer, directional coupler, filter and other modules simultaneously. A passive single-balanced mixer employing reverse-parallel Schottky diodes and a three-coupled-line Marchand balun structure serves as the core component. Measured at radio frequency = 76–81 GHz and intermediate frequency = 1 MHz–1 GHz, the chip achieves the conversion loss < 15 dB, local oscillation (LO)–intermediate frequency (IF) isolation > 36 dB and radio frequency (RF)–IF isolation > 25 dB.

This paper presents a wide-range, fast-lock duty-cycle corrector (DCC) with a 5-bit successive-approximation register (SAR). An inverter-based bang-bang duty-cycle detector (BBDCD) is equalised before each comparison to suppress hysteresis, enabling deterministic decisions and a fixed 4-cycle per-bit schedule. The duty-cycle adjuster (DCA) uses a controller frequency code for range adjustment and applies delay equalisation to limit code-dependent delay during updates. A half-LSB post-bias then halves the SAR quantisation-error bound without extra cycles. Post-layout simulations in 28-nm CMOS show operation from 0.8 to 3.2 GHz over 38%–62% input duty with a 20-cycle lock, ≤1.0% maximum duty error, and 1.73 mW at 3.2 GHz.

This letter proposes reflectionless linearly and circularly polarised patch antennas based on loading complementary absorptive branches. By establishing the equivalent circuit model of a conventional patch antenna, the complementary absorptive branch could be designed to dissipate the out-of-band energy through the grounded resistor, thereby achieving the reflectionless performance. Based on this concept, reflectionless linearly and circularly polarised patch antennas are designed and fabricated. Both antennas operate at 3.5 GHz. Measured results indicate that the linearly polarised patch antenna has a wide reflectionless frequency range of about 105% (1.71–5.4 GHz), with a peak radiation gain of 8.25 dBi. The circularly polarised patch antenna has a reflectionless frequency range of 68% (2.07–4.44 GHz), with the axial ratio (AR) bandwidth of 4.8%, stable radiation of right-handed circular polarisation (RHCP), and a peak radiation gain of 8.02 dBic.

Time synchronisation over power lines faces limitations in precision and range due to channel noise and asymmetry. This paper presents a high-accuracy synchronisation system using Power Line Carrier Communication (PLCC) enhanced with a threshold-limited sliding average algorithm. By integrating two-way time transfer with robust PLCC encoding, the proposed method adaptively filters time-difference fluctuations and compensates for path asymmetry. Experimental validation on a 900-metre active power line under real-world interference achieved a Time Deviation (TDEV) of 150 ns at 100,000 s. Comparative analysis demonstrates that the proposed approach attains precision comparable to that of the Precision Time Protocol (PTP) at 10% of the cost, while outperforming the Network Time Protocol (NTP) by three orders of magnitude. This work provides a cost-effective, infrastructure-free solution for smart grids, industrial automation, and other time-critical applications, enabling sub-microsecond accuracy without dedicated cabling.

Multi-head latent attention (MLA), introduced in DeepSeek-V2, improves the efficiency of large language models by projecting query, key and value tensors into a compact latent space. This architectural change reduces the KV-cache size and significantly lowers memory bandwidth demands, particularly in the autoregressive decode phase. This letter presents the first hardware-centric analysis of MLA, comparing it to conventional multi-head attention (MHA) and evaluating its implications for accelerator performance. We identify two alternative execution schemes of MLA-reusing, respectively recomputing latent projection matrices—which offer distinct trade-offs between compute and memory access. Using the Stream design space exploration framework, we model their throughput and energy cost across a range of hardware platforms and find that MLA can shift attention workloads toward the compute-bound regime. Our results show that MLA not only reduces bandwidth usage but also enables adaptable execution strategies aligned with hardware constraints. Compared to MHA, it provides more stable and efficient performance, particularly on bandwidth-limited hardware platforms. These findings emphasize MLA's relevance as a co-design opportunity for future AI accelerators.

RETRACTION: J. Huang, and S. Lale, “A Novel Nano-Scale Architecture of Vedic Multiplier Using Majority Logic in Quantum-Dot Cellular Automata Technology,” Electronics Letters 58, no 17 (2022): 660–662, https://doi.org/10.1049/ell2.12552.

The above article, published online on 13 June 2022 in Wiley Online Library (wileyonlinelibrary.com), has been retracted by agreement between the journal Editor-in-Chief, Paolo S. Crovetti; The Institution of Engineering and Technology; and John Wiley & Sons Ltd.

The retraction has been agreed due to concerns raised by the first author that they were not involved with the article in any capacity. Upon investigation, we also identified some unusual changes in the submitting author's email and ORCID IDs. We contacted the submitting author to clarify the concerns, but received no response. As we cannot verify the authorship of the publication and have serious concerns about the accountability of the research, we have taken the decision to retract the article. The authors have been informed of the decision to retract.

This letter proposes a convolutional neural network–bidirectional long short-term memory (CNN-BiLSTM) architecture for continuous phase modulation (CPM) signal detection by optimising the extraction of time-frequency features and temporal dependencies with reduced complexity. It significantly outperforms the existing maximum likelihood sequence detection (MLSD) and CNN with fully connected layer (CNN-FC) detectors in higher-order modulation and multipath scenarios, achieving a 97.99% parameter reduction compared to CNN-FC. Numerical results confirm its exceptional balance of detection performance and computational efficiency, making it ideal for complex channels and resource-constrained systems.

This work proposes a 6T1R non-volatile SRAM (nvSRAM) cell based on resistive memory (RRAM) with a small area overhead and low store power compared to previous designs. It features (1) reusing the transistors in the SRAM cell for accessing the RRAM cell, (2) a voltage-division (VD)-based restore process with reduced DC current and (3) a trimmable multi-cycle (TMC) store process to reduce data backup and recovery errors. We fabricated a 1 kb VD-6T1R nvSRAM test array with back-end-of-line integrated metal oxide RRAM cells in a 180 nm CMOS process. The reuse of transistors allows the VD-6T1R cell structure to occupy only 1.14× the area of a standard 6T SRAM cell. The store and restore operations were experimentally verified at the array level. The restore error rates of the fabricated test array can be effectively suppressed using TMC store cycles. The restore errors in the fabricated 1 kb cell array can be eliminated after five cycles.

Digital-domain self-interference cancellation (SIC) technology effectively mitigates self-interference by reconstructing the SI signal. Due to the high computational complexity of the traditional recursive least squares (RLS) algorithm in SIC, its real-time engineering application capability is limited. To overcome this limitation, this paper proposes the application of the DCD-RLS algorithm to SIC. The proposed method transforms the standard normal equations of the RLS algorithm into auxiliary normal equations and incorporates a bisection search strategy, thereby significantly reducing the computational complexity while maintaining optimal convergence performance. Simulation results demonstrate that the proposed algorithm not only achieves a significant reduction in computational complexity but also retains SIC performance, thus enhancing the implementation value of in-band full-duplex (IBFD) communication systems.We propose an RLS-SIC algorithm based on dichotomous coordinate descent (DCD), that converts the RLS normal equations into auxiliary equations and uses a bisection search to greatly reduce computational complexity while preserving optimal convergence. Simulations show, the method maintains self-interference cancellation performance with much lower complexity, improving the real-time feasibility of in-band full-duplex communication systems.