Virtual Worlds (VWs) are computer-simulated virtual environments accessed by multiple users through their avatars. VWs constitute a growing space for collaborative play, learning and work. Usability evaluation for VWs brings new challenges. There is a need for new evaluation methods or at least an extensive use of traditional evaluations in novel ways. The paper describes the development process of a new set of usability heuristics for VWs applications, including their early validation through two case studies. A usability checklist to use when applying VWs heuristics is also proposed.
{"title":"Defining Virtual Worlds Usability Heuristics","authors":"R. Muñoz-Soto, Virgínia Chalegre","doi":"10.1109/ITNG.2012.138","DOIUrl":"https://doi.org/10.1109/ITNG.2012.138","url":null,"abstract":"Virtual Worlds (VWs) are computer-simulated virtual environments accessed by multiple users through their avatars. VWs constitute a growing space for collaborative play, learning and work. Usability evaluation for VWs brings new challenges. There is a need for new evaluation methods or at least an extensive use of traditional evaluations in novel ways. The paper describes the development process of a new set of usability heuristics for VWs applications, including their early validation through two case studies. A usability checklist to use when applying VWs heuristics is also proposed.","PeriodicalId":117236,"journal":{"name":"2012 Ninth International Conference on Information Technology - New Generations","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121653638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
There have been several proposals for transforming and querying XML structures, but very few of them offer a data logic approach. This article describes data structures and some primitives as a framework to efficiently manipulate XML well-formed documents. The implementation of the querying system, based on the proposed framework, is performed in the Prolog programming language. Results indicate that this approach allows the solution of both deductive and recursive queries from XML documents.
{"title":"XML Querying Using Data Logic Structures and Primitives","authors":"J. U. Quevedo-Torrero, G. Erickson","doi":"10.1109/ITNG.2012.119","DOIUrl":"https://doi.org/10.1109/ITNG.2012.119","url":null,"abstract":"There have been several proposals for transforming and querying XML structures, but very few of them offer a data logic approach. This article describes data structures and some primitives as a framework to efficiently manipulate XML well-formed documents. The implementation of the querying system, based on the proposed framework, is performed in the Prolog programming language. Results indicate that this approach allows the solution of both deductive and recursive queries from XML documents.","PeriodicalId":117236,"journal":{"name":"2012 Ninth International Conference on Information Technology - New Generations","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115249030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The high-level contribution of this paper is the design and development of a unicast routing protocol to effectively minimize the stability-hop count tradeoff observed in mobile ad hoc networks (MANETs) and thereby incur lower end-to-end delay per data packet. The proposed unicast routing protocol, referred to as SILET, uses the predicted link expiration times (LETs) as part of the link weights. SILET is a source-initiated on-demand routing protocol that initiates a global broadcast query-reply cycle to discover routes, the destination chooses the route with the lowest sum of the link weights, the weight assigned to a link is '1' plus the inverse of the LET of the link. The term '1' as part of the link weight minimizes the hop count per path and the term comprising of the inverse of the LET maximizes the lifetime of the routes. Through extensive simulations and comparison with contemporary minimum-hop based and stability-based routing protocols, we demonstrate that SILET discovers long-living stable routes with hop count close to that of the minimum, thus, minimizing the stability-hop count tradeoff. By virtue of incurring lower route discovery control overhead (due to long-living stable routes) and lower hop count per route, the end-to-end delay per data packet is also optimized and has been observed to be the lowest among all the routing protocols simulated in this paper.
{"title":"A Unicast MANET Routing Protocol to Simultaneously Minimize the Stability-Hop Count Tradeoff and End-to-End Delay","authors":"N. Meghanathan","doi":"10.1109/ITNG.2012.17","DOIUrl":"https://doi.org/10.1109/ITNG.2012.17","url":null,"abstract":"The high-level contribution of this paper is the design and development of a unicast routing protocol to effectively minimize the stability-hop count tradeoff observed in mobile ad hoc networks (MANETs) and thereby incur lower end-to-end delay per data packet. The proposed unicast routing protocol, referred to as SILET, uses the predicted link expiration times (LETs) as part of the link weights. SILET is a source-initiated on-demand routing protocol that initiates a global broadcast query-reply cycle to discover routes, the destination chooses the route with the lowest sum of the link weights, the weight assigned to a link is '1' plus the inverse of the LET of the link. The term '1' as part of the link weight minimizes the hop count per path and the term comprising of the inverse of the LET maximizes the lifetime of the routes. Through extensive simulations and comparison with contemporary minimum-hop based and stability-based routing protocols, we demonstrate that SILET discovers long-living stable routes with hop count close to that of the minimum, thus, minimizing the stability-hop count tradeoff. By virtue of incurring lower route discovery control overhead (due to long-living stable routes) and lower hop count per route, the end-to-end delay per data packet is also optimized and has been observed to be the lowest among all the routing protocols simulated in this paper.","PeriodicalId":117236,"journal":{"name":"2012 Ninth International Conference on Information Technology - New Generations","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115926494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose a blind digital audio watermarking method for embedding a binary logo in an audio signal. This method uses the two-dimensional Dyadic Wavelet Transform (DYWT). To apply the two-dimensional DYWT, we construct an image from an audio signal by dividing the original audio signal into several parts and arranging these parts in rows. Since the DYWT has a redundant representation, the amount of information that the watermark must carry is higher than in discrete-wavelet-transform -- based (DWT-based) methods, which are very popular. We describe our embedding and extracting procedures in detail and show experimental results demonstrating that our method gives watermarked signals that have better quality and that are robust against attacks such as clipping and some audio compressions.
{"title":"Visualization of Digital Audio Watermarking Based on the Dyadic Wavelet Transform","authors":"Teruya Minamoto, Yuji Ogata, Masahiro Sawai","doi":"10.1109/ITNG.2012.84","DOIUrl":"https://doi.org/10.1109/ITNG.2012.84","url":null,"abstract":"We propose a blind digital audio watermarking method for embedding a binary logo in an audio signal. This method uses the two-dimensional Dyadic Wavelet Transform (DYWT). To apply the two-dimensional DYWT, we construct an image from an audio signal by dividing the original audio signal into several parts and arranging these parts in rows. Since the DYWT has a redundant representation, the amount of information that the watermark must carry is higher than in discrete-wavelet-transform -- based (DWT-based) methods, which are very popular. We describe our embedding and extracting procedures in detail and show experimental results demonstrating that our method gives watermarked signals that have better quality and that are robust against attacks such as clipping and some audio compressions.","PeriodicalId":117236,"journal":{"name":"2012 Ninth International Conference on Information Technology - New Generations","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132411720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The mutual exclusion (MX) paradigm can be used as a building block in many practical problems such as group communication, atomic commitment and replicated data management where the exclusive use of an object might be useful. The problem has been widely studied in the research community since one reason for this wide interest is that many distributed protocols need a mutual exclusion protocol. However, despite its usefulness, to our knowledge there is no work that has been devoted to this problem in a mobile computing environment. In this paper, we describe a solution to the mutual exclusion problem from mobile computing systems. This solution is based on the token-based mutual exclusion algorithm.
{"title":"A Design of Mutual Exclusion Protocol in Cellular Wireless Networks","authors":"Sunghoon Park, Seoun-Hyung Lee","doi":"10.1109/ITNG.2012.166","DOIUrl":"https://doi.org/10.1109/ITNG.2012.166","url":null,"abstract":"The mutual exclusion (MX) paradigm can be used as a building block in many practical problems such as group communication, atomic commitment and replicated data management where the exclusive use of an object might be useful. The problem has been widely studied in the research community since one reason for this wide interest is that many distributed protocols need a mutual exclusion protocol. However, despite its usefulness, to our knowledge there is no work that has been devoted to this problem in a mobile computing environment. In this paper, we describe a solution to the mutual exclusion problem from mobile computing systems. This solution is based on the token-based mutual exclusion algorithm.","PeriodicalId":117236,"journal":{"name":"2012 Ninth International Conference on Information Technology - New Generations","volume":"447 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131988355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rule-based systems have been studied for nearly two decades in applications such as geographical information systems (GIS) and metadata catalog systems. Recovering large data sets that are not well organized is a challenge that imposes constraints on applications. These constraints include utilizing huge amounts of memory, consuming excessive amounts of time, and the risk of exceeding these resources, thus causing instability. This work examines a novel approach to provide a large unorganized data set by deriving a rule-based system that regulates web page generation thereby improve cache performance and query generation. The trade-offs imposed by rule-based systems in terms of time to deliver content, memory consumption, and fault tolerance are also analyzed.
{"title":"Rule-based Management of Large Unorganized Data Sets","authors":"D. Beatty, N. Lopez-Benitez","doi":"10.1109/ITNG.2012.66","DOIUrl":"https://doi.org/10.1109/ITNG.2012.66","url":null,"abstract":"Rule-based systems have been studied for nearly two decades in applications such as geographical information systems (GIS) and metadata catalog systems. Recovering large data sets that are not well organized is a challenge that imposes constraints on applications. These constraints include utilizing huge amounts of memory, consuming excessive amounts of time, and the risk of exceeding these resources, thus causing instability. This work examines a novel approach to provide a large unorganized data set by deriving a rule-based system that regulates web page generation thereby improve cache performance and query generation. The trade-offs imposed by rule-based systems in terms of time to deliver content, memory consumption, and fault tolerance are also analyzed.","PeriodicalId":117236,"journal":{"name":"2012 Ninth International Conference on Information Technology - New Generations","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128338834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This document describes how to implement a Chat Bot on the Twitter social network for entertainment and viral advertising using a database and a simple algorithm. Having as a main theme a successfully implementation of a Chat Bot preventing people classify it as SPAM, as a result of this a Twitter account (@DonPlaticador) that works without the intervention of a person and every day earns more followers was obtained.
{"title":"Development and Implementation of a Chat Bot in a Social Network","authors":"Salto Martínez Rodrigo, Jacques Abraham","doi":"10.1109/ITNG.2012.147","DOIUrl":"https://doi.org/10.1109/ITNG.2012.147","url":null,"abstract":"This document describes how to implement a Chat Bot on the Twitter social network for entertainment and viral advertising using a database and a simple algorithm. Having as a main theme a successfully implementation of a Chat Bot preventing people classify it as SPAM, as a result of this a Twitter account (@DonPlaticador) that works without the intervention of a person and every day earns more followers was obtained.","PeriodicalId":117236,"journal":{"name":"2012 Ninth International Conference on Information Technology - New Generations","volume":"12 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123727566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Today object-oriented programming (OOP) is becoming more and more popular than ever, due to Internet and network computing, and need for resource sharing. Java becomes attractive because of its appealing features such as platform independence and code reusability. However, Java has lower performance than conventional programming languages due to its real-time execution overheads in the layer of Java Virtual Machine (JVM). With increasing performance through higher clock speed or multi-cores, software virtual machines are still needed to run on top of the operating system to execute Java, reducing the effect of the hardware performance improvements. This research proposes a high-performance computer architecture with hybrid system co-design for Java processing. Our FPGA model implemented in VHDL, jHISC, originates hardware support for object-oriented bytecodes, object referencing and method invocation. Moreover, baseline compiler is developed to construct the core structure and to ensure the architecture compatible to the JVM specifications. The project is at present version 4, which is target for mobile and embedded computing. Comparing with the products by Sun Microsystems through evaluation based on SPEC JVM98 benchmark, jHISC V4.0 provide overall performance gain of around 137% over HotSpot JVM and 102% to 1351% over picoJava II.
{"title":"A Hardware-Software Integrated Design for a High-Performance Java Processor","authors":"A. Fong, C. Yau, Yijun Liu","doi":"10.1109/ITNG.2012.174","DOIUrl":"https://doi.org/10.1109/ITNG.2012.174","url":null,"abstract":"Today object-oriented programming (OOP) is becoming more and more popular than ever, due to Internet and network computing, and need for resource sharing. Java becomes attractive because of its appealing features such as platform independence and code reusability. However, Java has lower performance than conventional programming languages due to its real-time execution overheads in the layer of Java Virtual Machine (JVM). With increasing performance through higher clock speed or multi-cores, software virtual machines are still needed to run on top of the operating system to execute Java, reducing the effect of the hardware performance improvements. This research proposes a high-performance computer architecture with hybrid system co-design for Java processing. Our FPGA model implemented in VHDL, jHISC, originates hardware support for object-oriented bytecodes, object referencing and method invocation. Moreover, baseline compiler is developed to construct the core structure and to ensure the architecture compatible to the JVM specifications. The project is at present version 4, which is target for mobile and embedded computing. Comparing with the products by Sun Microsystems through evaluation based on SPEC JVM98 benchmark, jHISC V4.0 provide overall performance gain of around 137% over HotSpot JVM and 102% to 1351% over picoJava II.","PeriodicalId":117236,"journal":{"name":"2012 Ninth International Conference on Information Technology - New Generations","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128130531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jie Luo, Yilin Zhang, S. Vadlamani, Byeong Kil Lee
Early-stage design exploration requires the detailed simulation which is running applications on a cycle-level microprocessor simulator. Main objectives of simulation-level design exploration include understanding the architectural behaviors of target applications and finding optimal configurations to cover wide range of applications in terms of performance and power. However, full simulation of an industry standard benchmark suite (e.g., SPEC CPU 2006) takes several weeks to months to complete. This problem has motivated several research groups to come up with methodologies to reduce simulation time while maintaining a certain level of accuracy. Among many techniques for reducing simulation time, a tool called Sim Point is popularly used. However, simulation load even with the reduced workloads is still heavy, considering design complexity of modern microprocessors. Basic motivation of this research is started from how design exploration is actually performed. Designers will observe the performance impact from resource variations or configuration changes. If a simulation point shows low sensitivity to resource variations, designers would eliminate those simulation points from the simulation setup procedure. In this paper, we focus on identifying those simulation points which have high sensitivity or low sensitivity, by which overall simulation methodology can be effectively improved. We also performed the performance-sensitivity-based similarity analysis (grouping) among simulation points on specific performance metric which can be an overall performance metric or a component-level metric.
早期的设计探索需要在周期级微处理器模拟器上运行应用程序的详细仿真。仿真级设计探索的主要目标包括理解目标应用程序的体系结构行为，并在性能和功耗方面找到涵盖广泛应用程序的最佳配置。然而，一个行业标准基准套件(例如，SPEC CPU 2006)的完整模拟需要几周到几个月的时间才能完成。这个问题促使几个研究小组提出了一些方法来减少模拟时间，同时保持一定程度的准确性。在许多减少模拟时间的技术中，一种叫做Sim Point的工具被广泛使用。然而，考虑到现代微处理器的设计复杂性，即使减少了工作负载，仿真负载仍然很重。本研究的基本动机是从如何进行设计探索开始的。设计人员将观察资源变化或配置更改对性能的影响。如果一个模拟点对资源变化的敏感性较低，设计人员将从模拟设置程序中删除这些模拟点。本文的重点是识别高灵敏度或低灵敏度的仿真点，从而有效地改进整个仿真方法。我们还对特定性能指标(可以是整体性能指标或组件级指标)的模拟点进行了基于性能敏感性的相似性分析(分组)。
{"title":"Performance-Sensitivity-based Workload Tailoring for Effective Design Exploration","authors":"Jie Luo, Yilin Zhang, S. Vadlamani, Byeong Kil Lee","doi":"10.1109/ITNG.2012.112","DOIUrl":"https://doi.org/10.1109/ITNG.2012.112","url":null,"abstract":"Early-stage design exploration requires the detailed simulation which is running applications on a cycle-level microprocessor simulator. Main objectives of simulation-level design exploration include understanding the architectural behaviors of target applications and finding optimal configurations to cover wide range of applications in terms of performance and power. However, full simulation of an industry standard benchmark suite (e.g., SPEC CPU 2006) takes several weeks to months to complete. This problem has motivated several research groups to come up with methodologies to reduce simulation time while maintaining a certain level of accuracy. Among many techniques for reducing simulation time, a tool called Sim Point is popularly used. However, simulation load even with the reduced workloads is still heavy, considering design complexity of modern microprocessors. Basic motivation of this research is started from how design exploration is actually performed. Designers will observe the performance impact from resource variations or configuration changes. If a simulation point shows low sensitivity to resource variations, designers would eliminate those simulation points from the simulation setup procedure. In this paper, we focus on identifying those simulation points which have high sensitivity or low sensitivity, by which overall simulation methodology can be effectively improved. We also performed the performance-sensitivity-based similarity analysis (grouping) among simulation points on specific performance metric which can be an overall performance metric or a component-level metric.","PeriodicalId":117236,"journal":{"name":"2012 Ninth International Conference on Information Technology - New Generations","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121625560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A golden rule that must be followed when building any larger system, is to manage complexity. Without complexity management a system can only grow to a certain point before it collapses under its own complexity. One complexity management technique is the use of design patterns, which are architectural constructs that have proven their usefulness in handling certain design problems. This paper will describe Generator Flow, a design pattern used in No GAP an EDA tool developed at the department of EE, Linköping University. Generator Flow is a design pattern aimed at handling a succession of transformations performed on a number of data sets to reach some useful outputs. This paper also describes the XML based flow-configuration file, which is used to allow for runtime configuration of the transformation flow used in No GAP. No GAP is an EDA tool aimed at easing the design and verification of ASIP and programmable hardware accelerators. A problem faced when developing No GAP was how to handle the flow of transformations, from an input specification to useful outputs. It was in this context that the Generator Flow pattern was developed.
{"title":"Generator Flow: An XML Configurable Design Pattern Used in NoGAP","authors":"Per Karlström, Wenbiao Zhou","doi":"10.1109/ITNG.2012.48","DOIUrl":"https://doi.org/10.1109/ITNG.2012.48","url":null,"abstract":"A golden rule that must be followed when building any larger system, is to manage complexity. Without complexity management a system can only grow to a certain point before it collapses under its own complexity. One complexity management technique is the use of design patterns, which are architectural constructs that have proven their usefulness in handling certain design problems. This paper will describe Generator Flow, a design pattern used in No GAP an EDA tool developed at the department of EE, Linköping University. Generator Flow is a design pattern aimed at handling a succession of transformations performed on a number of data sets to reach some useful outputs. This paper also describes the XML based flow-configuration file, which is used to allow for runtime configuration of the transformation flow used in No GAP. No GAP is an EDA tool aimed at easing the design and verification of ASIP and programmable hardware accelerators. A problem faced when developing No GAP was how to handle the flow of transformations, from an input specification to useful outputs. It was in this context that the Generator Flow pattern was developed.","PeriodicalId":117236,"journal":{"name":"2012 Ninth International Conference on Information Technology - New Generations","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114886294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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