ETRI Journal最新文献

SoCs with analog-circuit-based unsigned weight-accumulating spiking neural networks (UWA-SNNs) are a highly promising solution for achieving low-power AI-SoCs. This paper addresses the challenges that must be overcome to realize the potential of UWA-SNNs in low-power AI-SoCs: (i) the absence of UWA-SNN learning methods and the lack of an environment for developing applications based on trained SNN models and (ii) the inherent issue of testing and validating applications on the system being nearly impractical until the final chip is fabricated owing to the mixed-signal circuit implementation of UWA-SNN-based SoCs. This paper argues that, by integrating the proposed solutions, the development of an EDA tool that enables the easy and rapid development of UWA-SNN-based SoCs is feasible, and demonstrates this through the development of the SNN eXpress (SNX) tool. The developed SNX automates the generation of RTL code, FPGA prototypes, and a software development kit tailored for UWA-SNN-based application development. Comprehensive details of SNX development and the performance evaluation and verification results of two AI-SoCs developed using SNX are also presented.

Owing to the widespread advancement of transformer-based artificial neural networks, artificial intelligence (AI) processors are now required to perform matrix–vector multiplication in addition to the conventional matrix–matrix multiplication. However, current AI processor architectures are optimized for general matrix–matrix multiplications (GEMMs), which causes significant throughput degradation when processing general matrix–vector multiplications (GEMVs). In this study, we proposed a port-folding GEMV (PF-GEMV) scheme employing multiformat and low-precision techniques while reusing an outer product-based processor optimized for conventional GEMM operations. This approach achieves 93.7% utilization in GEMV operations with an 8-bit format on an 8 $�\times$ 8 processor, thus resulting in a 7.5 $�\times$ increase in throughput compared with that of the original scheme. Furthermore, when applied to the matrix operation of the GPT-2 large model, an increase in speed by 7 $�\times$ is achieved in single-batch inferences.

Entanglement is crucial for achieving quantum advantages. However, in the context of quantum machine learning, existing optimization strategies for generating quantum classifier circuits often result in unentangled circuits, indicating an underutilization of the entanglement effect needed to learn complex patterns. In this study, we proposed a novel metaheuristic approach—genetic algorithm—for designing a quantum kernel classifier that incorporates expressive entanglement. This classifier utilizes a loopless entanglement-directed graph, where each directed edge represents the entanglement between the target and control qubits. The proposed method consistently outperforms classical and quantum baselines across various artificial and actual datasets, achieving improvements up to 32.4% and 17.5%, respectively, compared with the best model among all other baselines. Moreover, this method successfully reconstructs the hidden entanglement structures underlying artificial datasets. The results also demonstrate that the optimized circuits exhibit diverse entanglement variations across different datasets, indicating the versatility of the proposed approach.

Anomaly detection in video surveillance is crucial but challenging due to the rarity of irregular events and ambiguity of defining anomalies. We propose a method called AONet that utilizes a spatiotemporal module to extract spatiotemporal features efficiently, as well as a residual autoencoder equipped with an attention network for effective future frame prediction in video anomaly detection. AONet utilizes a novel activation function called OptAF that combines the strengths of the ReLU, leaky ReLU, and sigmoid functions. Furthermore, the proposed method employs a combination of robust loss functions to address various aspects of prediction errors and enhance training effectiveness. The performance of the proposed method is evaluated on three widely used benchmark datasets. The results indicate that the proposed method outperforms existing state-of-the-art methods and demonstrates comparable performance, achieving area under the curve values of 97.0%, 86.9%, and 73.8% on the UCSD Ped2, CUHK Avenue, and ShanghaiTech Campus datasets, respectively. Additionally, the high speed of the proposed method enables its application to real-time tasks.

Deep learning (DL) has significantly advanced artificial intelligence (AI); however, frameworks such as PyTorch, ONNX, and TensorFlow are optimized for general-purpose GPUs, leading to inefficiencies on specialized accelerators such as neural processing units (NPUs) and processing-in-memory (PIM) devices. These accelerators are designed to optimize both throughput and energy efficiency but they require more tailored optimizations. To address these limitations, we propose the NEST compiler (NEST-C), a novel DL framework that improves the deployment and performance of models across various AI accelerators. NEST-C leverages profiling-based quantization, dynamic graph partitioning, and multi-level intermediate representation (IR) integration for efficient execution on diverse hardware platforms. Our results show that NEST-C significantly enhances computational efficiency and adaptability across various AI accelerators, achieving higher throughput, lower latency, improved resource utilization, and greater model portability. These benefits contribute to more efficient DL model deployment in modern AI applications.

In this study, we report a transmitter system for free-space quantum key distribution (QKD) using the BB84 protocol, which does not require an internal alignment process, by using a wavelength-division multiplexing (WDM) filter and polarization-encoding module. With a custom-made WDM filter, the signals required for QKD can be integrated by simply connecting fibers, thus avoiding the laborious internal alignment required for free-space QKD systems using conventional bulk-optic setups. The WDM filter is designed to multiplex the single-mode signals from 785-nm quantum and 1550-nm synchronization channels for spatial-mode matching while maintaining the polarization relations. The measured insertion loss and isolation are 1.8 dB and 32.6 dB for 785 nm and 0.7 dB and 28.3 dB for 1550 nm, respectively. We also evaluate the QKD performance of the proposed system. The sifted key rate and quantum bit error rate are 1.6 Mbps and 0.62%, respectively, at an operating speed of 100 MHz, rendering our system comparable to conventional systems using bulk-optic devices for channel integration.

Lithium niobate on insulator (LNOI) is a promising material platform for applications in integrated quantum photonics. A low optical loss is crucial for preserving fragile quantum states. Therefore, in this study, we have fabricated LNOI rib waveguides with a low optical propagation loss of 0.16 dB/cm by optimizing the etching conditions for various parameters. The symmetry and smoothness of the waveguides on $�x$-cut LNOI are improved by employing a shallow etching process. The proposed method is expected to facilitate the development of on-chip quantum photonic devices based on LNOI.

Fault-tolerant quantum computation requires error-correcting codes that enable reliable universal quantum operations. This study introduces a novel approach that executes the logical Hadamard with low-space requirements while preserving the original definition of logical operators within the framework of the rotated surface codes. Our method leverages a boundary deformation method to rotate the logical qubit transformed by transversal Hadamard. Following this, the original encoding of the logical qubit is reinstated through logical flip-and-shift operations. The estimated space–time cost for a logical Hadamard operation with a code distance d is 5d² + 3d². The efficiency enhancement of the proposed method is approximately four times greater than those of previous approaches, regardless of the code distance. Unlike the traditional method, implementing a logical Hadamard requires only two patches instead of seven. Furthermore, the proposed method ensures the parallelism of quantum circuits by preventing interferences between adjacent logical data qubits.

To expand the scale of spiking neural networks (SNNs), an interface circuit that supports multiple SNN cores is essential. This circuit should be designed using an asynchronous approach to leverage characteristics of SNNs similar to those of the human brain. However, the absence of a global clock presents timing issues during implementation. Hence, we propose an intermediate latching template to establish asynchronous nonlinear connectivity with multipipeline processing between multiple SNN cores. We design arbitration and distribution blocks in the interface circuit based on the proposed template and fabricate an interface circuit that supports four SNN cores using a full-custom approach in a 28-nm CMOS (complementary metal–oxide–semiconductor) FDSOI (fully depleted silicon on insulator) process. The proposed template can enhance throughput in the interface circuit by up to 53% compared with the conventional asynchronous template. The interface circuit transmits spikes while consuming 1.7 and 3.7 pJ of power, supporting 606 and 59 Mevent/s in intrachip and interchip communications, respectively.