A new algorithm is given for computing trigonometric functions using the logarithmic number system (LNS). Based on the laws of sines and cosines, the algorithm uses novel addressing of ROMs with the middle-order bits of the LNS representation. Error analysis and simulation show the algorithm is accurate to 22 bits when intermediate steps are performed with 23-bit precision LNS. A VLIW software implementation having throughput of one trigonometric result every 17 cycles is suggested that uses special instructions to access small ROMs containing logarithmic sines and cosines. Also, the proposed algorithm can be implemented fully in hardware having throughput of one trigonometric result every one or two cycles using minor low-cost modifications to an existing LNS ALU design.
{"title":"Approximating trigonometric functions with the laws of sines and cosines using the logarithmic number system","authors":"M. Arnold","doi":"10.1109/DSD.2005.18","DOIUrl":"https://doi.org/10.1109/DSD.2005.18","url":null,"abstract":"A new algorithm is given for computing trigonometric functions using the logarithmic number system (LNS). Based on the laws of sines and cosines, the algorithm uses novel addressing of ROMs with the middle-order bits of the LNS representation. Error analysis and simulation show the algorithm is accurate to 22 bits when intermediate steps are performed with 23-bit precision LNS. A VLIW software implementation having throughput of one trigonometric result every 17 cycles is suggested that uses special instructions to access small ROMs containing logarithmic sines and cosines. Also, the proposed algorithm can be implemented fully in hardware having throughput of one trigonometric result every one or two cycles using minor low-cost modifications to an existing LNS ALU design.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123888941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Virk, J. Madsen, Andreas Vad Lorentzen, Martin Leopold, Philippe Bonnet
Wireless integrated sensor networks are a new class of embedded computer systems which have been made possible mainly by the recent advances in the micro and the nano technology. In order to efficiently utilize the limited resources available on a sensor node, we need to optimize its key design parameters which is only possible by making system-level design decisions about its hardware and software (operating system and applications) architecture. In this paper, we present the design of a sensor node development platform in relation to an application of wireless integrated sensor networks for sow monitoring. We also discuss the related hardware/software codesign tradeoffs.
{"title":"Design of a development platform for HW/SW codesign of wireless integrated sensor nodes","authors":"K. Virk, J. Madsen, Andreas Vad Lorentzen, Martin Leopold, Philippe Bonnet","doi":"10.1109/DSD.2005.32","DOIUrl":"https://doi.org/10.1109/DSD.2005.32","url":null,"abstract":"Wireless integrated sensor networks are a new class of embedded computer systems which have been made possible mainly by the recent advances in the micro and the nano technology. In order to efficiently utilize the limited resources available on a sensor node, we need to optimize its key design parameters which is only possible by making system-level design decisions about its hardware and software (operating system and applications) architecture. In this paper, we present the design of a sensor node development platform in relation to an application of wireless integrated sensor networks for sow monitoring. We also discuss the related hardware/software codesign tradeoffs.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"253 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121171085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Agostini, R. Porto, S. Bampi, Ivan Saraiva Silva
This paper presents the design and implementation of a multiplierless JPEG compressor for gray scale images. The modules of this architecture were fully pipelined and targeted to FPGA device implementation. The designed architectures are detailed in this paper and they were described in VHDL, simulated and physically mapped to Altera Flex10KE FPGAs. The JPEG compressor pipeline has a minimum latency of 238 clock cycles, given the full modular pipeline depth. The minimum compressor period is 26.6ns and the compressor is able to process 37.6 millions of pixels per second. For example, the compressor can process a 640x480 pixels still image in 8.2 ms, reaching a maximum processing rate of 122.4 frames per second.
{"title":"A FPGA based design of a multiplierless and fully pipelined JPEG compressor","authors":"L. Agostini, R. Porto, S. Bampi, Ivan Saraiva Silva","doi":"10.1109/DSD.2005.6","DOIUrl":"https://doi.org/10.1109/DSD.2005.6","url":null,"abstract":"This paper presents the design and implementation of a multiplierless JPEG compressor for gray scale images. The modules of this architecture were fully pipelined and targeted to FPGA device implementation. The designed architectures are detailed in this paper and they were described in VHDL, simulated and physically mapped to Altera Flex10KE FPGAs. The JPEG compressor pipeline has a minimum latency of 238 clock cycles, given the full modular pipeline depth. The minimum compressor period is 26.6ns and the compressor is able to process 37.6 millions of pixels per second. For example, the compressor can process a 640x480 pixels still image in 8.2 ms, reaching a maximum processing rate of 122.4 frames per second.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125962411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hamid Safizadeh, Hamid Noori, M. Sedighi, A. Jahanian, Neda Zolfaghari
The recent growth of cellular phone systems, voice over IP devices, and other multimedia applications has created a considerable need for efficient voice coding algorithms. These algorithms usually require intensive amount of signal processing capabilities and demand significant signal processing power. The current market trend of integrating multiple voice channels into a single die has further intensified the need for more powerful hardware platforms. Some new design ideas such as vocoder-specialized DSP architectures, combined RISC/DSP platforms, and adding hardware accelerators or coprocessors to the general-purpose processors have been proposed. In this paper, a new hardware accelerator design has been proposed which executes macro instructions (MIs). The proposed coprocessor can be added to each processor type that can support at least one coprocessor without modifying the compiler and redesigning the processor. It can handle computationally intensive loops in speech coding algorithms parallel with the main processor. The coprocessor along with software optimization reduces clock cycles required for G.723.1 by 80% and G.729 by 64% while MIPS R3000 RISC is used as the host.
{"title":"Efficient host-independent coprocessor architecture for speech coding algorithms","authors":"Hamid Safizadeh, Hamid Noori, M. Sedighi, A. Jahanian, Neda Zolfaghari","doi":"10.1109/DSD.2005.37","DOIUrl":"https://doi.org/10.1109/DSD.2005.37","url":null,"abstract":"The recent growth of cellular phone systems, voice over IP devices, and other multimedia applications has created a considerable need for efficient voice coding algorithms. These algorithms usually require intensive amount of signal processing capabilities and demand significant signal processing power. The current market trend of integrating multiple voice channels into a single die has further intensified the need for more powerful hardware platforms. Some new design ideas such as vocoder-specialized DSP architectures, combined RISC/DSP platforms, and adding hardware accelerators or coprocessors to the general-purpose processors have been proposed. In this paper, a new hardware accelerator design has been proposed which executes macro instructions (MIs). The proposed coprocessor can be added to each processor type that can support at least one coprocessor without modifying the compiler and redesigning the processor. It can handle computationally intensive loops in speech coding algorithms parallel with the main processor. The coprocessor along with software optimization reduces clock cycles required for G.723.1 by 80% and G.729 by 64% while MIPS R3000 RISC is used as the host.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132653254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For running subsequent configurations in a reconfigurable computing system intermediate data must transfer between them. Reducing memory usage overhead can result in reduction in the array size and the number of input/output pins. In this paper, a new iterative design flow is proposed which integrates the synthesis and physical design aspects for performing a static compilation process. A new temporal partitioning algorithm for partitioning and scheduling is proposed, which tries to increase similarity of subsequent configurations in such a way that the reconfiguration time on a partially reconfigurable hardware decreases. In addition, we perform an iterative physical design process based on similar configurations produced in the previous stage. A modified algorithm improves our prior temporal partitioning algorithm, which usually had large overhead of memory usage and the number of input/output pins. This new approach performs partitioning in depth and tries to minimize the memory and 10 requirements.
{"title":"Reducing inter-configuration memory usage and performance improvement in reconfigurable computing systems","authors":"Farhad Mehdipour, M. S. Zamani, M. Sedighi","doi":"10.1109/DSD.2005.67","DOIUrl":"https://doi.org/10.1109/DSD.2005.67","url":null,"abstract":"For running subsequent configurations in a reconfigurable computing system intermediate data must transfer between them. Reducing memory usage overhead can result in reduction in the array size and the number of input/output pins. In this paper, a new iterative design flow is proposed which integrates the synthesis and physical design aspects for performing a static compilation process. A new temporal partitioning algorithm for partitioning and scheduling is proposed, which tries to increase similarity of subsequent configurations in such a way that the reconfiguration time on a partially reconfigurable hardware decreases. In addition, we perform an iterative physical design process based on similar configurations produced in the previous stage. A modified algorithm improves our prior temporal partitioning algorithm, which usually had large overhead of memory usage and the number of input/output pins. This new approach performs partitioning in depth and tries to minimize the memory and 10 requirements.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130520375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ghaffari Fakhreddine, M. Auguin, M. Abid, M. Benjemaa
We present a new HW/SW partitioning approach. This partitioning method is called an online partitioning algorithm (O.P.A) which consists to adapt dynamically the architecture to the processing requirements. A scheduling heuristic is associated to this partitioning approach. We compare our method with an off-line static HW/SW partitioning approach.
{"title":"An adaptive on-line HW/SW partitioning for soft real time reconfigurable systems","authors":"Ghaffari Fakhreddine, M. Auguin, M. Abid, M. Benjemaa","doi":"10.1109/DSD.2005.12","DOIUrl":"https://doi.org/10.1109/DSD.2005.12","url":null,"abstract":"We present a new HW/SW partitioning approach. This partitioning method is called an online partitioning algorithm (O.P.A) which consists to adapt dynamically the architecture to the processing requirements. A scheduling heuristic is associated to this partitioning approach. We compare our method with an off-line static HW/SW partitioning approach.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133946337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper presents a software tool that demonstrates principles of RAM memory testing and of the memory BIST structure. The MemBIST software tool automatically generates built-in self-test blocks for a given memory matrix as a VHDL model of the whole system. As a complement to the BIST structure generator, a module for visualisation of selected RAM memory fault models, March C-test algorithm as well as a memory self-testing architecture principle is a part of the tool. The developed system was implemented as a Java applet what means its good compatibility regarding different hardware and operating system platforms, its safety and accessibility while it is placed on Internet. The presented MemBIST applet is useful as an educational tool and a training tool in built-in self-testing for RAM memories.
{"title":"MemBIST applet for learning principles of memory testing and generating memory BIST","authors":"M. Fischerová, M. Simlastík","doi":"10.1109/DSD.2005.56","DOIUrl":"https://doi.org/10.1109/DSD.2005.56","url":null,"abstract":"The paper presents a software tool that demonstrates principles of RAM memory testing and of the memory BIST structure. The MemBIST software tool automatically generates built-in self-test blocks for a given memory matrix as a VHDL model of the whole system. As a complement to the BIST structure generator, a module for visualisation of selected RAM memory fault models, March C-test algorithm as well as a memory self-testing architecture principle is a part of the tool. The developed system was implemented as a Java applet what means its good compatibility regarding different hardware and operating system platforms, its safety and accessibility while it is placed on Internet. The presented MemBIST applet is useful as an educational tool and a training tool in built-in self-testing for RAM memories.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115486400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Ghiassi, M. M. Rad, M. Nikjoo, A. H. Mohseni, B. Khalaj
A sensor network with mobile agents (SENMA) is an architecture proposed for large scale sensor networks in which the access point moves above the network and gathers information from a limited number of nodes. However, the performance of such system is limited by estimation errors and packet errors due to collision. In this paper, we first derive the equations of distortion in a general scenario and use this model to obtain four best node positions in order to achieve min-max estimation error in a square. In addition, an opportunistic MAC is proposed that considers both collision effects and estimation error based on channel state information (CSI). As the simulation results show the proposed scheme achieves an optimum estimation with minimum collision and energy consumption.
{"title":"An efficient MAC protocol for sensor network considering energy consumption and information retrieval pattern","authors":"Y. Ghiassi, M. M. Rad, M. Nikjoo, A. H. Mohseni, B. Khalaj","doi":"10.1109/DSD.2005.17","DOIUrl":"https://doi.org/10.1109/DSD.2005.17","url":null,"abstract":"A sensor network with mobile agents (SENMA) is an architecture proposed for large scale sensor networks in which the access point moves above the network and gathers information from a limited number of nodes. However, the performance of such system is limited by estimation errors and packet errors due to collision. In this paper, we first derive the equations of distortion in a general scenario and use this model to obtain four best node positions in order to achieve min-max estimation error in a square. In addition, an opportunistic MAC is proposed that considers both collision effects and estimation error based on channel state information (CSI). As the simulation results show the proposed scheme achieves an optimum estimation with minimum collision and energy consumption.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116154888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Real-time image processing is a computational intensive task with applications in various engineering fields. In several image processing applications, a significant amount of computing power is committed to image enhancement operations, basic segmentation and identification of regions of interest for further analysis. Such type of front-end processing can be done efficiently by custom data-flow processors closely coupled to an image sensor. This paper proposes a visual design environment to support the high-level design of custom data-flow processors for real-time image analysis applications. The tool is embedded in Matlab/Simulink, and the system modeling is done using a library of blocks that implement common low-level image processing operations. Functional validation is performed efficiently by the simulation engine of Simulink in a frame by frame basis, using the functions provided by the image processing toolbox in Matlab. The automatic generation of a synthesizable RTL model guarantees a logic implementation of the system that complies to the high-level model validated, under constraints imposed by the user and the target reconfigurable device.
{"title":"A high-level tool for the design of custom image processing systems","authors":"Sérgio Martins, J. Alves","doi":"10.1109/DSD.2005.7","DOIUrl":"https://doi.org/10.1109/DSD.2005.7","url":null,"abstract":"Real-time image processing is a computational intensive task with applications in various engineering fields. In several image processing applications, a significant amount of computing power is committed to image enhancement operations, basic segmentation and identification of regions of interest for further analysis. Such type of front-end processing can be done efficiently by custom data-flow processors closely coupled to an image sensor. This paper proposes a visual design environment to support the high-level design of custom data-flow processors for real-time image analysis applications. The tool is embedded in Matlab/Simulink, and the system modeling is done using a library of blocks that implement common low-level image processing operations. Functional validation is performed efficiently by the simulation engine of Simulink in a frame by frame basis, using the functions provided by the image processing toolbox in Matlab. The automatic generation of a synthesizable RTL model guarantees a logic implementation of the system that complies to the high-level model validated, under constraints imposed by the user and the target reconfigurable device.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126962899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The hardware-software platform for design, simulation and learning via Internet network was realized with use the modern facilities Internet technologies (the server Apache, programming languages PERL/PHP).
{"title":"Internet-based IC technology design and simulation","authors":"V. Nelayev, V. Stempitsky, Kirill A. Kudin","doi":"10.1109/DSD.2005.52","DOIUrl":"https://doi.org/10.1109/DSD.2005.52","url":null,"abstract":"The hardware-software platform for design, simulation and learning via Internet network was realized with use the modern facilities Internet technologies (the server Apache, programming languages PERL/PHP).","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"349 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133978200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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