This paper presents a novel method to generate optimized architecture of hardware processes implemented on "system on a programmable chip" (SoPC). The hardware processes are the applications tailored "cells" in the processor-coupled polymorphous fabric (Ch. Wolinski et al., 2003, Ch. Wolinski et al., 2002) implemented on the reconfigurable SoPC platform. In order to obtain optimized high performance pipelined architecture each process implementing repetitive conditional behavior with possible inter-iteration dependencies is scheduled under hardware resource constraints using "fabric cell synthesis tool" (FAST). The scheduling problem is defined and solved using constraints programming approach. This approach makes it possible to obtain optimal solutions in terms of execution time and number of registers for a number of real cases. Our method is illustrated using a simple example and a part of the "CORDIC" application (S.F. Hsiao et al., 1991). The final design is implemented on a reconfigurable platform that shows feasibility of our approach. Optimal schedules are achieved for both discussed applications.
本文提出了一种在可编程芯片上实现的硬件进程优化体系结构生成的新方法。硬件进程是在可重构SoPC平台上实现的处理器耦合多态结构(Ch. Wolinski et al.， 2003, Ch. Wolinski et al.， 2002)中定制的应用程序“单元”。为了获得优化的高性能流水线架构，在硬件资源约束下，使用“fabric cell synthesis tool”(FAST)对每个实现重复条件行为且可能存在迭代依赖的进程进行调度。用约束规划的方法定义和解决了调度问题。这种方法可以在许多实际情况下获得执行时间和寄存器数量方面的最佳解决方案。我们的方法是用一个简单的例子和“CORDIC”应用程序的一部分来说明的(S.F. Hsiao et al.， 1991)。最后的设计在一个可重构的平台上实现，证明了我们方法的可行性。这两个应用程序都实现了最优调度。
{"title":"A constraints programming approach for fabric cell synthesis","authors":"C. Wolinski, K. Kuchcinski","doi":"10.1109/DSD.2005.5","DOIUrl":"https://doi.org/10.1109/DSD.2005.5","url":null,"abstract":"This paper presents a novel method to generate optimized architecture of hardware processes implemented on \"system on a programmable chip\" (SoPC). The hardware processes are the applications tailored \"cells\" in the processor-coupled polymorphous fabric (Ch. Wolinski et al., 2003, Ch. Wolinski et al., 2002) implemented on the reconfigurable SoPC platform. In order to obtain optimized high performance pipelined architecture each process implementing repetitive conditional behavior with possible inter-iteration dependencies is scheduled under hardware resource constraints using \"fabric cell synthesis tool\" (FAST). The scheduling problem is defined and solved using constraints programming approach. This approach makes it possible to obtain optimal solutions in terms of execution time and number of registers for a number of real cases. Our method is illustrated using a simple example and a part of the \"CORDIC\" application (S.F. Hsiao et al., 1991). The final design is implemented on a reconfigurable platform that shows feasibility of our approach. Optimal schedules are achieved for both discussed applications.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131119120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a massively parallel architecture for hardware implementation of genetic algorithms. This is design is quite innovative as it provides a viable solution to the fitness computation problem, which depends heavily on the problem-specific knowledge. The proposed architecture is completely independent of such specifics. It implements the fitness computation using a neural network. The hardware implementation of the used neural network is stochastic and thus minimise the required hardware area without much increase in response time. Finally, we compare the proposed hardware and existing ones.
{"title":"Massively parallel hardware architecture for genetic algorithms","authors":"N. Nedjah, L. M. Mourelle","doi":"10.1109/DSD.2005.55","DOIUrl":"https://doi.org/10.1109/DSD.2005.55","url":null,"abstract":"In this paper, we propose a massively parallel architecture for hardware implementation of genetic algorithms. This is design is quite innovative as it provides a viable solution to the fitness computation problem, which depends heavily on the problem-specific knowledge. The proposed architecture is completely independent of such specifics. It implements the fitness computation using a neural network. The hardware implementation of the used neural network is stochastic and thus minimise the required hardware area without much increase in response time. Finally, we compare the proposed hardware and existing ones.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121941721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Miguel Pereira, E. Soto, J. Rodríguez-Andina, F. González-Castaño
High-speed telecommunications routers are very important systems in today's networked environments. The purpose of this paper is to propose a mathematical model of the faulty behaviour of such systems and, derived from it, a scheme for the detection of errors occurring concurrently with their normal operation. Although the ultimate goal is to obtain a fault-tolerant router, this work concentrates on the scheduler part of the system and, in particular, in the case of virtual output-queued (VOQ) switches. As starting point, in this paper a balanced traffic load is assumed. The faulty behaviour of complex digital processing systems is usually better described at the algorithmic level, particularly when the operation of the system relies on complex mathematical principles. Therefore, the issues related to concurrent error detection are addressed from the developed mathematical model. Results are presented that point to the ability of the proposed solution to detect errors at a high abstraction level. They have been obtained by injecting faults in the algorithm flow rather than in the hardware itself.
{"title":"High-level modelling and detection of the faulty behaviour of VOQ switches under balanced traffic","authors":"Miguel Pereira, E. Soto, J. Rodríguez-Andina, F. González-Castaño","doi":"10.1109/DSD.2005.46","DOIUrl":"https://doi.org/10.1109/DSD.2005.46","url":null,"abstract":"High-speed telecommunications routers are very important systems in today's networked environments. The purpose of this paper is to propose a mathematical model of the faulty behaviour of such systems and, derived from it, a scheme for the detection of errors occurring concurrently with their normal operation. Although the ultimate goal is to obtain a fault-tolerant router, this work concentrates on the scheduler part of the system and, in particular, in the case of virtual output-queued (VOQ) switches. As starting point, in this paper a balanced traffic load is assumed. The faulty behaviour of complex digital processing systems is usually better described at the algorithmic level, particularly when the operation of the system relies on complex mathematical principles. Therefore, the issues related to concurrent error detection are addressed from the developed mathematical model. Results are presented that point to the ability of the proposed solution to detect errors at a high abstraction level. They have been obtained by injecting faults in the algorithm flow rather than in the hardware itself.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124068289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Despite recent advances in the microelectronics technology, the implementation of high-throughput decoders for LDPC codes remains a challenging task. This paper aims at summarising the top-down design flow of a decoder for a structured LDPC code compliant with the WWiSE proposal for WLAN. Starting from the system performance analysis with finite-precision arithmetic, a high-throughput architecture is presented as an enhancement of the state-of-the-art solutions, and its VLSI design detailed. The envisaged architecture is also very flexible as it supports several code rates with no significant hardware overhead. The overall decoder, synthesised on 0.18/spl mu/m standard cells CMOS technology, showed remarkable performances: small implementation loss (0.2dB down to BER=10/sup -8/), low latency (less than 6.0/spl mu/s), high useful throughput (up to 940 Mbps) and low complexity (about 375 Kgates).
{"title":"VLSI design of a high-throughput multi-rate decoder for structured LDPC codes","authors":"M. Rovini, N. L'Insalata, F. Rossi, L. Fanucci","doi":"10.1109/DSD.2005.77","DOIUrl":"https://doi.org/10.1109/DSD.2005.77","url":null,"abstract":"Despite recent advances in the microelectronics technology, the implementation of high-throughput decoders for LDPC codes remains a challenging task. This paper aims at summarising the top-down design flow of a decoder for a structured LDPC code compliant with the WWiSE proposal for WLAN. Starting from the system performance analysis with finite-precision arithmetic, a high-throughput architecture is presented as an enhancement of the state-of-the-art solutions, and its VLSI design detailed. The envisaged architecture is also very flexible as it supports several code rates with no significant hardware overhead. The overall decoder, synthesised on 0.18/spl mu/m standard cells CMOS technology, showed remarkable performances: small implementation loss (0.2dB down to BER=10/sup -8/), low latency (less than 6.0/spl mu/s), high useful throughput (up to 940 Mbps) and low complexity (about 375 Kgates).","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129706826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper offers high-performance technology for processing Boolean equations, based on compiler synchronized parallel-processor network-based logic device PRUS (programmable unlimited systems) - single-bit spherical multiprocessor, implemented into ASIC. This technology allows to perform parallel, sequential and pipelined Boolean equations processing using AND, OR, NOT, XOR operations. Multiprocessor is very efficient in hardware implementation - e.g. 256MB RAM is enough for processing Boolean equations containing 20 millions gates.
{"title":"PRUS - processor network for digital circuit implementation","authors":"Stanley Hyduke, V. Hahanov, V. Obrizan, O. Guz","doi":"10.1109/DSD.2005.65","DOIUrl":"https://doi.org/10.1109/DSD.2005.65","url":null,"abstract":"This paper offers high-performance technology for processing Boolean equations, based on compiler synchronized parallel-processor network-based logic device PRUS (programmable unlimited systems) - single-bit spherical multiprocessor, implemented into ASIC. This technology allows to perform parallel, sequential and pipelined Boolean equations processing using AND, OR, NOT, XOR operations. Multiprocessor is very efficient in hardware implementation - e.g. 256MB RAM is enough for processing Boolean equations containing 20 millions gates.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131538729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wireless ad-hoc networks are gaining interest for medical, sensing, wearable computing and other applications. The industry is at a critical juncture now where the maturity of RF CMOS can enable these networks. All of these applications, if deployed successfully, results in the proliferation of wireless devices like we have never seen before. The end result is that these devices need to be very low cost, which fits in well with the CMOS paradigm. The challenge going forward is how to make CMOS RF circuits that consume ultra-low power in a compact form factor.
{"title":"RF CMOS circuits for ad-hoc networks and wearable computing","authors":"C. Siu, S. Kasnavi, K. Iniewski, F. Nabki","doi":"10.1109/DSD.2005.69","DOIUrl":"https://doi.org/10.1109/DSD.2005.69","url":null,"abstract":"Wireless ad-hoc networks are gaining interest for medical, sensing, wearable computing and other applications. The industry is at a critical juncture now where the maturity of RF CMOS can enable these networks. All of these applications, if deployed successfully, results in the proliferation of wireless devices like we have never seen before. The end result is that these devices need to be very low cost, which fits in well with the CMOS paradigm. The challenge going forward is how to make CMOS RF circuits that consume ultra-low power in a compact form factor.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128473482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Joachim Sudbrock, J. Raik, R. Ubar, W. Kuzmicz, W. Pleskacz
This work shows a new concept to extend the hierarchical approach of standard-cell circuit design into the area of defect-oriented test pattern generation. For this purpose test patterns to detect shorts for each standard-cell are created separately. A new defect-oriented test generator (DOT) is using these single cell test pattern lists to create test patterns for the complete circuit. Additionally, test patterns for the routing network will be created. This work targets mainly shorts, but also other defects can be treated in a similar way. In order to generate tests only for relevant combinations of shorted nodes, the critical area for both the cells and the routing network is determined separately and the probability for each short is computed. Shorts inside the routing network can show sequential behaviour. The proposed test pattern generator is also able to find tests for such kind of defects. As the effort to test sequential defects can vary from short to short, a new testability analysis is presented. Based on this analysis a redesign of the circuit layout is proposed. This "layout for testability" approach is therefore a defect oriented equivalent for "design for testability" methods.
{"title":"Defect-oriented test- and layout-generation for standard-cell ASIC designs","authors":"Joachim Sudbrock, J. Raik, R. Ubar, W. Kuzmicz, W. Pleskacz","doi":"10.1109/DSD.2005.30","DOIUrl":"https://doi.org/10.1109/DSD.2005.30","url":null,"abstract":"This work shows a new concept to extend the hierarchical approach of standard-cell circuit design into the area of defect-oriented test pattern generation. For this purpose test patterns to detect shorts for each standard-cell are created separately. A new defect-oriented test generator (DOT) is using these single cell test pattern lists to create test patterns for the complete circuit. Additionally, test patterns for the routing network will be created. This work targets mainly shorts, but also other defects can be treated in a similar way. In order to generate tests only for relevant combinations of shorted nodes, the critical area for both the cells and the routing network is determined separately and the probability for each short is computed. Shorts inside the routing network can show sequential behaviour. The proposed test pattern generator is also able to find tests for such kind of defects. As the effort to test sequential defects can vary from short to short, a new testability analysis is presented. Based on this analysis a redesign of the circuit layout is proposed. This \"layout for testability\" approach is therefore a defect oriented equivalent for \"design for testability\" methods.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131729344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Reconfigurable architectures have becoming very relevant in recent years. In this paper we propose a methodology dedicated to analyze interactive applications in order to execute them in a SIMD reconfigurable architecture taking into account power/performance trade-offs. This methodology starts from a kernel description of the interactive application. Kernels are conditionally executed depending on dynamic conditions like user's input data manipulation. The volume of data involved in this kind of applications combined with user's actions occurring at unexpected times strongly impact on performance. We define an execution model to deal with conditional branches accompanied by a data prefetch scheme in order to avoid reconfigurable processing unit stalls due to operands unavailability. Experimental results satisfy time constraints of interactive applications and show a power effective solution for them.
{"title":"An approach to execute conditional branches onto SIMD multi-context reconfigurable architectures","authors":"F. Rivera, Milagros Fernández, N. Bagherzadeh","doi":"10.1109/DSD.2005.14","DOIUrl":"https://doi.org/10.1109/DSD.2005.14","url":null,"abstract":"Reconfigurable architectures have becoming very relevant in recent years. In this paper we propose a methodology dedicated to analyze interactive applications in order to execute them in a SIMD reconfigurable architecture taking into account power/performance trade-offs. This methodology starts from a kernel description of the interactive application. Kernels are conditionally executed depending on dynamic conditions like user's input data manipulation. The volume of data involved in this kind of applications combined with user's actions occurring at unexpected times strongly impact on performance. We define an execution model to deal with conditional branches accompanied by a data prefetch scheme in order to avoid reconfigurable processing unit stalls due to operands unavailability. Experimental results satisfy time constraints of interactive applications and show a power effective solution for them.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130641555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper describes the organization and use of a pipeline that is tightly-coupled to the CPU inside a platform FPGA with support for dynamic partial reconfiguration. It describes the overall hardware system organization and the pipeline structure, and presents the associated development environment and run-time support system, including the support for dynamically changing pipeline implementations and altering the operations of a pipeline stage.
{"title":"Using a tightly-coupled pipeline in dynamically reconfigurable platform FPGAs","authors":"M. Silva, J. Ferreira","doi":"10.1109/DSD.2005.74","DOIUrl":"https://doi.org/10.1109/DSD.2005.74","url":null,"abstract":"The paper describes the organization and use of a pipeline that is tightly-coupled to the CPU inside a platform FPGA with support for dynamic partial reconfiguration. It describes the overall hardware system organization and the pipeline structure, and presents the associated development environment and run-time support system, including the support for dynamically changing pipeline implementations and altering the operations of a pipeline stage.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124006844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the paper, the principles of scan educational tool are presented. First, the motivation for this activity is briefly mentioned. Then, the structure of software package together with the principles of communicating and controlling the tools belonging to the system are explained. It is shown how the system can be utilized for testability analysis and design for testability demonstrations resulting in applying scan design principles in the design.
{"title":"Educational tool for the demonstration of DfT principles based on scan methodologies","authors":"Josef Strnadel, Z. Kotásek","doi":"10.1109/DSD.2005.36","DOIUrl":"https://doi.org/10.1109/DSD.2005.36","url":null,"abstract":"In the paper, the principles of scan educational tool are presented. First, the motivation for this activity is briefly mentioned. Then, the structure of software package together with the principles of communicating and controlling the tools belonging to the system are explained. It is shown how the system can be utilized for testability analysis and design for testability demonstrations resulting in applying scan design principles in the design.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115049095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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