The implementation of a retargetable microcode generator system (RMGS) is described for a six-stage translation system. Portability of microcode is achieved by specifying microprograms in a C-like HLL (high-level language) and translating the specification into horizontal microcode. The HLL microprogram description is translated into an intermediate semantic description language (ISDL). The ISDL specification is then translated into a machine-dependent microcode using a heuristic pattern-matched code generator. Retargetability to a wide variety of machines is achieved through a semantic description of a particular machine. The code is compacted using a greedy heuristic strategy. Optimization techniques are applied to the intermediate form by shape analysis, during code generation through cost analysis, and during compaction through an optimal graph coloring inherent to the compaction strategy.<>
{"title":"Towards portable microcode","authors":"R. E. Boring, M. Andrews, F. Lam","doi":"10.1109/REG5.1988.15888","DOIUrl":"https://doi.org/10.1109/REG5.1988.15888","url":null,"abstract":"The implementation of a retargetable microcode generator system (RMGS) is described for a six-stage translation system. Portability of microcode is achieved by specifying microprograms in a C-like HLL (high-level language) and translating the specification into horizontal microcode. The HLL microprogram description is translated into an intermediate semantic description language (ISDL). The ISDL specification is then translated into a machine-dependent microcode using a heuristic pattern-matched code generator. Retargetability to a wide variety of machines is achieved through a semantic description of a particular machine. The code is compacted using a greedy heuristic strategy. Optimization techniques are applied to the intermediate form by shape analysis, during code generation through cost analysis, and during compaction through an optimal graph coloring inherent to the compaction strategy.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127820575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A rotational transform is described that has been developed to reduce a large linear electrical system into an equivalent system of reduced size. The transform is a power-invariant transform not unlike n-port reduction. However, where n-port reduction will eliminate nodes (or loops) entirely from a circuit, this reduction instead will replace these nodes (loops) with a single equivalent node (loop). The significance of the transform is found in the usefulness of the equivalent node. The voltage magnitude and angle are open to free choice, and this choice can be judiciously made to preserve desired properties of the reduced regions of the circuit.<>
{"title":"A rotational transform for reducing large circuits preserving a regional centroid","authors":"S. Stanton, D. R. Waggoner","doi":"10.1109/REG5.1988.15940","DOIUrl":"https://doi.org/10.1109/REG5.1988.15940","url":null,"abstract":"A rotational transform is described that has been developed to reduce a large linear electrical system into an equivalent system of reduced size. The transform is a power-invariant transform not unlike n-port reduction. However, where n-port reduction will eliminate nodes (or loops) entirely from a circuit, this reduction instead will replace these nodes (loops) with a single equivalent node (loop). The significance of the transform is found in the usefulness of the equivalent node. The voltage magnitude and angle are open to free choice, and this choice can be judiciously made to preserve desired properties of the reduced regions of the circuit.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130971961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An expert system is being developed at Federal Express Corporation to assist the staff to diagnose problems and help customers recover from errors. The development schedule for the expert system diagnostic advisor, called the Hotline Help Desk, was divided into three phases. The first phase was developing a demonstration system. The second phase, a field test system, was an expanded demonstration system. Two months were allotted for adding as much new diagnostic knowledge as the time allowed. The third phase, the delivery system, is currently in progress. The first production implementation of the diagnostic advisor was completed in November, 1987. Characteristics of the diagnostic advisor are presented.<>
{"title":"A diagnostic advisor","authors":"G.B. Sauer, H.J. Derbort","doi":"10.1109/REG5.1988.15891","DOIUrl":"https://doi.org/10.1109/REG5.1988.15891","url":null,"abstract":"An expert system is being developed at Federal Express Corporation to assist the staff to diagnose problems and help customers recover from errors. The development schedule for the expert system diagnostic advisor, called the Hotline Help Desk, was divided into three phases. The first phase was developing a demonstration system. The second phase, a field test system, was an expanded demonstration system. Two months were allotted for adding as much new diagnostic knowledge as the time allowed. The third phase, the delivery system, is currently in progress. The first production implementation of the diagnostic advisor was completed in November, 1987. Characteristics of the diagnostic advisor are presented.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"44 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113962326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Simulation and threshold logic are used to demonstrate the feasibility of a learning system that increases production output. Production is simulated with a discrete, next-event model having multiple paths and multiple processes on each path. Switches located throughout the model can direct production units to avoid bottlenecks and improve output. Each switch in the model is controlled by the action of threshold gates. For the process time configurations tested, minima were found to be associated with one or more of three threshold values set in 92% of the configurations. Using the three threshold value sets and a rule base for process time configurations that are not optimized by one of the three sets, a system may be created that avoids the computational costs and time delays of a multiple-trial optimizing system.<>
{"title":"The use of threshold logic to improve performance in scheduling a manufacturing process","authors":"E. T. Farley, D. Haworth","doi":"10.1109/REG5.1988.15890","DOIUrl":"https://doi.org/10.1109/REG5.1988.15890","url":null,"abstract":"Simulation and threshold logic are used to demonstrate the feasibility of a learning system that increases production output. Production is simulated with a discrete, next-event model having multiple paths and multiple processes on each path. Switches located throughout the model can direct production units to avoid bottlenecks and improve output. Each switch in the model is controlled by the action of threshold gates. For the process time configurations tested, minima were found to be associated with one or more of three threshold values set in 92% of the configurations. Using the three threshold value sets and a rule base for process time configurations that are not optimized by one of the three sets, a system may be created that avoids the computational costs and time delays of a multiple-trial optimizing system.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128434667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rapid thermal annealing is used to activate shallow-Be-implanted in GaAs. A proximity annealing technique is used which minimizes As evaporation. Because the substrate is left capless during annealing, surface interaction with the cap and interfacial stress are relieved. Surface morphology and Be redistribution during annealing are analyzed by scanning electron microscopy and secondary ion mass spectroscopy, respectively. Electrical characterization of the activated implant is achieved by means of a rapid thermally alloyed Au-Zn-Au contact using Van der Pauw patterns and the transmission line method. Nearly 100% implant activation and ohmic contacts are achieved.<>
{"title":"Rapid thermal annealing of Be implanted GaAs","authors":"Y. Lu, T. Kalkur, C. A. Paz de Araújo","doi":"10.1109/REG5.1988.15903","DOIUrl":"https://doi.org/10.1109/REG5.1988.15903","url":null,"abstract":"Rapid thermal annealing is used to activate shallow-Be-implanted in GaAs. A proximity annealing technique is used which minimizes As evaporation. Because the substrate is left capless during annealing, surface interaction with the cap and interfacial stress are relieved. Surface morphology and Be redistribution during annealing are analyzed by scanning electron microscopy and secondary ion mass spectroscopy, respectively. Electrical characterization of the activated implant is achieved by means of a rapid thermally alloyed Au-Zn-Au contact using Van der Pauw patterns and the transmission line method. Nearly 100% implant activation and ohmic contacts are achieved.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126204013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Current and future requirements are considered to be placing growing demands on real-time radar simulators that cannot be met using traditional approaches. The authors describe an advanced approach to real-time radar simulation. The approach is based on emerging hardware and software technologies, and is well suited to many applications. The radar modeling approach can be used for all detection modes. In order to provide a high degree of flexibility, modularity is stressed during software development. Databases containing key design parameters are maintained to provide a high degree of flexibility and ease of reconfigurability to the radar simulator. Implementations are discussed.<>
{"title":"Advances in realtime radar simulation","authors":"G.L. Bair, D. Johnston","doi":"10.1109/REG5.1988.15893","DOIUrl":"https://doi.org/10.1109/REG5.1988.15893","url":null,"abstract":"Current and future requirements are considered to be placing growing demands on real-time radar simulators that cannot be met using traditional approaches. The authors describe an advanced approach to real-time radar simulation. The approach is based on emerging hardware and software technologies, and is well suited to many applications. The radar modeling approach can be used for all detection modes. In order to provide a high degree of flexibility, modularity is stressed during software development. Databases containing key design parameters are maintained to provide a high degree of flexibility and ease of reconfigurability to the radar simulator. Implementations are discussed.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128131779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In order to encourage prospective students to consider graduate school, some senior undergraduate lab projects have been designed to give the student an introduction to the type of projects available to the electrical engineering graduate. Projects in the areas of pulsed power, image processing, neural networks, optical computing, and plasma research are available. Special lab projects provide the student with the opportunity to become acquainted with the faculty advisor and possible thesis topics. These lab projects provide the student with a better understanding of the available career options. Three projects are described and the objectives of each is discussed.<>
{"title":"An approach to increase graduate school enrollment in engineering","authors":"E. K. Arrant","doi":"10.1109/REG5.1988.15919","DOIUrl":"https://doi.org/10.1109/REG5.1988.15919","url":null,"abstract":"In order to encourage prospective students to consider graduate school, some senior undergraduate lab projects have been designed to give the student an introduction to the type of projects available to the electrical engineering graduate. Projects in the areas of pulsed power, image processing, neural networks, optical computing, and plasma research are available. Special lab projects provide the student with the opportunity to become acquainted with the faculty advisor and possible thesis topics. These lab projects provide the student with a better understanding of the available career options. Three projects are described and the objectives of each is discussed.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125920518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel surface channel charge-coupled device (CCD) using an AlGaAs/GaAs heterostructure is presented. Charge storage device characteristics have been determined relative to the unintentionally doped and depleted AlGaAs layer. This layer serves as an effective substitute for the traditional silicon dioxide insulator in a MOS diode. At Q/sub sig/=0 and x<<1, where x is the aluminum mole fraction, the heterostructure has shown a near one-to-one correspondence between the effective gate voltage and the surface potential. It is shown that the material properties of the AlGaAs layer permit better control of the surface potential and charge transfer, thereby offering the possibility of performance superior to current Si-MOS CCDs.<>
{"title":"Charge storage in AlGaAs/GaAs heterojunction surface channel CCDs","authors":"A. Krikos, C. A. Paz de Araújo","doi":"10.1109/REG5.1988.15905","DOIUrl":"https://doi.org/10.1109/REG5.1988.15905","url":null,"abstract":"A novel surface channel charge-coupled device (CCD) using an AlGaAs/GaAs heterostructure is presented. Charge storage device characteristics have been determined relative to the unintentionally doped and depleted AlGaAs layer. This layer serves as an effective substitute for the traditional silicon dioxide insulator in a MOS diode. At Q/sub sig/=0 and x<<1, where x is the aluminum mole fraction, the heterostructure has shown a near one-to-one correspondence between the effective gate voltage and the surface potential. It is shown that the material properties of the AlGaAs layer permit better control of the surface potential and charge transfer, thereby offering the possibility of performance superior to current Si-MOS CCDs.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130292441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Several algorithms for the minimization of control memory bit dimension are presented and evaluated. Early methods used techniques well known to switching theory, such as compatible classes and cover tables. The drawback in this approach is that the cover tables become unmanageably large for most real applications. The problem was then reformulated in the context of linear programming. However, this method still requires a lot of enumeration and always leads to an absolute minimal solution. A branch-and-bound algorithm is presented. Although it is exponential in the worst case, the procedure is found to be more efficient than the earlier enumerative methods.<>
{"title":"Minimization of the width of control memory: a survey","authors":"T. Ferguson","doi":"10.1109/REG5.1988.15932","DOIUrl":"https://doi.org/10.1109/REG5.1988.15932","url":null,"abstract":"Several algorithms for the minimization of control memory bit dimension are presented and evaluated. Early methods used techniques well known to switching theory, such as compatible classes and cover tables. The drawback in this approach is that the cover tables become unmanageably large for most real applications. The problem was then reformulated in the context of linear programming. However, this method still requires a lot of enumeration and always leads to an absolute minimal solution. A branch-and-bound algorithm is presented. Although it is exponential in the worst case, the procedure is found to be more efficient than the earlier enumerative methods.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116503379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An outline is presented of a computer thermal analysis model that inputs information for existing computer-aided design (CAD) layout files. This model assumes conductive heat flow to determine the difference in temperature from the junction-to-case for multiple heat sources and uses this information to create a CAD-compatible drawing of the isotherms. The development and input/output of the model are discussed. The model is verified by using experimental data obtained from hybrids built-up with thermal test chips.<>
{"title":"Thermal modeling of hybrid microelectronics","authors":"D. Reed, B. Gartner","doi":"10.1109/REG5.1988.15938","DOIUrl":"https://doi.org/10.1109/REG5.1988.15938","url":null,"abstract":"An outline is presented of a computer thermal analysis model that inputs information for existing computer-aided design (CAD) layout files. This model assumes conductive heat flow to determine the difference in temperature from the junction-to-case for multiple heat sources and uses this information to create a CAD-compatible drawing of the isotherms. The development and input/output of the model are discussed. The model is verified by using experimental data obtained from hybrids built-up with thermal test chips.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134029206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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