SCARA (selective compliance assembly robot arm) robots are frequently used for light pick-and-place type assembly tasks, and typically offer repeatability of +or-0.025 to +or-0.05 mm (+or-1 to 2 mils). Metrological data taken at a variety of positions, scattered throughout the horizontal plane of the robots' Cartesian workspace, indicates that the robot typically fails to respond to very small bands of displacement commands which correspond to the angular bands of physical motion within which the position feedback encoders present discrete values for displacement. An analysis is presented of the small-displacement behavior of a SCARA robot within the range of its repeatability specification, showing that it is basically dependent on the digitized resolution of the axial-joint-position feedback encoders.<>
{"title":"A metrological study of the small displacement behaviour of a SCARA type pick and place robot","authors":"D.H. Eppes, R. Flake","doi":"10.1109/REG5.1988.15934","DOIUrl":"https://doi.org/10.1109/REG5.1988.15934","url":null,"abstract":"SCARA (selective compliance assembly robot arm) robots are frequently used for light pick-and-place type assembly tasks, and typically offer repeatability of +or-0.025 to +or-0.05 mm (+or-1 to 2 mils). Metrological data taken at a variety of positions, scattered throughout the horizontal plane of the robots' Cartesian workspace, indicates that the robot typically fails to respond to very small bands of displacement commands which correspond to the angular bands of physical motion within which the position feedback encoders present discrete values for displacement. An analysis is presented of the small-displacement behavior of a SCARA robot within the range of its repeatability specification, showing that it is basically dependent on the digitized resolution of the axial-joint-position feedback encoders.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"48 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123042941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A system interface is described for a specific CCD image sensor that digitizes and collects the image from the sensor for storage in a personal computer. The output of the CCD image sensor is fed through an 8-bit flash analog-to-digital convertor and stored in a buffer memory. During the next integration period the image is loaded into the computer and processed. The system allows the imager to utilize the full silicon area and eliminates the need for mechanical shutters normally required to use CCD sensors of this type.<>
{"title":"A CCD image sensor frame grabber","authors":"M. Parten, K. Mau","doi":"10.1109/REG5.1988.15909","DOIUrl":"https://doi.org/10.1109/REG5.1988.15909","url":null,"abstract":"A system interface is described for a specific CCD image sensor that digitizes and collects the image from the sensor for storage in a personal computer. The output of the CCD image sensor is fed through an 8-bit flash analog-to-digital convertor and stored in a buffer memory. During the next integration period the image is loaded into the computer and processed. The system allows the imager to utilize the full silicon area and eliminates the need for mechanical shutters normally required to use CCD sensors of this type.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123509731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R.J. Pennnington, K. Bosworth, P. Wheeler, G. S. Stiles, A. Raghuram
The arrival of parallel processing architectures has generated considerable interest in mapping conventional sequential jobs onto the new machines (multiprocessor arrays). The problem is in finding and exploiting the parallelism in a given task. The authors outline some important findings on a branch-and-bound algorithm and how it was modified to run on a multiprocessor network of Transputers.<>
{"title":"Parallel implementations of a branch-and-bound algorithm for the optimization of distributed database computer networks","authors":"R.J. Pennnington, K. Bosworth, P. Wheeler, G. S. Stiles, A. Raghuram","doi":"10.1109/REG5.1988.15939","DOIUrl":"https://doi.org/10.1109/REG5.1988.15939","url":null,"abstract":"The arrival of parallel processing architectures has generated considerable interest in mapping conventional sequential jobs onto the new machines (multiprocessor arrays). The problem is in finding and exploiting the parallelism in a given task. The authors outline some important findings on a branch-and-bound algorithm and how it was modified to run on a multiprocessor network of Transputers.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115788901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The proposed multiplier views the operations as a logical one, without using addition or counting. Such a novel view provides grounds for a high pipeline throughput. The authors discuss the algorithm and then the cell design, cell placement, and a routing scheme in the VLSI layout of the proposed multiplier using CMOS technology. Then they compare their design against a number of recently proposed systolic multipliers, using multiplication delay as the comparison measure. They conclude that the proposed design outperforms most of the existing schemes for different multiplication sizes.<>
{"title":"VLSI layout of a pipelined multiplier","authors":"B. Shirazi, P. Mukherjee","doi":"10.1109/REG5.1988.15913","DOIUrl":"https://doi.org/10.1109/REG5.1988.15913","url":null,"abstract":"The proposed multiplier views the operations as a logical one, without using addition or counting. Such a novel view provides grounds for a high pipeline throughput. The authors discuss the algorithm and then the cell design, cell placement, and a routing scheme in the VLSI layout of the proposed multiplier using CMOS technology. Then they compare their design against a number of recently proposed systolic multipliers, using multiplication delay as the comparison measure. They conclude that the proposed design outperforms most of the existing schemes for different multiplication sizes.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128151673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Electronic microcircuit technology has evolved so rapidly that parts designed may become obsolete when production starts or during the production cycle. The authors explore methods to combat the parts obsolescence problem. They argue that the earlier in a program that obsolescence is treated, the greater the possibility that obsolescence will not become a problem.<>
{"title":"Microcircuit parts obsolescence","authors":"J. Leonard, J. Wolf, R. Stolinski","doi":"10.1109/REG5.1988.15936","DOIUrl":"https://doi.org/10.1109/REG5.1988.15936","url":null,"abstract":"Electronic microcircuit technology has evolved so rapidly that parts designed may become obsolete when production starts or during the production cycle. The authors explore methods to combat the parts obsolescence problem. They argue that the earlier in a program that obsolescence is treated, the greater the possibility that obsolescence will not become a problem.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130005959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The four major design-for-testability (DFT) techniques-ad hoc, built-in-self-test (BIST), structured, and semistructured approaches-differ widely in their ability to meet a products test needs. A few practical guidelines can aid in choosing the DFT approach that is best for your project. The techniques are reviewed, followed by a description of the selection criteria, and concluding with the various DFT techniques being compared using the criteria to do the tradeoff analysis.<>
{"title":"Considerations in selecting a design-for-testability technique","authors":"R. Hess","doi":"10.1109/REG5.1988.15921","DOIUrl":"https://doi.org/10.1109/REG5.1988.15921","url":null,"abstract":"The four major design-for-testability (DFT) techniques-ad hoc, built-in-self-test (BIST), structured, and semistructured approaches-differ widely in their ability to meet a products test needs. A few practical guidelines can aid in choosing the DFT approach that is best for your project. The techniques are reviewed, followed by a description of the selection criteria, and concluding with the various DFT techniques being compared using the criteria to do the tradeoff analysis.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"480 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130642290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The author develops the LMS algorithm for a recursive asymmetrical equalizer. By expressing the terms needed to update the equalizer coefficients in the Z-transform domain, he shows that a common recursive filter structure may be used both for the equalizer and to generate the terms needed to update the coefficients of the equalizer. Simulation confirms the algorithm and the implementation.<>
{"title":"A preliminary investigation of a recursive asymmetrical adaptive filter for correcting asymmetrical distortions","authors":"R. Turcotte","doi":"10.1109/REG5.1988.15901","DOIUrl":"https://doi.org/10.1109/REG5.1988.15901","url":null,"abstract":"The author develops the LMS algorithm for a recursive asymmetrical equalizer. By expressing the terms needed to update the equalizer coefficients in the Z-transform domain, he shows that a common recursive filter structure may be used both for the equalizer and to generate the terms needed to update the coefficients of the equalizer. Simulation confirms the algorithm and the implementation.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122432197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To overcome the shortcoming of time-consuming digital signal processing functions performed in a NS32016 microcomputer system, the TMS32010 serves as an independent numeric processor to implement the numeric processor to implement the numeric intensive algorithms. Hardware developments including direct memory expansion and extended memory interface are presented. Also, ADC (analog-to-digital conversion) and DAC (digital-to-analog conversion) are provided by this system to perform various DSP (digital signal processing) applications. Software development of this enhanced DSP system can be expanded to various applications. Some demonstration programs including an FIR bandpass filter, an IIR low-pass filter, and a rotation (graphics) application were used to test the system.<>
{"title":"An enhancement of the TMS32010 digital signal processor in a NS32016 microcomputer system","authors":"P. Giang, K. Hambacker, D. F. Dawson","doi":"10.1109/REG5.1988.15914","DOIUrl":"https://doi.org/10.1109/REG5.1988.15914","url":null,"abstract":"To overcome the shortcoming of time-consuming digital signal processing functions performed in a NS32016 microcomputer system, the TMS32010 serves as an independent numeric processor to implement the numeric processor to implement the numeric intensive algorithms. Hardware developments including direct memory expansion and extended memory interface are presented. Also, ADC (analog-to-digital conversion) and DAC (digital-to-analog conversion) are provided by this system to perform various DSP (digital signal processing) applications. Software development of this enhanced DSP system can be expanded to various applications. Some demonstration programs including an FIR bandpass filter, an IIR low-pass filter, and a rotation (graphics) application were used to test the system.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128885712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A model of direct-sequence spread-spectrum carriers accessing a limiting satellite repeater in the presence of strong interference (tone jamming, other users, and Gaussian noise) is presented. A simplified phasor analysis is used to obtain a strict upper bound on system bit error rate. Comparisons are made of the bit error rate for a limiting repeater system and that obtained for a linear repeater system. For a quadriphase spreading code, the upper bound on the average degradation due to the limiting repeater was approximately 4 dB for an error probability of 10/sup -4/.<>
提出了在强干扰(音干扰、其他用户干扰和高斯噪声)存在的情况下，直接序列扩频载波访问受限卫星中继器的模型。采用简化相量分析得到系统误码率的严格上限。比较了限制中继器系统的误码率和线性中继器系统的误码率。对于四相扩频码，在误差概率为10/sup -4/.>的情况下，由极限中继器引起的平均衰减的上界约为4 dB
{"title":"Modeling multiple access to a hard limiting direct-sequence spread spectrum satellite repeater using phasor analysis","authors":"M. R. Ehrlich, J. Liebetreu","doi":"10.1109/REG5.1988.15926","DOIUrl":"https://doi.org/10.1109/REG5.1988.15926","url":null,"abstract":"A model of direct-sequence spread-spectrum carriers accessing a limiting satellite repeater in the presence of strong interference (tone jamming, other users, and Gaussian noise) is presented. A simplified phasor analysis is used to obtain a strict upper bound on system bit error rate. Comparisons are made of the bit error rate for a limiting repeater system and that obtained for a linear repeater system. For a quadriphase spreading code, the upper bound on the average degradation due to the limiting repeater was approximately 4 dB for an error probability of 10/sup -4/.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115450088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The author points out the importance of the involvement of the design and manufacturing team in achieving reliability of microelectronic devices. A method of verifying reliability goals through calculation of failure rates based on life test parameters is described. An example illustrating the method is shown.<>
{"title":"Microelectronics reliability","authors":"J.W. Meredith","doi":"10.1109/REG5.1988.15935","DOIUrl":"https://doi.org/10.1109/REG5.1988.15935","url":null,"abstract":"The author points out the importance of the involvement of the design and manufacturing team in achieving reliability of microelectronic devices. A method of verifying reliability goals through calculation of failure rates based on life test parameters is described. An example illustrating the method is shown.<<ETX>>","PeriodicalId":126733,"journal":{"name":"IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology'","volume":"374 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123495370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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