Juan A. Colmenares, C. Im, Kane Kim, R. Klefstad, Chae-Deok Lim, Etri Korea
A hybrid approach to deriving tight execution-time bounds of program segments was proposed very recently. This approach symbiotically combines analytical and measurement-based methods to find a tight execution- time bound falling between the maximum measured execution time and an analytically derived loose bound. It also enables the estimation of the probability of the derived tight bound not being exceeded at run time. This paper provides a refined description of the hybrid approach and presents techniques for measuring the execution times of acyclic-path segments (APSs), which are possible execution sequences of instructions that contain no cycles and the basic units of analysis in the hybrid approach. In this paper, we also report the results of the hybrid approach in the derivation of tight execution-time bounds of three algorithms frequently used in the evaluation of WCET analysis techniques.
{"title":"Measurement Techniques in a Hybrid Approach for Deriving Tight Execution-time Bounds of Program Segments in Fully-featured Processors","authors":"Juan A. Colmenares, C. Im, Kane Kim, R. Klefstad, Chae-Deok Lim, Etri Korea","doi":"10.1109/RTAS.2008.35","DOIUrl":"https://doi.org/10.1109/RTAS.2008.35","url":null,"abstract":"A hybrid approach to deriving tight execution-time bounds of program segments was proposed very recently. This approach symbiotically combines analytical and measurement-based methods to find a tight execution- time bound falling between the maximum measured execution time and an analytically derived loose bound. It also enables the estimation of the probability of the derived tight bound not being exceeded at run time. This paper provides a refined description of the hybrid approach and presents techniques for measuring the execution times of acyclic-path segments (APSs), which are possible execution sequences of instructions that contain no cycles and the basic units of analysis in the hybrid approach. In this paper, we also report the results of the hybrid approach in the derivation of tight execution-time bounds of three algorithms frequently used in the evaluation of WCET analysis techniques.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126069682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We build on PTIDES, a programming model for distributed embedded systems that uses discrete-event (DE) models as program specifications. PTIDES improves on distributed DE execution by allowing more concurrent event processing without backtracking. This paper discusses the general execution strategy for PTIDES, and provides two feasible implementations. This execution strategy is then extended with tolerance for hardware errors. We take a program transformation approach to automatically enhance DE models with incremental checkpointing and state recovery functionality. Our fault tolerance mechanism is lightweight and has low overhead. It requires very little human intervention. We incorporate this mechanism into PTIDES for efficient execution of fault- tolerant real-time distributed DE systems.
{"title":"Real-Time Distributed Discrete-Event Execution with Fault Tolerance","authors":"T. Feng, Edward A. Lee","doi":"10.1109/RTAS.2008.22","DOIUrl":"https://doi.org/10.1109/RTAS.2008.22","url":null,"abstract":"We build on PTIDES, a programming model for distributed embedded systems that uses discrete-event (DE) models as program specifications. PTIDES improves on distributed DE execution by allowing more concurrent event processing without backtracking. This paper discusses the general execution strategy for PTIDES, and provides two feasible implementations. This execution strategy is then extended with tolerance for hardware errors. We take a program transformation approach to automatically enhance DE models with incremental checkpointing and state recovery functionality. Our fault tolerance mechanism is lightweight and has low overhead. It requires very little human intervention. We incorporate this mechanism into PTIDES for efficient execution of fault- tolerant real-time distributed DE systems.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123924988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Interactive 3D games are now widely available on a variety of mobile devices for which battery-life is a major concern. Many of these devices support voltage/frequency-scalable processors and dynamic voltage scaling (DVS) has emerged as a powerful technique for energy management in such devices. Although DVS algorithms have been very successfully applied to video encoding/decoding applications, their use in interactive computer games has not been sufficiently explored so far. In this paper we propose a novel DVS scheme that is specifically directed towards interactive 3D game applications running on battery-operated portable devices. The key to this DVS scheme lies in an accurate prediction of the rendering workload of a current game scene. We have applied this scheme to first person shooter games (e.g. Quake II) and obtained significant power savings while maintaining high frame rates. Based on the observation that there exist two types of workload variations in such games, we compute the voltage/frequency setting for any game scene using a hybrid combination of two different techniques: (i) adjusting the workload prediction using a control-theoretical feedback mechanism, and (ii) analyzing the graphical objects in the current game scene by parsing the corresponding frame. Our scheme is significantly different from those commonly applied to video decoding applications (where only technique (i) is used) and has shown very encouraging results when evaluated with different setups (e.g. laptop running Windows, PDA running Windows Mobile and a configurable simulation platform).
{"title":"A Hybrid DVS Scheme for Interactive 3D Games","authors":"Yan Gu, S. Chakraborty","doi":"10.1109/RTAS.2008.33","DOIUrl":"https://doi.org/10.1109/RTAS.2008.33","url":null,"abstract":"Interactive 3D games are now widely available on a variety of mobile devices for which battery-life is a major concern. Many of these devices support voltage/frequency-scalable processors and dynamic voltage scaling (DVS) has emerged as a powerful technique for energy management in such devices. Although DVS algorithms have been very successfully applied to video encoding/decoding applications, their use in interactive computer games has not been sufficiently explored so far. In this paper we propose a novel DVS scheme that is specifically directed towards interactive 3D game applications running on battery-operated portable devices. The key to this DVS scheme lies in an accurate prediction of the rendering workload of a current game scene. We have applied this scheme to first person shooter games (e.g. Quake II) and obtained significant power savings while maintaining high frame rates. Based on the observation that there exist two types of workload variations in such games, we compute the voltage/frequency setting for any game scene using a hybrid combination of two different techniques: (i) adjusting the workload prediction using a control-theoretical feedback mechanism, and (ii) analyzing the graphical objects in the current game scene by parsing the corresponding frame. Our scheme is significantly different from those commonly applied to video decoding applications (where only technique (i) is used) and has shown very encouraging results when evaluated with different setups (e.g. laptop running Windows, PDA running Windows Mobile and a configurable simulation platform).","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122017055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The convergence of computers and the physical world is the theme for next generation networking research. This trend calls for real-time network infrastructure, which requires a high-speed real-time WAN to serve as its backbone. However, commercially available high-speed WAN switches (routers) are designed for best-effort Internet traffic. A real-time switch design for the aforementioned networks is missing. We propose a real-time switch design using a crossbar switching fabric. The proposed switch can be implemented by making minimal modification, or even simplification, to the widely implemented iSLIP crossbar switch scheduler. Our real-time switch serves periodic and aperiodic traffic with real-time virtual machine tasks, which simplifies analysis, provides isolation, and facilitates future hierarchical scheduling and flow aggregation. Taking advantage of the fact that most industrial real-time network flows rarely change, our switch is better adapted to providing high bandwidths and low latencies.
{"title":"A Switch Design for Real-Time Industrial Networks","authors":"Qixin Wang, S. Gopalakrishnan, Xue Liu, L. Sha","doi":"10.1109/RTAS.2008.8","DOIUrl":"https://doi.org/10.1109/RTAS.2008.8","url":null,"abstract":"The convergence of computers and the physical world is the theme for next generation networking research. This trend calls for real-time network infrastructure, which requires a high-speed real-time WAN to serve as its backbone. However, commercially available high-speed WAN switches (routers) are designed for best-effort Internet traffic. A real-time switch design for the aforementioned networks is missing. We propose a real-time switch design using a crossbar switching fabric. The proposed switch can be implemented by making minimal modification, or even simplification, to the widely implemented iSLIP crossbar switch scheduler. Our real-time switch serves periodic and aperiodic traffic with real-time virtual machine tasks, which simplifies analysis, provides isolation, and facilitates future hierarchical scheduling and flow aggregation. Taking advantage of the fact that most industrial real-time network flows rarely change, our switch is better adapted to providing high bandwidths and low latencies.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132781134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jian-Jia Chen, Chuan-Yue Yang, Hsueh-I Lu, Tei-Wei Kuo
Energy-efficiency has been an important system issue in hardware and software designs for both real-time embedded systems and server systems. This research explores systems with probabilistic distribution on the execution time of realtime tasks on homogeneous multiprocessor platforms with the capability of dynamic voltage scaling (DVS). The objective is to derive a task partition which minimizes the expected energy consumption for completing all the given tasks in time. We give an efficient 1.13-approximation algorithm and a polynomial-time approximation scheme (PTAS) to provide worst-case guarantees for the strongly NP-hard problem. Experimental results show that the algorithms can effectively minimize the expected energy consumption.
{"title":"Approximation Algorithms for Multiprocessor Energy-Efficient Scheduling of Periodic Real-Time Tasks with Uncertain Task Execution Time","authors":"Jian-Jia Chen, Chuan-Yue Yang, Hsueh-I Lu, Tei-Wei Kuo","doi":"10.1109/RTAS.2008.24","DOIUrl":"https://doi.org/10.1109/RTAS.2008.24","url":null,"abstract":"Energy-efficiency has been an important system issue in hardware and software designs for both real-time embedded systems and server systems. This research explores systems with probabilistic distribution on the execution time of realtime tasks on homogeneous multiprocessor platforms with the capability of dynamic voltage scaling (DVS). The objective is to derive a task partition which minimizes the expected energy consumption for completing all the given tasks in time. We give an efficient 1.13-approximation algorithm and a polynomial-time approximation scheme (PTAS) to provide worst-case guarantees for the strongly NP-hard problem. Experimental results show that the algorithms can effectively minimize the expected energy consumption.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125893184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Message sequence charts (MSCs) are widely used for describing interaction scenarios between the components of a distributed system. Consequently, worst-case response time estimation and schedulability analysis of MSC-based specifications form natural building blocks for designing distributed real-time systems. However, currently there exists a large gap between the timing and quantitative performance analysis techniques that exist in the real-time systems literature, and the modeling/specification techniques that are advocated by the formal methods community. As a result, although a number of schedulability analysis techniques are known for a variety of task graph-based models, it is not clear if they can be used to effectively analyze standard specification formalisms such as MSCs. In this paper we make an attempt to bridge this gap by proposing a schedulability analysis technique for MSC-based system specifications. We show that compared to existing timing analysis techniques for distributed real-time systems, our proposed analysis gives tighter results, which immediately translate to better system design and improved resource dimensioning. We illustrate the details of our analysis using a setup from the automotive electronics domain, which consist of two real-life application programs (that are naturally modeled using MSCs) running on a platform consisting of multiple electronic control units (ECUs) connected via a FlexRay bus.
{"title":"Schedulability Analysis of MSC-based System Models","authors":"Lei Ju, Abhik Roychoudhury, S. Chakraborty","doi":"10.1109/RTAS.2008.9","DOIUrl":"https://doi.org/10.1109/RTAS.2008.9","url":null,"abstract":"Message sequence charts (MSCs) are widely used for describing interaction scenarios between the components of a distributed system. Consequently, worst-case response time estimation and schedulability analysis of MSC-based specifications form natural building blocks for designing distributed real-time systems. However, currently there exists a large gap between the timing and quantitative performance analysis techniques that exist in the real-time systems literature, and the modeling/specification techniques that are advocated by the formal methods community. As a result, although a number of schedulability analysis techniques are known for a variety of task graph-based models, it is not clear if they can be used to effectively analyze standard specification formalisms such as MSCs. In this paper we make an attempt to bridge this gap by proposing a schedulability analysis technique for MSC-based system specifications. We show that compared to existing timing analysis techniques for distributed real-time systems, our proposed analysis gives tighter results, which immediately translate to better system design and improved resource dimensioning. We illustrate the details of our analysis using a setup from the automotive electronics domain, which consist of two real-life application programs (that are naturally modeled using MSCs) running on a platform consisting of multiple electronic control units (ECUs) connected via a FlexRay bus.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129891949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dynamic power management (DPM) techniques are crucial in minimizing the overall energy consumption in real-time embedded systems. The timing constraints of real-time applications and non-trivial time/energy transition overheads introduce significant challenges, as the device sleep intervals should be longer than a minimum threshold (called the break-even time) to ensure energy-efficiency. In this paper, we present a novel approach to the real-time DPM problem by explicitly enforcing long device sleep intervals for different devices, called device forbidden regions. We focus on the application of our technique to task systems with rate-monotonic priorities, and develop our algorithm DFR-RMS. Our solution includes a static component where the duration and frequency of forbidden regions are determined through the extended time-demand analysis to preserve the temporal correctness of all the tasks, while enhancing the energy savings. Then, we present a sophisticated on-line component which interacts with existing prediction-based DPM schemes to realize the full potential of device forbidden regions. Further, our scheme can be used with or without dynamic voltage scaling (DVS). Our experimental evaluation hints that significant energy gains can be obtained, when compared to the existing prediction-based techniques. Another contribution of this research effort is to show that the general problem of generating feasible schedules for preemptive periodic real-time tasks where all device sleep intervals are longer than the device break-even times is NP-hard in the strong sense.
{"title":"Real-Time Dynamic Power Management through Device Forbidden Regions","authors":"V. Devadas, Hakan Aydin","doi":"10.1109/RTAS.2008.21","DOIUrl":"https://doi.org/10.1109/RTAS.2008.21","url":null,"abstract":"Dynamic power management (DPM) techniques are crucial in minimizing the overall energy consumption in real-time embedded systems. The timing constraints of real-time applications and non-trivial time/energy transition overheads introduce significant challenges, as the device sleep intervals should be longer than a minimum threshold (called the break-even time) to ensure energy-efficiency. In this paper, we present a novel approach to the real-time DPM problem by explicitly enforcing long device sleep intervals for different devices, called device forbidden regions. We focus on the application of our technique to task systems with rate-monotonic priorities, and develop our algorithm DFR-RMS. Our solution includes a static component where the duration and frequency of forbidden regions are determined through the extended time-demand analysis to preserve the temporal correctness of all the tasks, while enhancing the energy savings. Then, we present a sophisticated on-line component which interacts with existing prediction-based DPM schemes to realize the full potential of device forbidden regions. Further, our scheme can be used with or without dynamic voltage scaling (DVS). Our experimental evaluation hints that significant energy gains can be obtained, when compared to the existing prediction-based techniques. Another contribution of this research effort is to show that the general problem of generating feasible schedules for preemptive periodic real-time tasks where all device sleep intervals are longer than the device break-even times is NP-hard in the strong sense.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122851214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Interactive and batch tasks typically have aperiodic random demands and arrival patterns. Generally, interactive tasks are assigned high priority for high responsiveness. Batch tasks with less timing criticality are scheduled in background. Unfortunately, most real-time DVS algorithms focus only on the real-time task workload and timing constraints in determining the operating power-optimized clock frequency. This approach can often leave insufficient cycles for servicing interactive and batch tasks and lead to unacceptable tardiness in conventional applications. We present a power-management framework which ensures that conventional applications will obtain acceptable response times and workload throughput without breaking the temporal constraints of real-time tasks that use resource reservation. We propose two solutions: Background-Preserving and Background-On-Demand algorithms. The first scheme is straightforward and increases the clock frequencies of all tasks to accommodate a future non-real-time workload. The second scheme assigns two modes of frequencies to each task, normal mode and turbo mode. The turbo mode is triggered by the presence of a pending non-real-time task in the system. We also provide the integrated versions of both schemes with our dynamic slack reclamation DVS scheme, called the Progressive algorithm. The integrated versions exploit the slack time from underused reserves for saving more power without performance degradation in all applications.
{"title":"Coexistence of Real-Time and Interactive & Batch Tasks in DVS Systems","authors":"Saowanee Saewong, R. Rajkumar","doi":"10.1109/RTAS.2008.40","DOIUrl":"https://doi.org/10.1109/RTAS.2008.40","url":null,"abstract":"Interactive and batch tasks typically have aperiodic random demands and arrival patterns. Generally, interactive tasks are assigned high priority for high responsiveness. Batch tasks with less timing criticality are scheduled in background. Unfortunately, most real-time DVS algorithms focus only on the real-time task workload and timing constraints in determining the operating power-optimized clock frequency. This approach can often leave insufficient cycles for servicing interactive and batch tasks and lead to unacceptable tardiness in conventional applications. We present a power-management framework which ensures that conventional applications will obtain acceptable response times and workload throughput without breaking the temporal constraints of real-time tasks that use resource reservation. We propose two solutions: Background-Preserving and Background-On-Demand algorithms. The first scheme is straightforward and increases the clock frequencies of all tasks to accommodate a future non-real-time workload. The second scheme assigns two modes of frequencies to each task, normal mode and turbo mode. The turbo mode is triggered by the presence of a pending non-real-time task in the system. We also provide the integrated versions of both schemes with our dynamic slack reclamation DVS scheme, called the Progressive algorithm. The integrated versions exploit the slack time from underused reserves for saving more power without performance degradation in all applications.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115137710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able to accurately obtain the worst-case execution time (WCET) of applications running on multi-core platforms, which is very challenging due to the possible runtime inter-core interferences in using shared resources such as the shared L2 caches. As the first step toward time-predictable multi-core computing, this paper presents a novel approach to bounding the worst-case performance for threads running on multi-core processors with shared L2 instruction caches. The idea of our approach is to compute the worst-case instruction access interferences between different threads based on the program control flow information of each thread, which can be statically analyzed. Our experiments indicate that the proposed approach can reasonably estimate the worst- case shared L2 instruction cache misses by considering inter-thread instruction conflicts. Also, the WCET of applications running on multi-core processors estimated by our approach is much better than the estimation by simply assuming all L2 instruction accesses are misses.
{"title":"WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches","authors":"Jun Yan, Wei Zhang","doi":"10.1109/RTAS.2008.6","DOIUrl":"https://doi.org/10.1109/RTAS.2008.6","url":null,"abstract":"Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able to accurately obtain the worst-case execution time (WCET) of applications running on multi-core platforms, which is very challenging due to the possible runtime inter-core interferences in using shared resources such as the shared L2 caches. As the first step toward time-predictable multi-core computing, this paper presents a novel approach to bounding the worst-case performance for threads running on multi-core processors with shared L2 instruction caches. The idea of our approach is to compute the worst-case instruction access interferences between different threads based on the program control flow information of each thread, which can be statically analyzed. Our experiments indicate that the proposed approach can reasonably estimate the worst- case shared L2 instruction cache misses by considering inter-thread instruction conflicts. Also, the WCET of applications running on multi-core processors estimated by our approach is much better than the estimation by simply assuming all L2 instruction accesses are misses.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124845651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we consider the problem of providing QoS guarantees to the execution of applications using the X11 window system. In particular, we offer a system level analysis of the issues encountered when using X11 to serve realtime applications. By using a tracer developed for the purpose we analyse in depth the internal behaviour of the system. The result of the analysis puts on display the adverse effect played by a non real-time scheduler on the performance of time-sensitive applications. Based on this analysis, we propose an alternative solution based on the CBS scheduler and prove its effectiveness by an extensive set of experiments on real hardware.
{"title":"QoS Support in the X11 Window System","authors":"Nicola Manica, Luca Abeni, L. Palopoli","doi":"10.1109/RTAS.2008.20","DOIUrl":"https://doi.org/10.1109/RTAS.2008.20","url":null,"abstract":"In this paper, we consider the problem of providing QoS guarantees to the execution of applications using the X11 window system. In particular, we offer a system level analysis of the issues encountered when using X11 to serve realtime applications. By using a tracer developed for the purpose we analyse in depth the internal behaviour of the system. The result of the analysis puts on display the adverse effect played by a non real-time scheduler on the performance of time-sensitive applications. Based on this analysis, we propose an alternative solution based on the CBS scheduler and prove its effectiveness by an extensive set of experiments on real hardware.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125945785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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