Quite often the modeling tools used in the development lifecycle of distributed real-time and embedded (DRE) systems are middleware-specific, where they elevate middleware artifacts, such as configuration options, to first class modeling entities. Unfortunately, this level of abstraction does not resolve the complex issues in middleware configuration process for QoS assurance. This paper describes GT-QMAP (graph transformation for QoS mapping) model-driven engineering toolchain that combines (1) domain-specific modeling, to simplify specifying the QoS requirements of DRE systems intuitively, and (2) model transformations, to automate the mapping of domain-specific QoS requirements to middleware-specific QoS configuration options. The paper evaluates the automation capabilities of GT-QMAP in the context of three DRE system case studies. The results indicate that on an average the modeling effort is reduced by over 75%. Further, the results also indicate that GT-QMAP provides significant benefits in terms of scalability and automation as DRE system QoS requirements evolve during its entire development lifecycle.
{"title":"Automated Middleware QoS Configuration Techniques for Distributed Real-time and Embedded Systems","authors":"A. Kavimandan, A. Gokhale","doi":"10.1109/RTAS.2008.29","DOIUrl":"https://doi.org/10.1109/RTAS.2008.29","url":null,"abstract":"Quite often the modeling tools used in the development lifecycle of distributed real-time and embedded (DRE) systems are middleware-specific, where they elevate middleware artifacts, such as configuration options, to first class modeling entities. Unfortunately, this level of abstraction does not resolve the complex issues in middleware configuration process for QoS assurance. This paper describes GT-QMAP (graph transformation for QoS mapping) model-driven engineering toolchain that combines (1) domain-specific modeling, to simplify specifying the QoS requirements of DRE systems intuitively, and (2) model transformations, to automate the mapping of domain-specific QoS requirements to middleware-specific QoS configuration options. The paper evaluates the automation capabilities of GT-QMAP in the context of three DRE system case studies. The results indicate that on an average the modeling effort is reduced by over 75%. Further, the results also indicate that GT-QMAP provides significant benefits in terms of scalability and automation as DRE system QoS requirements evolve during its entire development lifecycle.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126705196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The notion of resource reservation for obtaining real-time scheduling guarantees and enforcement of resource usage has gained strong support in recent years. However, much work on resource reservation has primarily focused on single-processor systems. In this paper, we propose the distributed resource kernel frame wo rk to deploy distributed real-time applications with end-to-end timing constraints, and to efficiently enforce and monitor their usage. Modern distributed real-time systems host multiple applications, where each application can span two or more processors. Timing bugs in one distributed application can affect the timing properties of other applications in the system. Our framework introduces the abstraction of a distributed resource container as an isolated virtual operating environment for a distributed real-time application. We have implemented this framework by extending our open-source single- node Linux/RK platform (R. Rajkumar et al., 1998). A deployment and monitoring tool called dMon is also provided. We evaluate the framework's ability to provide timing guarantees by stress-testing the system using the Distributed Hartstone benchmarks. An audio processing pipeline is then used to illustrate the temporal isolation support provided by the Distributed RK framework. The distributed container abstraction can also be extended in the future to support security and fault-tolerance attributes.
为了获得实时调度保证和强制执行资源使用而预留资源的概念近年来得到了强有力的支持。然而，很多关于资源预留的工作主要集中在单处理器系统上。本文提出了分布式资源内核框架，用于部署具有端到端时间约束的分布式实时应用程序，并有效地强制和监控其使用情况。现代分布式实时系统承载多个应用程序，其中每个应用程序可以跨越两个或更多处理器。一个分布式应用程序中的计时错误可能会影响系统中其他应用程序的计时属性。我们的框架将分布式资源容器抽象为分布式实时应用程序的隔离虚拟操作环境。我们通过扩展我们的开源单节点Linux/RK平台实现了这个框架(R. Rajkumar et al.， 1998)。还提供了一个名为dMon的部署和监视工具。我们通过使用分布式Hartstone基准对系统进行压力测试来评估框架提供时间保证的能力。然后使用音频处理管道来说明分布式RK框架提供的时间隔离支持。分布式容器抽象还可以在将来进行扩展，以支持安全性和容错属性。
{"title":"Distributed Resource Kernels: OS Support for End-To-End Resource Isolation","authors":"Karthik Lakshmanan, R. Rajkumar","doi":"10.1109/RTAS.2008.37","DOIUrl":"https://doi.org/10.1109/RTAS.2008.37","url":null,"abstract":"The notion of resource reservation for obtaining real-time scheduling guarantees and enforcement of resource usage has gained strong support in recent years. However, much work on resource reservation has primarily focused on single-processor systems. In this paper, we propose the distributed resource kernel frame wo rk to deploy distributed real-time applications with end-to-end timing constraints, and to efficiently enforce and monitor their usage. Modern distributed real-time systems host multiple applications, where each application can span two or more processors. Timing bugs in one distributed application can affect the timing properties of other applications in the system. Our framework introduces the abstraction of a distributed resource container as an isolated virtual operating environment for a distributed real-time application. We have implemented this framework by extending our open-source single- node Linux/RK platform (R. Rajkumar et al., 1998). A deployment and monitoring tool called dMon is also provided. We evaluate the framework's ability to provide timing guarantees by stress-testing the system using the Distributed Hartstone benchmarks. An audio processing pipeline is then used to illustrate the temporal isolation support provided by the Distributed RK framework. The distributed container abstraction can also be extended in the future to support security and fault-tolerance attributes.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122907448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Embedded systems are often subject to constraints that require determinism to ensure that task deadlines are met. Such systems are referred to as real-time systems. Schedulability analysis provides a firm basis to ensure that tasks meet their deadlines for which knowledge of worst-case execution time (WCET) bounds is a critical piece of information. Static timing analysis techniques are used to derive these WCET bounds. A limiting factor for designing realtime systems is the class of processors that can be used. Typically, modern, complex processor pipelines cannot be used in real-time systems design. Contemporary processors with their advanced architectural features, such as out-of-order execution, branch prediction, speculation, prefetching, etc., cannot be statically analyzed to obtain tight WCET bounds for tasks. This is caused by the non-determinism of these features, which surfaces in full only at runtime. In this paper, we introduce a new paradigm to perform timing analysis of tasks for real-time systems running on modern processor architectures. We propose minor enhancements to the processor architecture to enable this process. These features, on interaction with software modules, are able to obtain tight, accurate timing analysis results for modern processors. We also briefly present analysis techniques that, combined with our timing analysis methods, reduce the complexity of worst-case estimations for loops. To the best of our knowledge, this method of constant interactions between hardware and software to calculate WCET bounds for out-of-order processors is the first of its kind.
{"title":"Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions","authors":"Sibin Mohan, F. Mueller","doi":"10.1109/RTAS.2008.19","DOIUrl":"https://doi.org/10.1109/RTAS.2008.19","url":null,"abstract":"Embedded systems are often subject to constraints that require determinism to ensure that task deadlines are met. Such systems are referred to as real-time systems. Schedulability analysis provides a firm basis to ensure that tasks meet their deadlines for which knowledge of worst-case execution time (WCET) bounds is a critical piece of information. Static timing analysis techniques are used to derive these WCET bounds. A limiting factor for designing realtime systems is the class of processors that can be used. Typically, modern, complex processor pipelines cannot be used in real-time systems design. Contemporary processors with their advanced architectural features, such as out-of-order execution, branch prediction, speculation, prefetching, etc., cannot be statically analyzed to obtain tight WCET bounds for tasks. This is caused by the non-determinism of these features, which surfaces in full only at runtime. In this paper, we introduce a new paradigm to perform timing analysis of tasks for real-time systems running on modern processor architectures. We propose minor enhancements to the processor architecture to enable this process. These features, on interaction with software modules, are able to obtain tight, accurate timing analysis results for modern processors. We also briefly present analysis techniques that, combined with our timing analysis methods, reduce the complexity of worst-case estimations for loops. To the best of our knowledge, this method of constant interactions between hardware and software to calculate WCET bounds for out-of-order processors is the first of its kind.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116742068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper tackles the problem of defining an appropriate access control model for multi-user systems providing adaptive resource reservations to unprivileged users. Security requirements that need to be met by the system are identified, and an access control model satisfying them is proposed that also does not degrade the flexibility available on such systems due to the adaptive reservations framework. Also, the implementation of the proposed model within the AQuoSA architecture for Linux is briefly discussed.
{"title":"Access Control for Adaptive Reservations on Multi-User Systems","authors":"T. Cucinotta","doi":"10.1109/RTAS.2008.16","DOIUrl":"https://doi.org/10.1109/RTAS.2008.16","url":null,"abstract":"This paper tackles the problem of defining an appropriate access control model for multi-user systems providing adaptive resource reservations to unprivileged users. Security requirements that need to be met by the system are identified, and an access control model satisfying them is proposed that also does not degrade the flexibility available on such systems due to the adaptive reservations framework. Also, the implementation of the proposed model within the AQuoSA architecture for Linux is briefly discussed.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125422226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper provides four contributions to the study of optimization techniques for component-based distributed real-time and embedded (DRE) systems. First, we describe key challenges of designing component-based DRE systems and identify key sources of overhead in a typical component-based DRE system from the domain of shipboard computing. Second, we describe a class of optimization techniques applicable to the deployment of component-based DRE systems. Third, we describe the physical assembly mapper (PAM), which is a model-driven optimization tool that implements these techniques to reduce footprint. Fourth, we evaluate the benefits of these optimization techniques empirically and analyze the results. Our results indicate that the deployment-time optimization techniques in PAM provides significant benefits, such as 45% improvement in footprint, when compared to conventional component middleware technologies.
{"title":"Physical Assembly Mapper: A Model-Driven Optimization Tool for QoS-Enabled Component Middleware","authors":"K. Balasubramanian, D. Schmidt","doi":"10.1109/RTAS.2008.36","DOIUrl":"https://doi.org/10.1109/RTAS.2008.36","url":null,"abstract":"This paper provides four contributions to the study of optimization techniques for component-based distributed real-time and embedded (DRE) systems. First, we describe key challenges of designing component-based DRE systems and identify key sources of overhead in a typical component-based DRE system from the domain of shipboard computing. Second, we describe a class of optimization techniques applicable to the deployment of component-based DRE systems. Third, we describe the physical assembly mapper (PAM), which is a model-driven optimization tool that implements these techniques to reduce footprint. Fourth, we evaluate the benefits of these optimization techniques empirically and analyze the results. Our results indicate that the deployment-time optimization techniques in PAM provides significant benefits, such as 45% improvement in footprint, when compared to conventional component middleware technologies.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"os-29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127774025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Matthieu Lemerre, V. David, Christophe Aussaguès, G. Vidal-Naquet
Multiprocessor scheduling problems are hard because of the numerous constraints on valid schedules to take into account. This paper presents new schedule representations in order to overcome these difficulties, by allowing processors to be fractionally allocated. We prove that these representations are equivalent to the standard representations when preemptive scheduling is allowed. This allows the creation of scheduling algorithms and the study of feasibility in the simpler representations. We apply this method throughout the paper. Then, we use it to provide new simple solutions to the previously solved implicit-deadline periodic scheduling problem. We also tackle the more general problem of scheduling arbitrary time-triggered tasks, and thus in particular solve the open multiprocessor general periodic tasks scheduling problem. Contrary to previous solutions like the PFair class of algorithms, the proposed solution also works when processors have different speeds. We complete the method by providing an online schedule transformation algorithm, that allows the efficient handling of both time-triggered and event-triggered tasks, as well as the creation of online rate-based scheduling algorithms on multiprocessors.
{"title":"Equivalence between Schedule Representations: Theory and Applications","authors":"Matthieu Lemerre, V. David, Christophe Aussaguès, G. Vidal-Naquet","doi":"10.1109/RTAS.2008.17","DOIUrl":"https://doi.org/10.1109/RTAS.2008.17","url":null,"abstract":"Multiprocessor scheduling problems are hard because of the numerous constraints on valid schedules to take into account. This paper presents new schedule representations in order to overcome these difficulties, by allowing processors to be fractionally allocated. We prove that these representations are equivalent to the standard representations when preemptive scheduling is allowed. This allows the creation of scheduling algorithms and the study of feasibility in the simpler representations. We apply this method throughout the paper. Then, we use it to provide new simple solutions to the previously solved implicit-deadline periodic scheduling problem. We also tackle the more general problem of scheduling arbitrary time-triggered tasks, and thus in particular solve the open multiprocessor general periodic tasks scheduling problem. Contrary to previous solutions like the PFair class of algorithms, the proposed solution also works when processors have different speeds. We complete the method by providing an online schedule transformation algorithm, that allows the efficient handling of both time-triggered and event-triggered tasks, as well as the creation of online rate-based scheduling algorithms on multiprocessors.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124954101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Real-time schedulability theory requires a priori knowledge of the worst-case execution time (WCET) of every task in the system. Fundamental to the calculation of WCET is a scheduling policy that determines priorities among tasks. Such policies can be non-preemptive or preemptive. While the former reduces analysis complexity and overhead in implementation, the latter provides increased flexibility in terms of schedulability for higher utilizations of arbitrary task sets. In practice, tasks often have non-preemptive regions but are otherwise scheduled preemptively. To bound the WCET of tasks, architectural features have to be considered in the context of a scheduling scheme. In particular, preemption affects caches, which can be modeled by bounding the cache-related preemption delay (CRPD) of a task. In this paper, we propose a framework that provides safe and tight bounds of the data-cache related preemption delay (D-CRPD), the WCET and the worst-case response times, not just for homogeneous tasks under fully preemptive or fully non-preemptive systems, but for tasks with a non-preemptive region. By retaining the option of preemption where legal, task sets become schedulable that might otherwise not be. Yet, by requiring a region within a task to be non-preemptive, correctness is ensured in terms of arbitration of access to shared resources. Experimental results confirm an increase in schedulability of a task set with non- preemptive regions over an equivalent task set where only those tasks with non-preemptive regions are scheduled non- preemptively altogether. Quantitative results further indicate that D-CRPD bounds and response-time bounds comparable to task sets with fully non-preemptive tasks can be retained in the presence of short non-preemptive regions. To the best of our knowledge, this is the first framework that performs D-CRPD calculations in a system for tasks with a non-preemptive region.
{"title":"Bounding Worst-Case Response Time for Tasks with Non-Preemptive Regions","authors":"H. Ramaprasad, F. Mueller","doi":"10.1109/RTAS.2008.18","DOIUrl":"https://doi.org/10.1109/RTAS.2008.18","url":null,"abstract":"Real-time schedulability theory requires a priori knowledge of the worst-case execution time (WCET) of every task in the system. Fundamental to the calculation of WCET is a scheduling policy that determines priorities among tasks. Such policies can be non-preemptive or preemptive. While the former reduces analysis complexity and overhead in implementation, the latter provides increased flexibility in terms of schedulability for higher utilizations of arbitrary task sets. In practice, tasks often have non-preemptive regions but are otherwise scheduled preemptively. To bound the WCET of tasks, architectural features have to be considered in the context of a scheduling scheme. In particular, preemption affects caches, which can be modeled by bounding the cache-related preemption delay (CRPD) of a task. In this paper, we propose a framework that provides safe and tight bounds of the data-cache related preemption delay (D-CRPD), the WCET and the worst-case response times, not just for homogeneous tasks under fully preemptive or fully non-preemptive systems, but for tasks with a non-preemptive region. By retaining the option of preemption where legal, task sets become schedulable that might otherwise not be. Yet, by requiring a region within a task to be non-preemptive, correctness is ensured in terms of arbitration of access to shared resources. Experimental results confirm an increase in schedulability of a task set with non- preemptive regions over an equivalent task set where only those tasks with non-preemptive regions are scheduled non- preemptively altogether. Quantitative results further indicate that D-CRPD bounds and response-time bounds comparable to task sets with fully non-preemptive tasks can be retained in the presence of short non-preemptive regions. To the best of our knowledge, this is the first framework that performs D-CRPD calculations in a system for tasks with a non-preemptive region.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123341211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recent developments in the field of reconfigurable SoC devices (FPGAs) will enable the development of embedded systems where software tasks, running on a CPU, can coexist with hardware tasks. We devised a real-time computing architecture that can integrate hardware and software executions in a transparent manner, and can support real-time QoS adaptation by means of partial reconfiguration of modern FPGA devices. Tasks are allowed to migrate seamlessly from CPU to FPGA and vice versa to support dynamic QoS adaptation and cope with dynamic workloads. In this paper, we discuss the design and implementation of an on-chip infrastructure, OS extensions and task design methodology that enable hardware-software transparency in the presence of relocation. The overall architecture is suitable to schedule real-time workloads and we derive bounds on relocation overhead. Finally, we show the applicability of our design methodology on a concrete task design case.
{"title":"Hybrid Hardware-Software Architecture for Reconfigurable Real-Time Systems","authors":"R. Pellizzoni, M. Caccamo","doi":"10.1109/RTAS.2008.14","DOIUrl":"https://doi.org/10.1109/RTAS.2008.14","url":null,"abstract":"Recent developments in the field of reconfigurable SoC devices (FPGAs) will enable the development of embedded systems where software tasks, running on a CPU, can coexist with hardware tasks. We devised a real-time computing architecture that can integrate hardware and software executions in a transparent manner, and can support real-time QoS adaptation by means of partial reconfiguration of modern FPGA devices. Tasks are allowed to migrate seamlessly from CPU to FPGA and vice versa to support dynamic QoS adaptation and cope with dynamic workloads. In this paper, we discuss the design and implementation of an on-chip infrastructure, OS extensions and task design methodology that enable hardware-software transparency in the presence of relocation. The overall architecture is suitable to schedule real-time workloads and we derive bounds on relocation overhead. Finally, we show the applicability of our design methodology on a concrete task design case.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130532707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Kaldewey, T. Wong, Richard A. Golding, A. Povzner, S. Brandt, C. Maltzahn
Large- and small-scale storage systems frequently serve a mixture of workloads, an increasing number of which require some form of performance guarantee. Providing guaranteed disk performance - the equivalent of a "virtual disk" - is challenging because disk requests are non-preemptible and their execution times are stateful, partially non-deterministic, and can vary by orders of magnitude. Guaranteeing throughput, the standard measure of disk performance, requires worst-case I/O time assumptions orders of magnitude greater than average I/O times, with correspondingly low performance and poor control of the resource allocation. We show that disk time utilization- analogous to CPU utilization in CPU scheduling and the only fully provisionable aspect of disk performance - yields greater control, more efficient use of disk resources, and better isolation between request streams than bandwidth or I/O rate when used as the basis for disk reservation and scheduling.
{"title":"Virtualizing Disk Performance","authors":"T. Kaldewey, T. Wong, Richard A. Golding, A. Povzner, S. Brandt, C. Maltzahn","doi":"10.1109/RTAS.2008.31","DOIUrl":"https://doi.org/10.1109/RTAS.2008.31","url":null,"abstract":"Large- and small-scale storage systems frequently serve a mixture of workloads, an increasing number of which require some form of performance guarantee. Providing guaranteed disk performance - the equivalent of a \"virtual disk\" - is challenging because disk requests are non-preemptible and their execution times are stateful, partially non-deterministic, and can vary by orders of magnitude. Guaranteeing throughput, the standard measure of disk performance, requires worst-case I/O time assumptions orders of magnitude greater than average I/O times, with correspondingly low performance and poor control of the resource allocation. We show that disk time utilization- analogous to CPU utilization in CPU scheduling and the only fully provisionable aspect of disk performance - yields greater control, more efficient use of disk resources, and better isolation between request streams than bandwidth or I/O rate when used as the basis for disk reservation and scheduling.","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128867591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A hybrid scheduling algorithm is proposed, which integrates features of the fixed priority (FP) and earliest deadline first (EDF) scheduling policies. It is shown that this hybrid scheduling algorithm is a generalization of both FP and EDF, and tends to retain most of the desirable properties and features of both individual policies. An exact (i.e., necessary and sufficient) test is derived for the preemptive uniprocessor scheduling of resource- sharing sporadic task systems using this hybrid scheduling algorithm, with access to shared resources arbitrated using the stack resource policy (SRP).
{"title":"Hybrid-priority Scheduling of Resource-Sharing Sporadic Task Systems","authors":"Sanjoy Baruah, N. Fisher","doi":"10.1109/RTAS.2008.7","DOIUrl":"https://doi.org/10.1109/RTAS.2008.7","url":null,"abstract":"A hybrid scheduling algorithm is proposed, which integrates features of the fixed priority (FP) and earliest deadline first (EDF) scheduling policies. It is shown that this hybrid scheduling algorithm is a generalization of both FP and EDF, and tends to retain most of the desirable properties and features of both individual policies. An exact (i.e., necessary and sufficient) test is derived for the preemptive uniprocessor scheduling of resource- sharing sporadic task systems using this hybrid scheduling algorithm, with access to shared resources arbitrated using the stack resource policy (SRP).","PeriodicalId":130593,"journal":{"name":"2008 IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132101104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：