Modern Heterogeneous Systems-on-Chip (HeSoCs) rely on the accelerator-rich paradigm to achieve performance and energy efficiency through the on-chip integration of many application-specific functional units. However, the lack of a standard System-Level Design (SLD) methodology and the heterogeneity of the HW/SW components complicate the costly and time-consuming process of deploying accelerator-rich systems and applications. In this work, we present Richie, an open-source research SLD framework featuring a modular and composable RISC-V-based accelerator-rich platform and a support toolchain to automate the assembly and specialization of accelerator-rich HeSoCs. Richie exploits Field Programmable Gate Arrays (FPGAs) to deploy full-stack applications and explore the HeSoC design space. We show how Richie facilitates the investigation of platform non-idealities as the system scales up in accelerator count, identifying key design solutions and exploring platform costs, such as area usage. This yields comparable trade-off improvements over manually-optimized designs. Finally, we assess the methodology ease-of-use and extensibility by deploying a real-world workload and adding support for a Network-on-Chip (NoC) architecture.
{"title":"Richie: A Framework for Agile Design and Exploration of RISC-V-Based Accelerator-Rich Heterogeneous SoCs","authors":"Gianluca Bellocchi;Alessandro Capotondi;Luca Benini;Andrea Marongiu","doi":"10.1109/TPDS.2025.3624958","DOIUrl":"https://doi.org/10.1109/TPDS.2025.3624958","url":null,"abstract":"Modern Heterogeneous Systems-on-Chip (HeSoCs) rely on the accelerator-rich paradigm to achieve performance and energy efficiency through the on-chip integration of many application-specific functional units. However, the lack of a standard System-Level Design (SLD) methodology and the heterogeneity of the HW/SW components complicate the costly and time-consuming process of deploying accelerator-rich systems and applications. In this work, we present <sc>Richie</small>, an open-source research SLD framework featuring a modular and composable RISC-V-based accelerator-rich platform and a support toolchain to automate the assembly and specialization of accelerator-rich HeSoCs. <sc>Richie</small> exploits Field Programmable Gate Arrays (FPGAs) to deploy full-stack applications and explore the HeSoC design space. We show how <sc>Richie</small> facilitates the investigation of platform non-idealities as the system scales up in accelerator count, identifying key design solutions and exploring platform costs, such as area usage. This yields comparable trade-off improvements over manually-optimized designs. Finally, we assess the methodology ease-of-use and extensibility by deploying a real-world workload and adding support for a Network-on-Chip (NoC) architecture.","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"37 2","pages":"533-547"},"PeriodicalIF":6.0,"publicationDate":"2025-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145929626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-22DOI: 10.1109/TPDS.2025.3624289
Lei Xu;Haipeng Jia;Yunquan Zhang
Direction optimization determines whether to use Sparse Matrix-Sparse Vector Multiplication (SpMSpV) or Sparse Matrix-Dense Vector Multiplication (SpMV) based on the input vector’s sparsity at each iteration of Breadth-First Search (BFS), aiming to achieve the fastest graph traversal. Although prior work on direction optimization has achieved state-of-the-art performance on either CPUs or GPUs, it has not fully leveraged the capabilities of modern heterogeneous platforms. This is because SpMSpV/SpMV execution times on GPUs do not consistently outperform those on CPUs, particularly for SpMSpV. In response, this paper introduces CGA, a machine learning-based adaptive framework for BFS that optimally selects between CPU and GPU kernels, effectively Adapting to diverse real-world graphs, vectors, and computing platforms. Our contributions include a novel set of bucket-based SpMSpV algorithms that significantly enhance kernel performance in high-sparsity scenarios, along with a low-overhead decision tree model and reduced CPU-GPU data transfers. Experimental results show that our framework outperforms previous state-of-the-art methods, achieving up to a 4.91x speedup over CPU-only baseline and 3.27x speedup over GPU-only baseline.
{"title":"CGA: Accelerating BFS Through an Sparsity-Aware Adaptive Framework on Heterogeneous Platforms","authors":"Lei Xu;Haipeng Jia;Yunquan Zhang","doi":"10.1109/TPDS.2025.3624289","DOIUrl":"https://doi.org/10.1109/TPDS.2025.3624289","url":null,"abstract":"Direction optimization determines whether to use Sparse Matrix-Sparse Vector Multiplication (SpMSpV) or Sparse Matrix-Dense Vector Multiplication (SpMV) based on the input vector’s sparsity at each iteration of Breadth-First Search (BFS), aiming to achieve the fastest graph traversal. Although prior work on direction optimization has achieved state-of-the-art performance on either CPUs or GPUs, it has not fully leveraged the capabilities of modern heterogeneous platforms. This is because SpMSpV/SpMV execution times on GPUs do not consistently outperform those on CPUs, particularly for SpMSpV. In response, this paper introduces <bold><u>CGA</u></b>, a machine learning-based adaptive framework for BFS that optimally selects between <bold><u>C</u></b>PU and <bold><u>G</u></b>PU kernels, effectively <bold><u>A</u></b>dapting to diverse real-world graphs, vectors, and computing platforms. Our contributions include a novel set of bucket-based SpMSpV algorithms that significantly enhance kernel performance in high-sparsity scenarios, along with a low-overhead decision tree model and reduced CPU-GPU data transfers. Experimental results show that our framework outperforms previous state-of-the-art methods, achieving up to a 4.91x speedup over CPU-only baseline and 3.27x speedup over GPU-only baseline.","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"37 1","pages":"45-59"},"PeriodicalIF":6.0,"publicationDate":"2025-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145560808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a Parallel Hybrid Direct–Iterative Eigensolver for Hermitian Eigenvalue Problems without tridiagonalization, denoted by PHIDE, which combines direct and iterative methods. PHIDE first reduces a Hermitian matrix to banded form, then applies a spectrum slicing algorithm to the banded matrix, and finally computes the eigenvectors of the original matrix via backtransformation. Compared with conventional direct eigensolvers, PHIDE avoids tridiagonalization, which involves many memory-bound operations. In PHIDE, the banded eigenvalue problem is solved using the contour integral method implemented in FEAST, which may yield slightly lower accuracy than tridiagonalization-based approaches. For sequences of correlated Hermitian eigenvalue problems arising in density functional theory (DFT), PHIDE achieves an average speedup of $1.22times$ over the state-of-the-art direct solver in ELPA when using 1024 processes. Numerical experiments are conducted on dense Hermitian matrices from real applications as well as large sparse matrices from the SuiteSparse and ELSES collections.
{"title":"PHIDE: A Parallel Hybrid Direct–Iterative Eigensolver for Hermitian Eigenvalue Problems","authors":"Shengguo Li;Xinzhe Wu;Jose E. Roman;Ziyang Yuan;Ruibo Wang;Tiejun Li;Yi Xie;Bo Yang;Xuguang Chen","doi":"10.1109/TPDS.2025.3623188","DOIUrl":"https://doi.org/10.1109/TPDS.2025.3623188","url":null,"abstract":"In this paper, we propose a Parallel Hybrid Direct–Iterative Eigensolver for Hermitian Eigenvalue Problems without tridiagonalization, denoted by <monospace>PHIDE</monospace>, which combines direct and iterative methods. <monospace>PHIDE</monospace> first reduces a Hermitian matrix to banded form, then applies a spectrum slicing algorithm to the banded matrix, and finally computes the eigenvectors of the original matrix via backtransformation. Compared with conventional direct eigensolvers, <monospace>PHIDE</monospace> avoids tridiagonalization, which involves many memory-bound operations. In <monospace>PHIDE</monospace>, the banded eigenvalue problem is solved using the contour integral method implemented in FEAST, which may yield slightly lower accuracy than tridiagonalization-based approaches. For sequences of correlated Hermitian eigenvalue problems arising in density functional theory (DFT), <monospace>PHIDE</monospace> achieves an average speedup of <inline-formula><tex-math>$1.22times$</tex-math></inline-formula> over the state-of-the-art direct solver in ELPA when using 1024 processes. Numerical experiments are conducted on dense Hermitian matrices from real applications as well as large sparse matrices from the SuiteSparse and ELSES collections.","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"37 1","pages":"260-271"},"PeriodicalIF":6.0,"publicationDate":"2025-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145674786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-17DOI: 10.1109/TPDS.2025.3622691
Hengzhe Chi;Jihe Wang;Jinzhe Zhang;Danghui Wang
Point cloud processing is fundamental to applications such as autonomous driving, robotic navigation, and 3D reconstruction. Sampling is a crucial process in point cloud processing, but current sampling algorithms perform poorly when deployed on edge devices due to limited computational resources. This stems from three main reasons. First, the robustness of sampling is weak; even after denoising, residual noise remains, and existing edge sampling methods struggle to ignore noisy sampling nodes. Second, there’s a lack of structural sampling, popular algorithms like FPS tend to cover global information without considering special structures for focused sampling. Third, system efficiency is poor, traditional Farthest Point Sampling (FPS) and k-Nearest Neighbor Search (kNN) have terrible time and space complexities of $O(n^{2})$ with low parallelism, limiting system throughput, especially for large-scale point cloud processing. To bridge this gap, we propose a novel point cloud sampling algorithm based on parallel graph deconstruction named DPS (Deconstruction-based Point Cloud Sampling) and its multi-scale version DPS_MS with better denoising effect. First, during graph construction, we employ multi-scale graphing and add a preprocessing stage to filter out some noise nodes, reducing the noise rate. Second, in the sampling stage, we categorize important structures into edge nodes and dense nodes based on the reverse neighbor count of graph nodes, assigning them higher sampling weights to supplement structural information. Finally, we use a highly parallel locality-sensitive hashing algorithm to accelerate neighbor search and reduce memory consumption, we achieved data-level parallelization through the comprehensive parallelization of our algorithm. Through rigorous qualitative and quantitative validation on classification and segmentation tasks, we demonstrate that DPS, while maintaining accuracy, increases point cloud sampling speed by 22.08 times compared to the FPS algorithm, the implementation achieved a 75.1-fold improvement in system throughput and a maximum parallel speedup of 10.32x, and improves the Accuracy/FLOPs (M) ratio to 8.68.
点云处理是自动驾驶、机器人导航和3D重建等应用的基础。采样是点云处理中的一个关键过程，但由于计算资源有限，目前的采样算法在边缘设备上部署时表现不佳。这主要源于三个原因。首先，抽样的鲁棒性较弱；即使去噪后，残余噪声仍然存在，现有的边缘采样方法很难忽略有噪声的采样节点。其次，缺乏结构化采样，FPS等流行算法倾向于覆盖全局信息，而不考虑集中采样的特殊结构。第三，系统效率较差，传统的最远点采样（FPS）和k近邻搜索（kNN）的时间和空间复杂度为$ 0 (n^{2})$，并行性较低，限制了系统吞吐量，特别是对于大规模点云处理。为了弥补这一缺陷，我们提出了一种新的基于并行图解构的点云采样算法DPS （deconstruction -based point cloud sampling）及其去噪效果更好的多尺度版本DPS_MS。首先，在图的构建过程中，我们采用了多尺度图，并增加了预处理阶段来过滤掉一些噪声节点，降低了噪声率。其次，在采样阶段，根据图节点的反向邻居计数，将重要结构分为边缘节点和密集节点，赋予它们更高的采样权值，以补充结构信息。最后，我们使用高度并行的位置敏感散列算法来加速邻居搜索并减少内存消耗，通过对算法的全面并行化，实现了数据级并行化。通过对分类和分割任务进行严格的定性和定量验证，我们证明DPS算法在保持精度的同时，将点云采样速度提高了22.08倍，系统吞吐量提高了75.1倍，最大并行加速提高了10.32倍，并将精度/FLOPs (M)比提高到8.68。
{"title":"Accelerating Point Cloud Sampling by Parallel Structure Deconstruction","authors":"Hengzhe Chi;Jihe Wang;Jinzhe Zhang;Danghui Wang","doi":"10.1109/TPDS.2025.3622691","DOIUrl":"https://doi.org/10.1109/TPDS.2025.3622691","url":null,"abstract":"Point cloud processing is fundamental to applications such as autonomous driving, robotic navigation, and 3D reconstruction. Sampling is a crucial process in point cloud processing, but current sampling algorithms perform poorly when deployed on edge devices due to limited computational resources. This stems from three main reasons. First, the robustness of sampling is weak; even after denoising, residual noise remains, and existing edge sampling methods struggle to ignore noisy sampling nodes. Second, there’s a lack of structural sampling, popular algorithms like FPS tend to cover global information without considering special structures for focused sampling. Third, system efficiency is poor, traditional Farthest Point Sampling (FPS) and k-Nearest Neighbor Search (kNN) have terrible time and space complexities of <inline-formula><tex-math>$O(n^{2})$</tex-math></inline-formula> with low parallelism, limiting system throughput, especially for large-scale point cloud processing. To bridge this gap, we propose a novel point cloud sampling algorithm based on parallel graph deconstruction named DPS (Deconstruction-based Point Cloud Sampling) and its multi-scale version DPS_MS with better denoising effect. First, during graph construction, we employ multi-scale graphing and add a preprocessing stage to filter out some noise nodes, reducing the noise rate. Second, in the sampling stage, we categorize important structures into edge nodes and dense nodes based on the reverse neighbor count of graph nodes, assigning them higher sampling weights to supplement structural information. Finally, we use a highly parallel locality-sensitive hashing algorithm to accelerate neighbor search and reduce memory consumption, we achieved data-level parallelization through the comprehensive parallelization of our algorithm. Through rigorous qualitative and quantitative validation on classification and segmentation tasks, we demonstrate that DPS, while maintaining accuracy, increases point cloud sampling speed by 22.08 times compared to the FPS algorithm, the implementation achieved a 75.1-fold improvement in system throughput and a maximum parallel speedup of 10.32x, and improves the Accuracy/FLOPs (M) ratio to 8.68.","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"37 1","pages":"60-75"},"PeriodicalIF":6.0,"publicationDate":"2025-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145546979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-16DOI: 10.1109/TPDS.2025.3612151
Jesus Carretero;Javier García-Blas;Sameer Shende
{"title":"Guest Editorial: New Tools and Techniques for the Distributed Computing Continuum","authors":"Jesus Carretero;Javier García-Blas;Sameer Shende","doi":"10.1109/TPDS.2025.3612151","DOIUrl":"https://doi.org/10.1109/TPDS.2025.3612151","url":null,"abstract":"","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"36 12","pages":"2451-2454"},"PeriodicalIF":6.0,"publicationDate":"2025-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11205817","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145351993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Quantum many-body system can be solved with neural-network method. Nonetheless, the practical deployment of neural network quantum states (NNQS) in large-scale electronic structure analyses faces challenges, chiefly the high sampling cost and the complexity of local energy computations. To overcome these computational barriers, we present an innovative data-parallel NNQS-Transformer implementation. This implementation introduces a hybrid multi-layer workload balancing strategy that effectively addresses previous load imbalance issues while leveraging Julia’s portability to achieve targeted performance optimizations. Through extensive testing, we validate our approach using comprehensive quantum chemistry calculations on systems containing up to 120 spin orbitals, where previous methods were limited to much smaller scales. The implementation demonstrates exceptional scalability on the Sunway platform, achieving 92% strong scaling and 98% weak scaling efficiencies when utilizing up to 37 million processor cores. These significant performance improvements mark a crucial step toward making NNQS calculations practical for real-world quantum chemistry applications.
{"title":"Large-Scale Neural Network Quantum States Calculation for Quantum Chemistry on a New Sunway Supercomputer","authors":"Yangjun Wu;Wenhao Zhou;Li Shen;Hong Qian;Honghui Shang","doi":"10.1109/TPDS.2025.3620251","DOIUrl":"https://doi.org/10.1109/TPDS.2025.3620251","url":null,"abstract":"Quantum many-body system can be solved with neural-network method. Nonetheless, the practical deployment of neural network quantum states (NNQS) in large-scale electronic structure analyses faces challenges, chiefly the high sampling cost and the complexity of local energy computations. To overcome these computational barriers, we present an innovative data-parallel NNQS-Transformer implementation. This implementation introduces a hybrid multi-layer workload balancing strategy that effectively addresses previous load imbalance issues while leveraging Julia’s portability to achieve targeted performance optimizations. Through extensive testing, we validate our approach using comprehensive quantum chemistry calculations on systems containing up to 120 spin orbitals, where previous methods were limited to much smaller scales. The implementation demonstrates exceptional scalability on the Sunway platform, achieving 92% strong scaling and 98% weak scaling efficiencies when utilizing up to 37 million processor cores. These significant performance improvements mark a crucial step toward making NNQS calculations practical for real-world quantum chemistry applications.","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"36 12","pages":"2724-2732"},"PeriodicalIF":6.0,"publicationDate":"2025-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145352195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-14DOI: 10.1109/TPDS.2025.3621058
Jinru Chen;Jingke Tu;Lei Yang;Jiannong Cao
Edge AI applications enable edge devices to collaboratively learn a model via repeated model aggregations, aiming to utilize the distributed data on the devices for achieving high model accuracy. Existing methods either leverage a centralized server to directly aggregate the model updates from edge devices or need a central coordinator to group the edge devices for localized model aggregations. The centralized server (or coordinator) has a performance bottleneck and a high cost of collecting the global state needed for making the grouping decision in large-scale networks. In this paper, we propose an Autonomous Model Aggregation (AMA) method for large-scale decentralized learning on edge devices. Instead of needing a central coordinator to group the edge devices, AMA allows the edge devices to autonomously form groups using a highly efficient protocol, according to model functional similarity and historical grouping information. Moreover, AMA adopts a reinforcement learning approach to optimize the size of each group. Evaluation results on our self-developed edge computing testbed demonstrate that AMA outperforms the benchmark approaches by up to 20.71% in accuracy and reduced the convergence time by 75.58%.
{"title":"Autonomous Model Aggregation for Decentralized Learning on Edge Devices","authors":"Jinru Chen;Jingke Tu;Lei Yang;Jiannong Cao","doi":"10.1109/TPDS.2025.3621058","DOIUrl":"https://doi.org/10.1109/TPDS.2025.3621058","url":null,"abstract":"Edge AI applications enable edge devices to collaboratively learn a model via repeated model aggregations, aiming to utilize the distributed data on the devices for achieving high model accuracy. Existing methods either leverage a centralized server to directly aggregate the model updates from edge devices or need a central coordinator to group the edge devices for localized model aggregations. The centralized server (or coordinator) has a performance bottleneck and a high cost of collecting the global state needed for making the grouping decision in large-scale networks. In this paper, we propose an Autonomous Model Aggregation (AMA) method for large-scale decentralized learning on edge devices. Instead of needing a central coordinator to group the edge devices, AMA allows the edge devices to autonomously form groups using a highly efficient protocol, according to model functional similarity and historical grouping information. Moreover, AMA adopts a reinforcement learning approach to optimize the size of each group. Evaluation results on our self-developed edge computing testbed demonstrate that AMA outperforms the benchmark approaches by up to 20.71% in accuracy and reduced the convergence time by 75.58%.","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"37 1","pages":"15-28"},"PeriodicalIF":6.0,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145560809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-13DOI: 10.1109/TPDS.2025.3620384
Yanyan Li;Yu Chen;Zhiqian Xu;Yawen Wang;Hai Jiang;Keqin Li
Field Programmable Gate Arrays (FPGAs) are widely adopted in datacenters, where each FPGA is exclusively assigned to a task. This strategy results in significant resource waste and increased task rejections. To address this issue, placement algorithms adjust the locations and shapes of tasks based on Dynamic Partial Reconfiguration, which partitions an FPGA into multiple rectangular areas for sharing. However, existing schemes are designed for static task sets without adjustable shapes, incapable of optimizing the placement problem in datacenters. In this paper, FEditor is proposed as the first consecutive task placement scheme with adjustable shapes. It expands the planar FPGA models into three-dimensional ones with timestamps to accommodate consecutive tasks. To reduce the complexity of three-dimensional resource management, State Frames (SFs) are designed to compress the models losslessly. Three metrics and a nested heuristic algorithm are used for task placement. Experimental results demonstrate that FEditor has improved resource utilization by at least 19.8% and acceptance rate by at least 10% compared to the referenced algorithms. SFs and the nested algorithm accelerate the task placement by up to $10.26times$. The suitability of FEditor in datacenter environments is verified by its time efficiency trends.
{"title":"FEditor: Consecutive Task Placement With Adjustable Shapes Using FPGA State Frames","authors":"Yanyan Li;Yu Chen;Zhiqian Xu;Yawen Wang;Hai Jiang;Keqin Li","doi":"10.1109/TPDS.2025.3620384","DOIUrl":"https://doi.org/10.1109/TPDS.2025.3620384","url":null,"abstract":"Field Programmable Gate Arrays (FPGAs) are widely adopted in datacenters, where each FPGA is exclusively assigned to a task. This strategy results in significant resource waste and increased task rejections. To address this issue, placement algorithms adjust the locations and shapes of tasks based on Dynamic Partial Reconfiguration, which partitions an FPGA into multiple rectangular areas for sharing. However, existing schemes are designed for static task sets without adjustable shapes, incapable of optimizing the placement problem in datacenters. In this paper, FEditor is proposed as the first consecutive task placement scheme with adjustable shapes. It expands the planar FPGA models into three-dimensional ones with timestamps to accommodate consecutive tasks. To reduce the complexity of three-dimensional resource management, <i>State Frames</i> (<i>SFs</i>) are designed to compress the models losslessly. Three metrics and a nested heuristic algorithm are used for task placement. Experimental results demonstrate that FEditor has improved resource utilization by at least 19.8% and acceptance rate by at least 10% compared to the referenced algorithms. <i>SFs</i> and the nested algorithm accelerate the task placement by up to <inline-formula><tex-math>$10.26times$</tex-math></inline-formula>. The suitability of FEditor in datacenter environments is verified by its time efficiency trends.","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"37 1","pages":"1-14"},"PeriodicalIF":6.0,"publicationDate":"2025-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145546973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The rapid growth of AIoT devices brings huge demands for DNNs deployed on resource-constrained devices. However, the intensive computation and high memory footprint of DNN inference make it difficult for the AIoT devices to execute the inference tasks efficiently. In many widely deployed AIoT use cases, multiple local AIoT devices launch DNN inference tasks randomly. Although local collaborative inference has been proposed to accelerate DNN inference on local devices with limited resources, multitasking local collaborative inference, which is common in AIoT scenarios, has not been fully studied in previous works. We consider multitasking local client-server collaborative inference (MLCCI), which achieves efficient DNN inference by offloading the inference tasks from multiple AIoT devices to a more powerful local server with parallel pipelined execution streams through Wi-Fi 6. Our optimization goal is to minimize the mean end-to-end latency of MLCCI. Based on the experiment results, we identify three key challenges: high communication costs, high model initialization latency, and congestion delay brought by task interference. We analyze congestion delay in MLCCI and its stochastic fluctuations with queuing theory and propose Chorus, a high-performance adaptive MLCCI framework for AIoT devices, to minimize the mean end-to-end latency of MLCCI against stochastic congestion delay. Chorus generates communication-efficient model partitions with heuristic search, uses a prefetch-enabled two-level LRU cache to accelerate model initialization on the server, reduces congestion delay and its short-term fluctuations with execution stream allocation based on the cross-entropy method, and finally achieves efficient computation offloading with reinforcement learning. We established a system prototype, which statistically simulated many virtual clients with limited physical client devices to conduct performance evaluations, for Chorus with real devices. The evaluation results for various workload levels show that Chorus achieved an average of $1.4times$, $1.3times$, and $2times$ speedup over client-only inference, and server-only inference with LRU and MLSH, respectively.
{"title":"Chorus: Robust Multitasking Local Client-Server Collaborative Inference With Wi-Fi 6 for AIoT Against Stochastic Congestion Delay","authors":"Yuzhe Luo;Ji Qi;Ling Li;Ruizhi Chen;Xiaoyu Wu;Limin Cheng;Chen Zhao","doi":"10.1109/TPDS.2025.3619775","DOIUrl":"https://doi.org/10.1109/TPDS.2025.3619775","url":null,"abstract":"The rapid growth of AIoT devices brings huge demands for DNNs deployed on resource-constrained devices. However, the intensive computation and high memory footprint of DNN inference make it difficult for the AIoT devices to execute the inference tasks efficiently. In many widely deployed AIoT use cases, multiple local AIoT devices launch DNN inference tasks randomly. Although local collaborative inference has been proposed to accelerate DNN inference on local devices with limited resources, multitasking local collaborative inference, which is common in AIoT scenarios, has not been fully studied in previous works. We consider multitasking local client-server collaborative inference (MLCCI), which achieves efficient DNN inference by offloading the inference tasks from multiple AIoT devices to a more powerful local server with parallel pipelined execution streams through Wi-Fi 6. Our optimization goal is to minimize the mean end-to-end latency of MLCCI. Based on the experiment results, we identify three key challenges: high communication costs, high model initialization latency, and congestion delay brought by task interference. We analyze congestion delay in MLCCI and its stochastic fluctuations with queuing theory and propose Chorus, a high-performance adaptive MLCCI framework for AIoT devices, to minimize the mean end-to-end latency of MLCCI against stochastic congestion delay. Chorus generates communication-efficient model partitions with heuristic search, uses a prefetch-enabled two-level LRU cache to accelerate model initialization on the server, reduces congestion delay and its short-term fluctuations with execution stream allocation based on the cross-entropy method, and finally achieves efficient computation offloading with reinforcement learning. We established a system prototype, which statistically simulated many virtual clients with limited physical client devices to conduct performance evaluations, for Chorus with real devices. The evaluation results for various workload levels show that Chorus achieved an average of <inline-formula><tex-math>$1.4times$</tex-math></inline-formula>, <inline-formula><tex-math>$1.3times$</tex-math></inline-formula>, and <inline-formula><tex-math>$2times$</tex-math></inline-formula> speedup over client-only inference, and server-only inference with LRU and MLSH, respectively.","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"36 12","pages":"2706-2723"},"PeriodicalIF":6.0,"publicationDate":"2025-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145352076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
NVMe SSDs have become mainstream storage devices thanks to their compact size and ultra-low latency. It has been observed that the impact of interference among all concurrently running streams (i.e., I/O workloads) on their overall responsiveness differs significantly, thus leading to unfairness. The intensity and access locality of streams are the primary factors contributing to interference. A small-sized data cache is commonly equipped in the front-end of SSDs to improve I/O performance and extend the device’s lifetime. The degree of parallelism at this level, however, is limited compared to that of the SSD back end, which consists of multiple channels, chips, and planes. Therefore, the impact of interference can be more significant at the data cache level. In this paper, we propose a cache division management scheme that not only contributes to fairness but also boosts I/O responsiveness across all workloads in NVMe SSDs. Specifically, our proposal supports long-term data cache partitioning and short-term cache adjustment with global sharing, ensuring better fairness and further enhancing cache utilization efficiency in multi-stream scenarios. Trace-driven simulation experiments show that our proposal improves fairness by an average of 66.0% and reduces overall I/O response time by between 3.8% and 18.0%, compared to existing cache management schemes for NVMe SSDs.
{"title":"Cache Partition Management for Improving Fairness and I/O Responsiveness in NVMe SSDs","authors":"Jiaojiao Wu;Fan Yang;Zhibing Sha;Li Cai;Zhigang Cai;Balazs Gerofi;Yuanquan Shi;Jianwei Liao","doi":"10.1109/TPDS.2025.3619866","DOIUrl":"https://doi.org/10.1109/TPDS.2025.3619866","url":null,"abstract":"NVMe SSDs have become mainstream storage devices thanks to their compact size and ultra-low latency. It has been observed that the impact of interference among all concurrently running streams (i.e., I/O workloads) on their overall responsiveness differs significantly, thus leading to unfairness. The intensity and access locality of streams are the primary factors contributing to interference. A small-sized data cache is commonly equipped in the front-end of SSDs to improve I/O performance and extend the device’s lifetime. The degree of parallelism at this level, however, is limited compared to that of the SSD back end, which consists of multiple channels, chips, and planes. Therefore, the impact of interference can be more significant at the data cache level. In this paper, we propose a cache division management scheme that not only contributes to fairness but also boosts I/O responsiveness across all workloads in NVMe SSDs. Specifically, our proposal supports long-term data cache partitioning and short-term cache adjustment with global sharing, ensuring better fairness and further enhancing cache utilization efficiency in multi-stream scenarios. Trace-driven simulation experiments show that our proposal improves fairness by an average of <monospace>66.0</monospace>% and reduces overall I/O response time by between <monospace>3.8</monospace>% and <monospace>18.0</monospace>%, compared to existing cache management schemes for NVMe SSDs.","PeriodicalId":13257,"journal":{"name":"IEEE Transactions on Parallel and Distributed Systems","volume":"37 1","pages":"122-136"},"PeriodicalIF":6.0,"publicationDate":"2025-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145546986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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