J. Hennessy, N. Jouppi, S. Przybylski, C. Rowen, T. Gross, F. Baskett, John T. Gill
MIPS is a new single chip VLSI microprocessor. It attempts to achieve high performance with the use of a simplified instruction set, similar to those found in microengines. The processor is a fast pipelined engine without pipeline interlocks. Software solutions to several traditional hardware problems, such as providing pipeline interlocks, are used.
{"title":"MIPS: A microprocessor architecture","authors":"J. Hennessy, N. Jouppi, S. Przybylski, C. Rowen, T. Gross, F. Baskett, John T. Gill","doi":"10.1145/1014194.800930","DOIUrl":"https://doi.org/10.1145/1014194.800930","url":null,"abstract":"MIPS is a new single chip VLSI microprocessor. It attempts to achieve high performance with the use of a simplified instruction set, similar to those found in microengines. The processor is a fast pipelined engine without pipeline interlocks. Software solutions to several traditional hardware problems, such as providing pipeline interlocks, are used.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124904876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The designer of an optimizing compiler must concern himself with the order in which optimization phases are performed; a pair of phases may be interdependent in the sense that each phase could benefit from information produced by the other. In a compiler for a horizontal target architecture, one such phase-ordering problem occurs between code-generation and compaction. Presented here is an overview of a research effort at Carnegie-Mellon University which has examined solutions to this problem. One aspect of the code generation problem-that of generating constants “intelligently”-is discussed in detail. A technique, called constant-unfolding, is described that can be used to produce code sequences that generate constants in “unusual” ways during execution; such code sequences can lead to more compact code when the literal field of the microinstruction is a “bottleneck”.
{"title":"Phase coupling and constant generation in an optimizing microcode compiler","authors":"S. Vegdahl","doi":"10.1145/1014194.800942","DOIUrl":"https://doi.org/10.1145/1014194.800942","url":null,"abstract":"The designer of an optimizing compiler must concern himself with the order in which optimization phases are performed; a pair of phases may be interdependent in the sense that each phase could benefit from information produced by the other. In a compiler for a horizontal target architecture, one such phase-ordering problem occurs between code-generation and compaction. Presented here is an overview of a research effort at Carnegie-Mellon University which has examined solutions to this problem. One aspect of the code generation problem-that of generating constants “intelligently”-is discussed in detail. A technique, called constant-unfolding, is described that can be used to produce code sequences that generate constants in “unusual” ways during execution; such code sequences can lead to more compact code when the literal field of the microinstruction is a “bottleneck”.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125154196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kazutoshi Takahashi, E. Takahashi, T. Bitoh, T. Aoyama, A. Yamada
A general purpose, total system MDS1,2 (Microprogramming Design-support System) has been developed to hasten the introduction of various kinds of firmware over the widest possible range of computer from the largest to the smallest (microcomputer). Not only many types of assembly language but also machine dependent high-level languages can be used and physical address assignment can be performed automatically with MDS. This paper describes an overview of MDS, the design approach to the high-level languages, and three examples which have been developed.
{"title":"MDS: An improved total system for firmware development","authors":"Kazutoshi Takahashi, E. Takahashi, T. Bitoh, T. Aoyama, A. Yamada","doi":"10.1145/1014194.800934","DOIUrl":"https://doi.org/10.1145/1014194.800934","url":null,"abstract":"A general purpose, total system MDS1,2 (Microprogramming Design-support System) has been developed to hasten the introduction of various kinds of firmware over the widest possible range of computer from the largest to the smallest (microcomputer).\u0000 Not only many types of assembly language but also machine dependent high-level languages can be used and physical address assignment can be performed automatically with MDS.\u0000 This paper describes an overview of MDS, the design approach to the high-level languages, and three examples which have been developed.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129255956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Four schemes for the design of concurrently testable microprogrammed control units are presented. In Schemes 1 and 2 the concept of path signatures is used for detection of malfunctions in the control unit. Two different methods for computation of signatures are given. In Schemes 3 and 4, a check-symbol is assigned to each microinstruction and the integrity of these check-symbols is checked concurrently. A deterministic approach is used for generation of check-symbols in Scheme 4. A comparative study of these schemes is done with respect to storage and time overhead, error coverage, and implementation complexity.
{"title":"Design of concurrently testable microprogrammed control units","authors":"M. Namjoo","doi":"10.1145/1014194.800947","DOIUrl":"https://doi.org/10.1145/1014194.800947","url":null,"abstract":"Four schemes for the design of concurrently testable microprogrammed control units are presented. In Schemes 1 and 2 the concept of path signatures is used for detection of malfunctions in the control unit. Two different methods for computation of signatures are given. In Schemes 3 and 4, a check-symbol is assigned to each microinstruction and the integrity of these check-symbols is checked concurrently. A deterministic approach is used for generation of check-symbols in Scheme 4. A comparative study of these schemes is done with respect to storage and time overhead, error coverage, and implementation complexity.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127744095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A microarchitecture designed for high performance, control store efficiency, and ease of microprogramming is described. These objectives were achieved by orienting the design to support the requirements of a powerful higher-level-like microprogramming language. 1, 2 The language is machine dependent and achieves efficiency of execution and space, as well as compactness of expression through relatively powerful constructs such as partial field operations and by permitting appropriate suboptions to be coupled with each of the various constructs. The relative utility of the various constructs is indicated by a statistical analysis of an actual emulator.
{"title":"A microprogramming language-directed microarchitecture","authors":"Ronald M. Guffin","doi":"10.1145/1014194.800933","DOIUrl":"https://doi.org/10.1145/1014194.800933","url":null,"abstract":"A microarchitecture designed for high performance, control store efficiency, and ease of microprogramming is described. These objectives were achieved by orienting the design to support the requirements of a powerful higher-level-like microprogramming language. 1, 2 The language is machine dependent and achieves efficiency of execution and space, as well as compactness of expression through relatively powerful constructs such as partial field operations and by permitting appropriate suboptions to be coupled with each of the various constructs. The relative utility of the various constructs is indicated by a statistical analysis of an actual emulator.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132587987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes PACE (Product Assurance Code Evaluation) System, a tool for evaluating microprograms. PACE incorporates both static analysis and dynamic analysis capabilities and it provides features that enable systematic and comprehensive evaluations of large-scale microcoded systems. The PACE static analysis capability performs a control flow analysis of the code being evaluated, reports various anomalous program constructs, and generates a program flow graph that is subsequently employed by PACE's dynamic analysis procedures. The PACE dynamic analysis capability uses encoded execution trace data to produce microcode test-coverage reports and formatted code-execution traces. The dynamic analysis capability provides quantitative code execution coverage data that enables an assessment of testing thoroughness and is useful in the identification of effective regression test cases.
{"title":"PACE - a microprogram evaluation system","authors":"R. Skibbe","doi":"10.1145/1014194.800948","DOIUrl":"https://doi.org/10.1145/1014194.800948","url":null,"abstract":"This paper describes PACE (Product Assurance Code Evaluation) System, a tool for evaluating microprograms. PACE incorporates both static analysis and dynamic analysis capabilities and it provides features that enable systematic and comprehensive evaluations of large-scale microcoded systems.\u0000 The PACE static analysis capability performs a control flow analysis of the code being evaluated, reports various anomalous program constructs, and generates a program flow graph that is subsequently employed by PACE's dynamic analysis procedures.\u0000 The PACE dynamic analysis capability uses encoded execution trace data to produce microcode test-coverage reports and formatted code-execution traces. The dynamic analysis capability provides quantitative code execution coverage data that enables an assessment of testing thoroughness and is useful in the identification of effective regression test cases.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123825978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This keynote address contains a brief account of the arguements being advanced in favor of reduced instruction sets. These arguements have relevance both to single chip computers and to larger computers. Some comments are made on instruction set design from a compiler writer's point of view, and on the advantages to be gained from regarding the design of an instruction set and the code generator of the compiler as a single task.
{"title":"Keynote address - the processor instruction set","authors":"M. Wilkes","doi":"10.1145/1014194.800928","DOIUrl":"https://doi.org/10.1145/1014194.800928","url":null,"abstract":"This keynote address contains a brief account of the arguements being advanced in favor of reduced instruction sets. These arguements have relevance both to single chip computers and to larger computers. Some comments are made on instruction set design from a compiler writer's point of view, and on the advantages to be gained from regarding the design of an instruction set and the code generator of the compiler as a single task.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"35 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114127709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the possible effects of VLSI technology on the design and development process of microprogrammed systems are explored. The function architectures of future microprogrammed VLSI systems are expected to be very complex, and most of them will be implemented as heterogeneous multiprocessors with each processor being microprogrammed to perform specific tasks. Current microprogrammed system design methodologies are examined and are shown to be inadequate. A new design methodology employing a synthetic approach for developing microprogrammed systems is proposed.
{"title":"A VLSI view of microprogrammed system design","authors":"Tientien Li","doi":"10.1145/1014194.800939","DOIUrl":"https://doi.org/10.1145/1014194.800939","url":null,"abstract":"In this paper, the possible effects of VLSI technology on the design and development process of microprogrammed systems are explored. The function architectures of future microprogrammed VLSI systems are expected to be very complex, and most of them will be implemented as heterogeneous multiprocessors with each processor being microprogrammed to perform specific tasks. Current microprogrammed system design methodologies are examined and are shown to be inadequate. A new design methodology employing a synthetic approach for developing microprogrammed systems is proposed.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127733570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A procedure is outlined for describing the microarchitecture of a horizontal processor such that a retargetable Microprogram Compiler System can incorporate the description to generate microcode for that processor. The microarchitecture description methodology is an organized approach to defining a machine's microinstruction formats, fields, and microorders; its hardware elements; its microoperation usage rules; and its behavioral rules. To a large extent, the description procedure can be performed interactively. The link between the microarchitecture description and the microprogram compiler, termed the instruction set interpretation mechanism, is also described. Preliminary application of the microarchitecture description methodology to several real processors has shown that, despite some problems, the procedure shows promise for significantly reducing the time required to retarget a microprogram compiler.
{"title":"Microarchitecture description techniques","authors":"J. L. Gieser, Robert J. Sheraga","doi":"10.1145/1014194.800931","DOIUrl":"https://doi.org/10.1145/1014194.800931","url":null,"abstract":"A procedure is outlined for describing the microarchitecture of a horizontal processor such that a retargetable Microprogram Compiler System can incorporate the description to generate microcode for that processor. The microarchitecture description methodology is an organized approach to defining a machine's microinstruction formats, fields, and microorders; its hardware elements; its microoperation usage rules; and its behavioral rules. To a large extent, the description procedure can be performed interactively. The link between the microarchitecture description and the microprogram compiler, termed the instruction set interpretation mechanism, is also described. Preliminary application of the microarchitecture description methodology to several real processors has shown that, despite some problems, the procedure shows promise for significantly reducing the time required to retarget a microprogram compiler.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125499999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As part of a research effort in parallel processor architecture and programming, the Ultracomputer group at New York University has done extensive simulation of parallel programs. To speed up these simulations, we have developed a parallel processor emulator, using the microprogrammable PUMA Computer System previously designed and built at NYU.
{"title":"Emulating an MIMD architecture","authors":"B. Su, R. Grishman","doi":"10.1145/1014194.800949","DOIUrl":"https://doi.org/10.1145/1014194.800949","url":null,"abstract":"As part of a research effort in parallel processor architecture and programming, the Ultracomputer group at New York University has done extensive simulation of parallel programs. To speed up these simulations, we have developed a parallel processor emulator, using the microprogrammable PUMA Computer System previously designed and built at NYU.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"18 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125616394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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