Pub Date : 2000-09-05DOI: 10.1109/EURMIC.2000.874405
H. Wedde, J. Siepmann
In the multimedia field, metadata are becoming increasingly important for efficiently cataloguing the abundant flood of information. (Metadata are data on information structures.) The number of electronic data files made accessible by metadata increases rapidly, however at the present retrieving textual, audio, video and/or mixed data files through metadata is definitely restricted. In particular, there is only a limited number of metadata formats at hand. Nevertheless, within the framework of testbeds, some efforts have been made not only to develop retrieval systems adjusted to the respective field of application, but also to unite several metadata formats into one system in order to obtain better search results. This paper describes specifications for developing an attribute service which, as part of the "Dragon Slayer" distributed file system, is intended to offer a uniform platform for different metadata formats, and to offer efficient information metadata retrieval. Via the interface provided by the Dragon Slayer file system, the user can assign metadata to files and reference them via these metadata. For each metadata format used, an external meta module is incorporated into the file system which, depending on its format, manages and searches for metadata in a database, according to their format.
{"title":"A universal framework for managing metadata in the distributed Dragon Slayer system","authors":"H. Wedde, J. Siepmann","doi":"10.1109/EURMIC.2000.874405","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874405","url":null,"abstract":"In the multimedia field, metadata are becoming increasingly important for efficiently cataloguing the abundant flood of information. (Metadata are data on information structures.) The number of electronic data files made accessible by metadata increases rapidly, however at the present retrieving textual, audio, video and/or mixed data files through metadata is definitely restricted. In particular, there is only a limited number of metadata formats at hand. Nevertheless, within the framework of testbeds, some efforts have been made not only to develop retrieval systems adjusted to the respective field of application, but also to unite several metadata formats into one system in order to obtain better search results. This paper describes specifications for developing an attribute service which, as part of the \"Dragon Slayer\" distributed file system, is intended to offer a uniform platform for different metadata formats, and to offer efficient information metadata retrieval. Via the interface provided by the Dragon Slayer file system, the user can assign metadata to files and reference them via these metadata. For each metadata format used, an external meta module is incorporated into the file system which, depending on its format, manages and searches for metadata in a database, according to their format.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131902871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-05DOI: 10.1109/EURMIC.2000.874640
K. Wiatr, E. Jamro
Investigates different architectures implementing bit-parallel constant-coefficient multiplication in FPGA structures. First, multiplierless multiplication (MM) architectures employing canonic sign digit (CSD) and sub-structure sharing methods are addressed, and a novel algorithm for the conversion from two's-complement to CSD representation is presented. In the second part of this paper, lookup table-based multiplication (LM) is investigated. Correspondingly, the usage of different memory modules and finding the optimal combination of the memory and adders are considered. The LM architecture also considers reduction of the address width for each memory cell and the possibility of memory sub-structure sharing. Finally, implementation results for the Xilinx XC4000 and Virtex families are presented. As a result, MM generally surpasses the LM architecture. However, the actual choice between these two architectures is coefficient- and input parameter-dependent.
{"title":"Constant coefficient multiplication in FPGA structures","authors":"K. Wiatr, E. Jamro","doi":"10.1109/EURMIC.2000.874640","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874640","url":null,"abstract":"Investigates different architectures implementing bit-parallel constant-coefficient multiplication in FPGA structures. First, multiplierless multiplication (MM) architectures employing canonic sign digit (CSD) and sub-structure sharing methods are addressed, and a novel algorithm for the conversion from two's-complement to CSD representation is presented. In the second part of this paper, lookup table-based multiplication (LM) is investigated. Correspondingly, the usage of different memory modules and finding the optimal combination of the memory and adders are considered. The LM architecture also considers reduction of the address width for each memory cell and the possibility of memory sub-structure sharing. Finally, implementation results for the Xilinx XC4000 and Virtex families are presented. As a result, MM generally surpasses the LM architecture. However, the actual choice between these two architectures is coefficient- and input parameter-dependent.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132274234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-05DOI: 10.1109/EURMIC.2000.874398
B. McClelland
While there has been a great deal of activity in the exploration of learning situations, especially with the development of computer aided learning, the introduction of holistic views of learning situations can be useful. In particular, one current approach is that of supported Web based learning systems to complement traditional teaching. This paper focuses on recent work at LBS on one undergraduate module, which with one other has served to provide a rationale for a Web-based teaching, learning and support environment for academic staff and students. The approach has enabled us to explore module/programme support development possibilities on the Web from academic, quality and commercial perspectives as well as the cybernetic and evolutionary nature of learning. It has also enabled us to explore student attitudes and perceptions to the technology, the learning strategies adopted by students, and relate it to student learning styles and approaches to study. The emphases in studying this system are appropriateness in terms of pedagogy, quality of content and presentation, technology fit. There is appeal to students, flexibility as a delivery platform, cost benefits and external commercial possibilities. The development process for academics has been mapped and cost benefits of the Web site recorded, in order to develop the strategy of a Web supported teaching and learning environment, coupled with a suitable support mechanism, for staff and students at Liverpool Business School.
{"title":"Digital teaching, learning and program supports: an examination of developments for students in higher education","authors":"B. McClelland","doi":"10.1109/EURMIC.2000.874398","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874398","url":null,"abstract":"While there has been a great deal of activity in the exploration of learning situations, especially with the development of computer aided learning, the introduction of holistic views of learning situations can be useful. In particular, one current approach is that of supported Web based learning systems to complement traditional teaching. This paper focuses on recent work at LBS on one undergraduate module, which with one other has served to provide a rationale for a Web-based teaching, learning and support environment for academic staff and students. The approach has enabled us to explore module/programme support development possibilities on the Web from academic, quality and commercial perspectives as well as the cybernetic and evolutionary nature of learning. It has also enabled us to explore student attitudes and perceptions to the technology, the learning strategies adopted by students, and relate it to student learning styles and approaches to study. The emphases in studying this system are appropriateness in terms of pedagogy, quality of content and presentation, technology fit. There is appeal to students, flexibility as a delivery platform, cost benefits and external commercial possibilities. The development process for academics has been mapped and cost benefits of the Web site recorded, in order to develop the strategy of a Web supported teaching and learning environment, coupled with a suitable support mechanism, for staff and students at Liverpool Business School.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134449520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-05DOI: 10.1109/EURMIC.2000.874419
I. Kovalev, K. Großpietsch
The paper presents an approach to systematically derive the optimal structure of fault-tolerant software for safety-critical control processes, with respect to resource requirements and cost- and timing constraints. For the modelling of the control process, a graph model description is used; basic static distributed scheduling and allocation decisions for the tasks are performed and task computation times are defined. Adaptive optimization techniques are used to derive the optimal solution for the given requirements. The application of the method in practice is illustrated by the example of a software system for spacecraft control.
{"title":"Deriving the optimal structure of N-version software under resource requirements and cost/timing constraints","authors":"I. Kovalev, K. Großpietsch","doi":"10.1109/EURMIC.2000.874419","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874419","url":null,"abstract":"The paper presents an approach to systematically derive the optimal structure of fault-tolerant software for safety-critical control processes, with respect to resource requirements and cost- and timing constraints. For the modelling of the control process, a graph model description is used; basic static distributed scheduling and allocation decisions for the tasks are performed and task computation times are defined. Adaptive optimization techniques are used to derive the optimal solution for the given requirements. The application of the method in practice is illustrated by the example of a software system for spacecraft control.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130358558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-05DOI: 10.1109/EURMIC.2000.874440
Onur Demirörs, Özkan Yildiz, A. S. Güceglioglu
Process improvement in the manufacturing sector traditionally starts with calculation of: cost of quality. The cost of quality calculation enables identification of the weakest links of the process that requires immediate attention, prioritization of improvement tasks and establishment of a baseline for these tasks. In the software field, process improvement initiatives usually leave out the cost of quality calculations. The authors report on a case study concerning the utilization of cost of software quality as an initiator for software process improvement in a public software development organization.
{"title":"Using cost of software quality for a process improvement initiative","authors":"Onur Demirörs, Özkan Yildiz, A. S. Güceglioglu","doi":"10.1109/EURMIC.2000.874440","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874440","url":null,"abstract":"Process improvement in the manufacturing sector traditionally starts with calculation of: cost of quality. The cost of quality calculation enables identification of the weakest links of the process that requires immediate attention, prioritization of improvement tasks and establishment of a baseline for these tasks. In the software field, process improvement initiatives usually leave out the cost of quality calculations. The authors report on a case study concerning the utilization of cost of software quality as an initiator for software process improvement in a public software development organization.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115239721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-05DOI: 10.1109/EURMIC.2000.874627
D. Kania
The objective of the technology mapping method presented in this paper is to cover a multiple-output function by a minimal number of PAL (programmable array logic) based logic blocks included in CPLDs (complex programmable logic devices). According to this method, product terms included in a logic block can be shared by several functions. The developed algorithms, implemented within the PALDec system, have been used for partitioning the benchmark circuits due to implementation by means of the PAL-based logic blocks with the restricted number of terms. The results are compared to the classical technology mapping method and synthesis of benchmarks executed by means of MACHXL and MAX+PLUS II software.
{"title":"A technology mapping algorithm for PAL-based devices using multi-output function graphs","authors":"D. Kania","doi":"10.1109/EURMIC.2000.874627","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874627","url":null,"abstract":"The objective of the technology mapping method presented in this paper is to cover a multiple-output function by a minimal number of PAL (programmable array logic) based logic blocks included in CPLDs (complex programmable logic devices). According to this method, product terms included in a logic block can be shared by several functions. The developed algorithms, implemented within the PALDec system, have been used for partitioning the benchmark circuits due to implementation by means of the PAL-based logic blocks with the restricted number of terms. The results are compared to the classical technology mapping method and synthesis of benchmarks executed by means of MACHXL and MAX+PLUS II software.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115770810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-05DOI: 10.1109/EURMIC.2000.874634
J. Hidalgo, J. Lanchares, R. Hermida
One of the most important and difficult tasks in multi-FPGA systems design is partitioning. The main problems are related to the I/O pins and logic capacity of FPGAs. The number of pins available is a critical problem, because FPGA devices have such a reduced number of them compared with their logic capacity. In addition we must reserve some of the pins to interconnect parts of the circuit placed on non-adjacent FPGAs. Most of the previous works have been adapted from other VLSI areas, and hence, they disregard the specific features of these kind of circuit. A new method for solving the partitioning and placement problem in multi-FPGA systems is presented. We use graph theory to describe the circuit, then a classical genetic algorithm (GA) is applied with a problem-specific encoding. The algorithm preserves the original structure of the circuit and by means of a fuzzy technique it evaluates the I/O-pins consumption due to direct and indirect connections between FPGAs. We have used the Partitioning93 benchmarks described with the Xilinx Netlist Format (XNF). The results obtained show how genetic algorithms are capable of accomplishing successfully the partitioning and placement tasks while respecting the board constraints.
在多fpga系统设计中，最重要也是最困难的任务之一就是分区。主要问题与fpga的I/O引脚和逻辑容量有关。可用引脚的数量是一个关键问题，因为FPGA设备的引脚数量与其逻辑容量相比是如此之少。此外，我们必须保留一些引脚来连接放置在非相邻fpga上的电路部分。以前的大部分工作都是改编自其他VLSI领域，因此，他们忽视了这类电路的具体特征。提出了一种解决多fpga系统中划分与放置问题的新方法。首先利用图论对电路进行描述，然后采用经典的遗传算法对问题进行编码。该算法保留了电路的原始结构，并通过模糊技术评估fpga之间直接和间接连接导致的I/ o引脚消耗。我们使用了Xilinx Netlist Format (XNF)描述的Partitioning93基准测试。结果表明，遗传算法能够成功地完成分区和放置任务，同时尊重板的约束。
{"title":"Partitioning and placement for multi-FPGA systems using genetic algorithms","authors":"J. Hidalgo, J. Lanchares, R. Hermida","doi":"10.1109/EURMIC.2000.874634","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874634","url":null,"abstract":"One of the most important and difficult tasks in multi-FPGA systems design is partitioning. The main problems are related to the I/O pins and logic capacity of FPGAs. The number of pins available is a critical problem, because FPGA devices have such a reduced number of them compared with their logic capacity. In addition we must reserve some of the pins to interconnect parts of the circuit placed on non-adjacent FPGAs. Most of the previous works have been adapted from other VLSI areas, and hence, they disregard the specific features of these kind of circuit. A new method for solving the partitioning and placement problem in multi-FPGA systems is presented. We use graph theory to describe the circuit, then a classical genetic algorithm (GA) is applied with a problem-specific encoding. The algorithm preserves the original structure of the circuit and by means of a fuzzy technique it evaluates the I/O-pins consumption due to direct and indirect connections between FPGAs. We have used the Partitioning93 benchmarks described with the Xilinx Netlist Format (XNF). The results obtained show how genetic algorithms are capable of accomplishing successfully the partitioning and placement tasks while respecting the board constraints.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115438099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-05DOI: 10.1109/EURMIC.2000.874662
R. Drechsler, Nicole Drechsler, E. Mackensen, Tobias Schubert, B. Becker
We present a scalable, low cost multiprocessor system, which is used in the area of measurement, regulation, controlling and soft computing. The system is an example of extremely modular hardware/software design. Modular in this context means that we can easily change or optimize individually the components in the system for a given problem. One of the most important aspects of our multiprocessor system is the fact that the user can dynamically change the communication topology by software 'on-the-fly'. Thus, the hardware can be (re)configured during operation in less than 1 ms. By this, the CPUs in the multiprocessor system can communicate directly without any invention of another processor preventing the typical bottleneck in parallel systems. First applications have been implemented in an embedded controller for a vote counting machine, with emphasis on high data security and high throughput.
{"title":"Design reuse by modularity: a scalable dynamical (re)configurable multiprocessor system","authors":"R. Drechsler, Nicole Drechsler, E. Mackensen, Tobias Schubert, B. Becker","doi":"10.1109/EURMIC.2000.874662","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874662","url":null,"abstract":"We present a scalable, low cost multiprocessor system, which is used in the area of measurement, regulation, controlling and soft computing. The system is an example of extremely modular hardware/software design. Modular in this context means that we can easily change or optimize individually the components in the system for a given problem. One of the most important aspects of our multiprocessor system is the fact that the user can dynamically change the communication topology by software 'on-the-fly'. Thus, the hardware can be (re)configured during operation in less than 1 ms. By this, the CPUs in the multiprocessor system can communicate directly without any invention of another processor preventing the typical bottleneck in parallel systems. First applications have been implemented in an embedded controller for a vote counting machine, with emphasis on high data security and high throughput.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122880497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-05DOI: 10.1109/EURMIC.2000.874616
P. Andersson, K. Kuchcinski
Time-multiplexing is a promising method to reduce the cost of FPGA based systems. It means execution of logic in consecutive steps with reconfiguration taking place between these steps. The use of time-multiplexing makes it possible to reduce the size of FPGAs but requires a new step in the design flow. The circuit has to be divided into sequential steps, partitions. In this paper we present an algorithm which partitions sequential circuits for time-multiplexing. The algorithm is based on list scheduling. Our experiments show that the algorithm is fast. It is able to partition a design with 4000 nodes in less than 4 seconds. The generated partitions have small size overhead, up to 3.2%, while no time overhead is allowed, besides the necessary reconfiguration time.
{"title":"Performance oriented partitioning for time-multiplexed FPGA's","authors":"P. Andersson, K. Kuchcinski","doi":"10.1109/EURMIC.2000.874616","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874616","url":null,"abstract":"Time-multiplexing is a promising method to reduce the cost of FPGA based systems. It means execution of logic in consecutive steps with reconfiguration taking place between these steps. The use of time-multiplexing makes it possible to reduce the size of FPGAs but requires a new step in the design flow. The circuit has to be divided into sequential steps, partitions. In this paper we present an algorithm which partitions sequential circuits for time-multiplexing. The algorithm is based on list scheduling. Our experiments show that the algorithm is fast. It is able to partition a design with 4000 nodes in less than 4 seconds. The generated partitions have small size overhead, up to 3.2%, while no time overhead is allowed, besides the necessary reconfiguration time.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123999090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-05DOI: 10.1109/EURMIC.2000.874620
C. André, Marie-Agnès Peraldi-Frati
The authors propose a high-level description of the behavior of digital systems. Behaviors are specified with a graphical synchronous model: "SyncCharts". SyncCharts supports hierarchical descriptions, concurrency and preemption. It is fully compatible with the programming environment of the Esterel synchronous language and can generate output formats understandable by synthesis tools. Thanks to the mathematical semantics of the model, the correctness of the design can be formally established. Taking the example of a non-trivial binary encoder/decoder, we show how our approach makes the design easier, without loss of rigour or efficiency.
{"title":"Behavioral specification of a circuit using SyncCharts: a case study","authors":"C. André, Marie-Agnès Peraldi-Frati","doi":"10.1109/EURMIC.2000.874620","DOIUrl":"https://doi.org/10.1109/EURMIC.2000.874620","url":null,"abstract":"The authors propose a high-level description of the behavior of digital systems. Behaviors are specified with a graphical synchronous model: \"SyncCharts\". SyncCharts supports hierarchical descriptions, concurrency and preemption. It is fully compatible with the programming environment of the Esterel synchronous language and can generate output formats understandable by synthesis tools. Thanks to the mathematical semantics of the model, the correctness of the design can be formally established. Taking the example of a non-trivial binary encoder/decoder, we show how our approach makes the design easier, without loss of rigour or efficiency.","PeriodicalId":138250,"journal":{"name":"Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129234684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：