Pub Date : 1900-01-01DOI: 10.1109/ICCCI.2018.8441263
Hari Sai Ram Vamsi, K. Reddy, C. Babu, N. S. Murty
The future of computing is highly dependent on the reversible logic based logic circuitry because the reversible logic implementation reduces the power dissipated compared to the conventional logic based computing. As the reversible logic is more advantageous in reducing power dissipation, the important and frequently used modules can be designed through this reversible logic. There are special reversible logic gates present which are reversible in nature i.e inputs also can be realized from the outputs and they are selected based on the Quantum cost and Garbage outputs. A Multiply and Accumulate (MAC) unit is one of the most frequently used design in the Digital Signal Processing (DSP) applications and also used in many of the FPGA architectures. Hence reversible implementation of 32 bit MAC unit which is frequently used in digital world is done in this paper. Radix-16 Booth encoded Wallace tree multiplier which gives better results is considered in this MAC unit design. Different types of adders are designed and all combinations are compared. A testable 64-bit reversible PIPO unit is designed which stores the temporary values. The complete design of this MAC unit is done in Verilog HDL and synthesis is done using Cadence RTL Compiler. This design is also implemented on Xilinx Virtex 7 FPGA using Synplify Premier tool.
{"title":"Design of reversible logic based 32-bit MAC unit using radix-16 booth encoded wallace tree multiplier","authors":"Hari Sai Ram Vamsi, K. Reddy, C. Babu, N. S. Murty","doi":"10.1109/ICCCI.2018.8441263","DOIUrl":"https://doi.org/10.1109/ICCCI.2018.8441263","url":null,"abstract":"The future of computing is highly dependent on the reversible logic based logic circuitry because the reversible logic implementation reduces the power dissipated compared to the conventional logic based computing. As the reversible logic is more advantageous in reducing power dissipation, the important and frequently used modules can be designed through this reversible logic. There are special reversible logic gates present which are reversible in nature i.e inputs also can be realized from the outputs and they are selected based on the Quantum cost and Garbage outputs. A Multiply and Accumulate (MAC) unit is one of the most frequently used design in the Digital Signal Processing (DSP) applications and also used in many of the FPGA architectures. Hence reversible implementation of 32 bit MAC unit which is frequently used in digital world is done in this paper. Radix-16 Booth encoded Wallace tree multiplier which gives better results is considered in this MAC unit design. Different types of adders are designed and all combinations are compared. A testable 64-bit reversible PIPO unit is designed which stores the temporary values. The complete design of this MAC unit is done in Verilog HDL and synthesis is done using Cadence RTL Compiler. This design is also implemented on Xilinx Virtex 7 FPGA using Synplify Premier tool.","PeriodicalId":141663,"journal":{"name":"2018 International Conference on Computer Communication and Informatics (ICCCI)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128132510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICCCI.2018.8441218
Hamsagayathri Palanisamy, S. Palaniswami
In this research paper, an effective and efficient optimization technique is utilized for miniaturization of the antenna structure. Earlier research articles have never employed Whale Optimization Algorithm (WOA) for antenna optimization and hence this paper focus to exploit Bio inspired whale metaheuristic algorithm for patch antenna optimization with objective of $pmb{S_{11} < =}pmb{-20 mathrm{dB}}$. The optimized Quad H slotted antenna has been designed and simulated using ADS. Various performance parameters like return loss, gain, directivity, radiation pattern are analyzed. Impedance and radiation characteristics of the proposed antenna are tested using N9923A vector network analyzer (4 GHz) and in anechoic chamber. It confirms that proposed antenna has attained the minimum return loss −28.764 dB with maximum gain of 5.566 dBi and directivity of 6.510 dBi at the designed frequency 2.45 GHz.
{"title":"Design and Performance analysis of compact H-Slotted antenna for 2.45 GHz","authors":"Hamsagayathri Palanisamy, S. Palaniswami","doi":"10.1109/ICCCI.2018.8441218","DOIUrl":"https://doi.org/10.1109/ICCCI.2018.8441218","url":null,"abstract":"In this research paper, an effective and efficient optimization technique is utilized for miniaturization of the antenna structure. Earlier research articles have never employed Whale Optimization Algorithm (WOA) for antenna optimization and hence this paper focus to exploit Bio inspired whale metaheuristic algorithm for patch antenna optimization with objective of $pmb{S_{11} < =}pmb{-20 mathrm{dB}}$. The optimized Quad H slotted antenna has been designed and simulated using ADS. Various performance parameters like return loss, gain, directivity, radiation pattern are analyzed. Impedance and radiation characteristics of the proposed antenna are tested using N9923A vector network analyzer (4 GHz) and in anechoic chamber. It confirms that proposed antenna has attained the minimum return loss −28.764 dB with maximum gain of 5.566 dBi and directivity of 6.510 dBi at the designed frequency 2.45 GHz.","PeriodicalId":141663,"journal":{"name":"2018 International Conference on Computer Communication and Informatics (ICCCI)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117264648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICCCI.2018.8441328
Vaishali Muralidharan, S. Arumugham, Sivaraman Rethinam, S. Janakiraman, H. Upadhyay, Sundararaman Rajagopalan
Looking at the demands of secure communication schemes, new platforms for information security have a significant role in the data protection. In this paper, image encryption on reconfigurable hardware FPGA has been proposed with the confluence of the chaotic map and DNA schemes. Confusion and diffusion were performed with both Chaotic and DNA approaches. The image encryption architecture with 128 × 128 grayscale image which was implemented on Cyclone II FPGA EP2C35F672C6 consumed 23,877 (72%) logic elements, 131,072 (27%) internal M4KRAM memory units with a total thermal power dissipation of 273.55 mW for a test image. NPCR, UACI, Correlation, Uniform distribution and entropy analyses revealed the strength of the proposed scheme which requires a specific bitstream and hardware to retrieve and decrypt the hidden secret image on FPGA.
从安全通信方案的需求来看，新的信息安全平台在数据保护方面具有重要作用。本文提出了一种基于可重构硬件FPGA的图像加密方案，将混沌映射和DNA方案相结合。用混沌和DNA两种方法进行混淆和扩散。在Cyclone II FPGA EP2C35F672C6上实现的128 × 128灰度图像加密架构，测试图像消耗23,877(72%)个逻辑元件，131,072(27%)个内部M4KRAM存储单元，总热功耗为273.55 mW。NPCR、UACI、相关性、均匀分布和熵分析显示了该方案的强度，该方案需要特定的比特流和硬件来在FPGA上检索和解密隐藏的秘密图像。
{"title":"Chaos Blend DNA Coding for Image Encryption on FPGA","authors":"Vaishali Muralidharan, S. Arumugham, Sivaraman Rethinam, S. Janakiraman, H. Upadhyay, Sundararaman Rajagopalan","doi":"10.1109/ICCCI.2018.8441328","DOIUrl":"https://doi.org/10.1109/ICCCI.2018.8441328","url":null,"abstract":"Looking at the demands of secure communication schemes, new platforms for information security have a significant role in the data protection. In this paper, image encryption on reconfigurable hardware FPGA has been proposed with the confluence of the chaotic map and DNA schemes. Confusion and diffusion were performed with both Chaotic and DNA approaches. The image encryption architecture with 128 × 128 grayscale image which was implemented on Cyclone II FPGA EP2C35F672C6 consumed 23,877 (72%) logic elements, 131,072 (27%) internal M4KRAM memory units with a total thermal power dissipation of 273.55 mW for a test image. NPCR, UACI, Correlation, Uniform distribution and entropy analyses revealed the strength of the proposed scheme which requires a specific bitstream and hardware to retrieve and decrypt the hidden secret image on FPGA.","PeriodicalId":141663,"journal":{"name":"2018 International Conference on Computer Communication and Informatics (ICCCI)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116105552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICCCI.2018.8441350
Renu Jaiswal, Mahendra Sahare, Umesh Lilhore
In software industry analyzing bug by various tester and developer is a costly approach. So collecting these bug reports and triage is done manually which consume time with high rate of error. Here proposed work has focus on this triage of the bug reports by reducing the dataset size. In order to reduce cost of bug triage proper sequencing of the instance and feature selection is done. Here instance and feature selection are clustered by using list of words, keywords and bug id as fitness function parameters. Two stage learning genetic algorithm named as teacher learning based optimization was used for clustering. As genetic algorithms are unsupervised learning approach, so new set bug report triage is adopt by the proposed work. Experiment is done on real dataset of bug reports. Result shows that proposed work is better on precision value by 38.5% while execution time was reduce by 29.2% as compared with existing procedures.
{"title":"Genetic Approach based Bug Triage for Sequencing the Instance and Features","authors":"Renu Jaiswal, Mahendra Sahare, Umesh Lilhore","doi":"10.1109/ICCCI.2018.8441350","DOIUrl":"https://doi.org/10.1109/ICCCI.2018.8441350","url":null,"abstract":"In software industry analyzing bug by various tester and developer is a costly approach. So collecting these bug reports and triage is done manually which consume time with high rate of error. Here proposed work has focus on this triage of the bug reports by reducing the dataset size. In order to reduce cost of bug triage proper sequencing of the instance and feature selection is done. Here instance and feature selection are clustered by using list of words, keywords and bug id as fitness function parameters. Two stage learning genetic algorithm named as teacher learning based optimization was used for clustering. As genetic algorithms are unsupervised learning approach, so new set bug report triage is adopt by the proposed work. Experiment is done on real dataset of bug reports. Result shows that proposed work is better on precision value by 38.5% while execution time was reduce by 29.2% as compared with existing procedures.","PeriodicalId":141663,"journal":{"name":"2018 International Conference on Computer Communication and Informatics (ICCCI)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124176928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICCCI.2018.8441381
Pallav Parmar, Abhishek Sharma, Amit Kumar Sahu
In today's scenario there is a wide scope in the field of Image Denoising as the demand of noise free images are continuously increasing in this era. It is an important division of Image Processing. Still there are several methods are applied successfully to some extent to retrieve noise free images but there is a chance of improvement. Our aim of this paper to frame an efficient method based on non-local mean filter so that sparsity and multiresolution structure of non-local mean filter properties can be used for Image Denosing.
{"title":"Improved Denoising Technique for Medical Mri Brain Images","authors":"Pallav Parmar, Abhishek Sharma, Amit Kumar Sahu","doi":"10.1109/ICCCI.2018.8441381","DOIUrl":"https://doi.org/10.1109/ICCCI.2018.8441381","url":null,"abstract":"In today's scenario there is a wide scope in the field of Image Denoising as the demand of noise free images are continuously increasing in this era. It is an important division of Image Processing. Still there are several methods are applied successfully to some extent to retrieve noise free images but there is a chance of improvement. Our aim of this paper to frame an efficient method based on non-local mean filter so that sparsity and multiresolution structure of non-local mean filter properties can be used for Image Denosing.","PeriodicalId":141663,"journal":{"name":"2018 International Conference on Computer Communication and Informatics (ICCCI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130205695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICCCI.2018.8441281
H. Tarunkumar, A. Ranjan, Nonglen Meitei Pheiroijam
This paper presents an active design for fourth order band pass filter (BPF) and all pass filter (APF) using Four Terminal Floating Nullor (FTFN) where the selection of input sections provides the output filter function. The proposed filter uses single FTFN with four resistors and four capacitors and does not required component matching. The filter circuit is simulated using commercially available AD844 and CMOS technology with $mathbf{0}.mathbf{35} pmb{mu}mathbf{m}$ based FTFN design. Theoretical observation through transfer function also matches the simulation results.
{"title":"Fourth Order Band Pass and All Pass Filter using Single FTFN","authors":"H. Tarunkumar, A. Ranjan, Nonglen Meitei Pheiroijam","doi":"10.1109/ICCCI.2018.8441281","DOIUrl":"https://doi.org/10.1109/ICCCI.2018.8441281","url":null,"abstract":"This paper presents an active design for fourth order band pass filter (BPF) and all pass filter (APF) using Four Terminal Floating Nullor (FTFN) where the selection of input sections provides the output filter function. The proposed filter uses single FTFN with four resistors and four capacitors and does not required component matching. The filter circuit is simulated using commercially available AD844 and CMOS technology with $mathbf{0}.mathbf{35} pmb{mu}mathbf{m}$ based FTFN design. Theoretical observation through transfer function also matches the simulation results.","PeriodicalId":141663,"journal":{"name":"2018 International Conference on Computer Communication and Informatics (ICCCI)","volume":"49 44","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120810972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICCCI.2018.8441368
S. Kumar, P. S. Kumar
Asynchronous circuits are a promising design style for high performance and low-power applications. Among the templates, pipeline templates are popular in high-performance systems. In asynchronous pipelines, every stage has to wait for its successive stage to complete its operation as they were interrelated to each other by hand shaking protocols. Asynchronous circuits are cyclic in nature. Current EDA tools support only acyclic circuits for timing calculations. The present tools have to adapt to new algorithms in order to support full cyclic circuits. The work in this paper proposes an asynchronous pipelining template without handshaking protocols which will be acyclic in nature so that timing calculations are possible with the current EDA tools without the need of adapting to any new algorithms.
{"title":"Pulse based Acyclic Asynchronous Pipelines for Combinational Logic Circuits","authors":"S. Kumar, P. S. Kumar","doi":"10.1109/ICCCI.2018.8441368","DOIUrl":"https://doi.org/10.1109/ICCCI.2018.8441368","url":null,"abstract":"Asynchronous circuits are a promising design style for high performance and low-power applications. Among the templates, pipeline templates are popular in high-performance systems. In asynchronous pipelines, every stage has to wait for its successive stage to complete its operation as they were interrelated to each other by hand shaking protocols. Asynchronous circuits are cyclic in nature. Current EDA tools support only acyclic circuits for timing calculations. The present tools have to adapt to new algorithms in order to support full cyclic circuits. The work in this paper proposes an asynchronous pipelining template without handshaking protocols which will be acyclic in nature so that timing calculations are possible with the current EDA tools without the need of adapting to any new algorithms.","PeriodicalId":141663,"journal":{"name":"2018 International Conference on Computer Communication and Informatics (ICCCI)","volume":"22 23","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113955546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICCCI.2018.8441356
K. Jaiswal, Ankit Kumar Patel, S. Yadav, R. S. Yadav, Rajeev Singh
A new ultra wide band (UWB) proximity fed gap-coupled microstrip patch antenna is proposed in this paper. The proposed antenna is designed using Christmas tree-shaped patch with additional slot on the patch and ground. The proposed antenna resonate at three ultra-wide bands and single wide band with impedance bandwidth of 20.82%, 28.43%, 14.83 % and 8.23% respectively.
{"title":"Christmas tree Shaped Proximity Coupled Microstrip Patch Antenna for Multiple Ultra Wide-Band Application","authors":"K. Jaiswal, Ankit Kumar Patel, S. Yadav, R. S. Yadav, Rajeev Singh","doi":"10.1109/ICCCI.2018.8441356","DOIUrl":"https://doi.org/10.1109/ICCCI.2018.8441356","url":null,"abstract":"A new ultra wide band (UWB) proximity fed gap-coupled microstrip patch antenna is proposed in this paper. The proposed antenna is designed using Christmas tree-shaped patch with additional slot on the patch and ground. The proposed antenna resonate at three ultra-wide bands and single wide band with impedance bandwidth of 20.82%, 28.43%, 14.83 % and 8.23% respectively.","PeriodicalId":141663,"journal":{"name":"2018 International Conference on Computer Communication and Informatics (ICCCI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122347414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICCCI.2018.8441387
Sricheta Parui, Lidia Ghosh, A. Konar
The present work aims at classifying the 3 different learning levels of a subject during olfactory memory learning task based on the N400 repetition effects. The paper proposes a simple feature extraction technique to detect the N400 signal from the captured electroencephalographic waveform and an Interval type-2 Fuzzy Classifier is then designed to classify the learning levels using the extracted features. The paper also proposes a way to detect the early Alzheimer and schizophrenic patients using an event-related potential named N400. Here it is shown that the repetition effect of the N400 signal is different for the Alzheimer patients and healthy person. An N400 peak is noticed for both the Alzheimer patients and the healthy person but the amplitude of the curve is different for two different cases. The other aspect of this present work reveals that the increased latency of N400 signal can help us to detect a schizophrenic patient.
{"title":"N400 Repetition Effects on Olfactory Memory Learning","authors":"Sricheta Parui, Lidia Ghosh, A. Konar","doi":"10.1109/ICCCI.2018.8441387","DOIUrl":"https://doi.org/10.1109/ICCCI.2018.8441387","url":null,"abstract":"The present work aims at classifying the 3 different learning levels of a subject during olfactory memory learning task based on the N400 repetition effects. The paper proposes a simple feature extraction technique to detect the N400 signal from the captured electroencephalographic waveform and an Interval type-2 Fuzzy Classifier is then designed to classify the learning levels using the extracted features. The paper also proposes a way to detect the early Alzheimer and schizophrenic patients using an event-related potential named N400. Here it is shown that the repetition effect of the N400 signal is different for the Alzheimer patients and healthy person. An N400 peak is noticed for both the Alzheimer patients and the healthy person but the amplitude of the curve is different for two different cases. The other aspect of this present work reveals that the increased latency of N400 signal can help us to detect a schizophrenic patient.","PeriodicalId":141663,"journal":{"name":"2018 International Conference on Computer Communication and Informatics (ICCCI)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123861537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICCCI.2018.8441202
S. Umamaheshwari, J. N. Swaminathan
In a Wireless Sensor Network (WSN) which is heavily deployed, shortest direct communication would be possible for a node to its numerous neighboring nodes. When the connection is established with moderate transmission power, the method is not beneficial. But at the same time lot of energy required for high power. Recent research has taken new tasks to further development of various net-work protocols like energy feeding, network exposure, fault in nodes, node failure tolerance, lifetime of network has to be conserved in WSN. Better topology has been employed in this paper that leads to better performance of WSN with man in middle attack. In this paper, a modified scale free topology had been proposed that leads to various advantages of tolerance against intrusion, fault and also some selective remove attacks.
{"title":"Man-In-Middle Attack/for a Free Scale Topology","authors":"S. Umamaheshwari, J. N. Swaminathan","doi":"10.1109/ICCCI.2018.8441202","DOIUrl":"https://doi.org/10.1109/ICCCI.2018.8441202","url":null,"abstract":"In a Wireless Sensor Network (WSN) which is heavily deployed, shortest direct communication would be possible for a node to its numerous neighboring nodes. When the connection is established with moderate transmission power, the method is not beneficial. But at the same time lot of energy required for high power. Recent research has taken new tasks to further development of various net-work protocols like energy feeding, network exposure, fault in nodes, node failure tolerance, lifetime of network has to be conserved in WSN. Better topology has been employed in this paper that leads to better performance of WSN with man in middle attack. In this paper, a modified scale free topology had been proposed that leads to various advantages of tolerance against intrusion, fault and also some selective remove attacks.","PeriodicalId":141663,"journal":{"name":"2018 International Conference on Computer Communication and Informatics (ICCCI)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127948651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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