Pub Date : 2022-12-01DOI: 10.1109/MCSoC57363.2022.00024
Akram Ben Ahmed, Ryousei Takano, Takahiro Hirofuchi
In recent years, Edge Computing has been attracting a lot of attention as it has shown its ability to mitigate some issues found in Cloud Computing (e.g., high latency, centralization issues, programmability, etc.), Moving computation from the Cloud to the Edge has resulted in an exponential increase in the number of devices to be connected. With such an increase, interconnection has become a major design and performance factor, especially in terms of power efficiency. Thus, the question that a lot of research has been trying to answer is how to connect such devices in a power-efficient way while making sure to maintain high-performance and accuracy at the lowest cost. In this paper, we investigate the Error-permissive communication paradigm and its potential to answer the aforementioned question. In particular, we focus on the importance of using this paradigm on Multi-FPGA systems which have gained significant attention in Edge Computing and can be a good candidate for Error-permissive communication. We also present a preliminary evaluation of a novel concept to reduce the power consumption by undervolting the supply voltage of the serial transceivers, and we show its potential to reduce the total FPGA power consumption by up to 26%.
{"title":"Exploring the Potential of Error-permissive Communication in Multi-FPGA-based Edge Computing","authors":"Akram Ben Ahmed, Ryousei Takano, Takahiro Hirofuchi","doi":"10.1109/MCSoC57363.2022.00024","DOIUrl":"https://doi.org/10.1109/MCSoC57363.2022.00024","url":null,"abstract":"In recent years, Edge Computing has been attracting a lot of attention as it has shown its ability to mitigate some issues found in Cloud Computing (e.g., high latency, centralization issues, programmability, etc.), Moving computation from the Cloud to the Edge has resulted in an exponential increase in the number of devices to be connected. With such an increase, interconnection has become a major design and performance factor, especially in terms of power efficiency. Thus, the question that a lot of research has been trying to answer is how to connect such devices in a power-efficient way while making sure to maintain high-performance and accuracy at the lowest cost. In this paper, we investigate the Error-permissive communication paradigm and its potential to answer the aforementioned question. In particular, we focus on the importance of using this paradigm on Multi-FPGA systems which have gained significant attention in Edge Computing and can be a good candidate for Error-permissive communication. We also present a preliminary evaluation of a novel concept to reduce the power consumption by undervolting the supply voltage of the serial transceivers, and we show its potential to reduce the total FPGA power consumption by up to 26%.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120939215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Repetitive transcranial magnetic stimulation (rTMS) is a non-invasive antidepressant neuromodulation therapy for treatment-resistant depression (TRD). However, the remission rate of patients remains unsatisfactory possibly due to the suboptimal configuration of conventional rTMS protocol. This work aims to design a close-loop TMS system and validate the practicability of brain-state-dependent stimulation based on real-time monitoring of electroencephalogram (EEG). We propose a novel method of phase estimation to enhance the precision of EEG phase-triggered firing of TMS. Our implementation supports subsequent studies on personalized brain-state-dependent neuromodulation for clinical applications.
{"title":"Toward EEG-Based Brain State Recognition for Personalized Neuromodulation","authors":"Yu-Cheng Chang, Pin-Hsuan Chao, Sin-Horng Chen, Chun-Shu Wei","doi":"10.1109/MCSoC57363.2022.00053","DOIUrl":"https://doi.org/10.1109/MCSoC57363.2022.00053","url":null,"abstract":"Repetitive transcranial magnetic stimulation (rTMS) is a non-invasive antidepressant neuromodulation therapy for treatment-resistant depression (TRD). However, the remission rate of patients remains unsatisfactory possibly due to the suboptimal configuration of conventional rTMS protocol. This work aims to design a close-loop TMS system and validate the practicability of brain-state-dependent stimulation based on real-time monitoring of electroencephalogram (EEG). We propose a novel method of phase estimation to enhance the precision of EEG phase-triggered firing of TMS. Our implementation supports subsequent studies on personalized brain-state-dependent neuromodulation for clinical applications.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121334140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Endometrial segmentation plays a vital role in the computerized evaluation of uterine ultrasonic images. Accurate segmentation of endometrial regions may improve the accuracy and efficiency of diagnosis. Recent studies have been focused on the employment of deep learning in medical image segmentation. In this study, we compared six models, including five convolutional neural networks with different network architectures (UNet, Segnet) and backbones (Resnet50, Vanilla CNN, VGG16) for the segmentation of endometrium, and one model called deep dual-resolution networks (DDRNets). The training and test datasets were composed of 840 and 210 images from 302 and 68 cases, respectively. Through validation, DRRNets demonstrated the best performance for endometrial segmentation with an average Dice coefficient (DSC) of 0.895.
{"title":"Automatic endometrial segmentation in ultrasound images using deep learning","authors":"Yiyang Liu, Boyuan Peng, Xin Zhu, Wenwen Wang, Qin Zhou, Shixuan Wang, Jingjing Jiang, Li Fang","doi":"10.1109/MCSoC57363.2022.00020","DOIUrl":"https://doi.org/10.1109/MCSoC57363.2022.00020","url":null,"abstract":"Endometrial segmentation plays a vital role in the computerized evaluation of uterine ultrasonic images. Accurate segmentation of endometrial regions may improve the accuracy and efficiency of diagnosis. Recent studies have been focused on the employment of deep learning in medical image segmentation. In this study, we compared six models, including five convolutional neural networks with different network architectures (UNet, Segnet) and backbones (Resnet50, Vanilla CNN, VGG16) for the segmentation of endometrium, and one model called deep dual-resolution networks (DDRNets). The training and test datasets were composed of 840 and 210 images from 302 and 68 cases, respectively. Through validation, DRRNets demonstrated the best performance for endometrial segmentation with an average Dice coefficient (DSC) of 0.895.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116210864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/MCSoC57363.2022.10023992
Yujie Gao, Yuan He, Xiaohan Yue, Haiyan Jiang, Xibo Wang
A growing number of cores per chip has driven the rapid adoption of increasingly complex Networks-on-Chip (NoCs) under diminishing power budgets. In such a situation, having more routers or having routers with higher radix is inevitable, which creates higher demands for input buffers while they already draw a significant amount of power. Thus, this paper introduces a hybrid input buffer design for on-chip routers attempting to shrink their power consumption while conserving performance. The key idea behind this proposal is to design input buffers with the network traffic characteristics in mind. As in our observations, a large portion of the network traffic is short packets, which means, it is fair to implement most of the input buffers with slow but less leaky devices (STT-MRAM) to suppress the static power consumption while still having most of the network traffic stored in fast but leaky SRAM devices to conserve the network performance. Our evaluations show that this hybrid design can achieve an average reduction of energy consumption per flit by 44.5% under 93.6% of the original router area and small degradation of the network performance.
{"title":"Traffic-Aware Energy-Efficient Hybrid Input Buffer Design for On-Chip Routers","authors":"Yujie Gao, Yuan He, Xiaohan Yue, Haiyan Jiang, Xibo Wang","doi":"10.1109/MCSoC57363.2022.10023992","DOIUrl":"https://doi.org/10.1109/MCSoC57363.2022.10023992","url":null,"abstract":"A growing number of cores per chip has driven the rapid adoption of increasingly complex Networks-on-Chip (NoCs) under diminishing power budgets. In such a situation, having more routers or having routers with higher radix is inevitable, which creates higher demands for input buffers while they already draw a significant amount of power. Thus, this paper introduces a hybrid input buffer design for on-chip routers attempting to shrink their power consumption while conserving performance. The key idea behind this proposal is to design input buffers with the network traffic characteristics in mind. As in our observations, a large portion of the network traffic is short packets, which means, it is fair to implement most of the input buffers with slow but less leaky devices (STT-MRAM) to suppress the static power consumption while still having most of the network traffic stored in fast but leaky SRAM devices to conserve the network performance. Our evaluations show that this hybrid design can achieve an average reduction of energy consumption per flit by 44.5% under 93.6% of the original router area and small degradation of the network performance.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132221348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/MCSoC57363.2022.00030
M. Al-Shatari, F. Hussin, A. A. Aziz, M. S. Rohmad, Xuan-Tu Tran
IoT devices are being used in different environments recently. They are mostly resource-constrained, and therefore, their data security is crucial. Several lightweight cryptographic primitives were proposed to overcome the limitations of the devices while maintaining moderate security levels. Such primitives provide either encryption or authentication. The encryption must be authenticated by a Message Authentication Code (MA C) or hash function for better overall security. Therefore, an architecture of integrated lightweight authenticated encryption (AE) based on LED block cipher and PHOTON hash function is presented. LED and PHOTON architectures were combined while exploiting area-performance trade-offs and utilizing the shared internal functions. The architecture is designed in Verilog HDL, synthesized in Altera Quartus II and simulated on Field Programmable Gate Array (FPGA) devices. The individual design of LED utilizes 357 logic elements (LE) and PHOTON utilizes 852 LE resulting in a total of 1209 LE. The logic utilization of the proposed shared architecture is 1046 LE. The results reveal that 13.5 % reduction in logic area is achieved compared to the independent implementations of LED and PHOTON.
最近，物联网设备正在不同的环境中使用。他们大多资源有限，因此，他们的数据安全至关重要。提出了几个轻量级的加密原语，以克服设备的限制，同时保持适度的安全级别。这些原语提供加密或身份验证。加密必须通过消息验证码(Message Authentication Code, MA C)或散列函数进行身份验证，以获得更好的整体安全性。为此，提出了一种基于LED分组密码和光子哈希函数的集成轻量级认证加密(AE)体系结构。LED和光子架构结合在一起，同时利用面积性能权衡和共享的内部功能。该体系结构采用Verilog HDL进行设计，在Altera Quartus II中进行合成，并在现场可编程门阵列(FPGA)器件上进行仿真。LED的单独设计使用357个逻辑元件(LE)，而PHOTON使用852个逻辑元件，总共使用1209个逻辑元件。所提出的共享体系结构的逻辑利用率为1046le。结果表明，与独立实现LED和光子相比，该电路的逻辑面积减少了13.5%。
{"title":"Composite Lightweight Authenticated Encryption Based on LED Block Cipher and PHOTON Hash Function for IoT Devices","authors":"M. Al-Shatari, F. Hussin, A. A. Aziz, M. S. Rohmad, Xuan-Tu Tran","doi":"10.1109/MCSoC57363.2022.00030","DOIUrl":"https://doi.org/10.1109/MCSoC57363.2022.00030","url":null,"abstract":"IoT devices are being used in different environments recently. They are mostly resource-constrained, and therefore, their data security is crucial. Several lightweight cryptographic primitives were proposed to overcome the limitations of the devices while maintaining moderate security levels. Such primitives provide either encryption or authentication. The encryption must be authenticated by a Message Authentication Code (MA C) or hash function for better overall security. Therefore, an architecture of integrated lightweight authenticated encryption (AE) based on LED block cipher and PHOTON hash function is presented. LED and PHOTON architectures were combined while exploiting area-performance trade-offs and utilizing the shared internal functions. The architecture is designed in Verilog HDL, synthesized in Altera Quartus II and simulated on Field Programmable Gate Array (FPGA) devices. The individual design of LED utilizes 357 logic elements (LE) and PHOTON utilizes 852 LE resulting in a total of 1209 LE. The logic utilization of the proposed shared architecture is 1046 LE. The results reveal that 13.5 % reduction in logic area is achieved compared to the independent implementations of LED and PHOTON.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115435717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/mcsoc57363.2022.00005
{"title":"Message from the Chairs: Welcome to the 2022 IEEE 15th International Symposium on embedded Multicore/Many-core Systems-on-Chip (IEEE MCSoC-2022)","authors":"","doi":"10.1109/mcsoc57363.2022.00005","DOIUrl":"https://doi.org/10.1109/mcsoc57363.2022.00005","url":null,"abstract":"","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115589649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/MCSoC57363.2022.00057
Takumi Inaba, Takatsugu Ono, Koji Inoue, Satoshi Kawakami
The performance improvement by CMOS circuit technology is reaching its limits. Many researchers have been studying computing technologies that use emerging devices to challenge such critical issues. Nanophotonic technology is a promising candidate due to its ultra-low latency, high bandwidth, and low power natures. The advanced research activity of nanophotonic computing is to design hardware accelerators for AI inference applications. However, few considerations about nanophotonic accelerators for AI training applications have been conducted. The main reason is that state-of-the-art nanophotonic AI accelerators involve integer operations, whereas floating-point (FP) sum-of-products dominate the training process. However, to the best of the authors' knowledge, there are no optical circuits that target floating-point arithmetic units. This study proposes a novel Opto-Electrical Floating-point Multiplier (OEFM) toward ultra-low-latency, a power-efficient nanophotonic accelerator for AI training applications. We design a microarchitecture of OEFM, including a novel optical integer multiplier and other electrical components. Based on our evaluation framework, we analyze the calculation accuracy of the proposed multiplier and OEFM. Experimental results show that OEFM achieves a 56 % reduction in latency and a 41 % reduction in energy consumption compared with a conventional electrical circuit.
{"title":"A Hybrid Opto-Electrical Floating-point Multiplier","authors":"Takumi Inaba, Takatsugu Ono, Koji Inoue, Satoshi Kawakami","doi":"10.1109/MCSoC57363.2022.00057","DOIUrl":"https://doi.org/10.1109/MCSoC57363.2022.00057","url":null,"abstract":"The performance improvement by CMOS circuit technology is reaching its limits. Many researchers have been studying computing technologies that use emerging devices to challenge such critical issues. Nanophotonic technology is a promising candidate due to its ultra-low latency, high bandwidth, and low power natures. The advanced research activity of nanophotonic computing is to design hardware accelerators for AI inference applications. However, few considerations about nanophotonic accelerators for AI training applications have been conducted. The main reason is that state-of-the-art nanophotonic AI accelerators involve integer operations, whereas floating-point (FP) sum-of-products dominate the training process. However, to the best of the authors' knowledge, there are no optical circuits that target floating-point arithmetic units. This study proposes a novel Opto-Electrical Floating-point Multiplier (OEFM) toward ultra-low-latency, a power-efficient nanophotonic accelerator for AI training applications. We design a microarchitecture of OEFM, including a novel optical integer multiplier and other electrical components. Based on our evaluation framework, we analyze the calculation accuracy of the proposed multiplier and OEFM. Experimental results show that OEFM achieves a 56 % reduction in latency and a 41 % reduction in energy consumption compared with a conventional electrical circuit.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123622611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/MCSoC57363.2022.00067
Julian Robledo, J. Castrillón
Recent works on 5G baseband processing systems address the optimization of applications with different require-ments of quality of service (QoS). The volume and heterogeneity of applications that have to be processed on a base station are growing and 5G introduces new use cases that push system designers towards more flexible and adaptable approaches. To investigate future network challenges of mobile communications, a good methodology for the generation of realistic workloads, that allows target optimizations of different traffic scenarios, is required. In this paper, we study the variation of real traffic data on multiple base stations and identify the main sources for the high variation of the 5G workloads. We propose a methodology for parameterizable workload generation for users with different QoS requirements that enables optimization techniques in base-band processing systems. We demonstrate the feasibility of our approach based on a virtual base station using a heterogeneous hardware model and various state-of-the-art mapping policies.
{"title":"Parameterizable mobile workloads for adaptable base station optimizations","authors":"Julian Robledo, J. Castrillón","doi":"10.1109/MCSoC57363.2022.00067","DOIUrl":"https://doi.org/10.1109/MCSoC57363.2022.00067","url":null,"abstract":"Recent works on 5G baseband processing systems address the optimization of applications with different require-ments of quality of service (QoS). The volume and heterogeneity of applications that have to be processed on a base station are growing and 5G introduces new use cases that push system designers towards more flexible and adaptable approaches. To investigate future network challenges of mobile communications, a good methodology for the generation of realistic workloads, that allows target optimizations of different traffic scenarios, is required. In this paper, we study the variation of real traffic data on multiple base stations and identify the main sources for the high variation of the 5G workloads. We propose a methodology for parameterizable workload generation for users with different QoS requirements that enables optimization techniques in base-band processing systems. We demonstrate the feasibility of our approach based on a virtual base station using a heterogeneous hardware model and various state-of-the-art mapping policies.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121826644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/MCSoC57363.2022.00027
Ashwin Raut, Divesh Kumar, V. Chaurasiya, Manish Kumar
IoT data analytics have numerous applications that generate huge data to gain new insights and information. How-ever, this work remains challenging due to the heterogeneity of IoT data sources, unnecessary data processing, uncertainty in decision-making, data biasness, and ever-increasing data size. To overcome these challenges, we propose distributed decision fusion framework for the large-scale IoT ecosystem. The proposed framework has divided into three-level. The first and second level provides the local decision of the small individual ecosystem using the filter method-based feature selection and dynamic classifier selection criteria for decision making; whereas the third level fuses the collected decision from the small ecosystems using Majority voting, Weighted majority voting and distributed Naive Bayes classifier. Lastly, we illustrate performance of the proposed solution on the US-Accidents dataset.
{"title":"Distributed Decision Fusion for Large Scale IoT- Ecosystem","authors":"Ashwin Raut, Divesh Kumar, V. Chaurasiya, Manish Kumar","doi":"10.1109/MCSoC57363.2022.00027","DOIUrl":"https://doi.org/10.1109/MCSoC57363.2022.00027","url":null,"abstract":"IoT data analytics have numerous applications that generate huge data to gain new insights and information. How-ever, this work remains challenging due to the heterogeneity of IoT data sources, unnecessary data processing, uncertainty in decision-making, data biasness, and ever-increasing data size. To overcome these challenges, we propose distributed decision fusion framework for the large-scale IoT ecosystem. The proposed framework has divided into three-level. The first and second level provides the local decision of the small individual ecosystem using the filter method-based feature selection and dynamic classifier selection criteria for decision making; whereas the third level fuses the collected decision from the small ecosystems using Majority voting, Weighted majority voting and distributed Naive Bayes classifier. Lastly, we illustrate performance of the proposed solution on the US-Accidents dataset.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125545142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/MCSoC57363.2022.00034
Zhuoqi Guo, Yongchao Zhang, Meiling Hu, Zhongming Xue, Li Geng
For SoC and IoT systems, conventional power management unit (PMU) uses Buck converter and LDOs. With the increase of load current consumed by the digital circuits, the overall efficiency of the conventional architecture deteriorates due to the drop-voltage of the LDO. A new PMU architecture is proposed in this paper to break through the bottleneck of efficiency. The LDO is removed and a step-up converter provides the high voltage for the analog domain. The supply efficiency of the whole SoC could be improved because no LDO is needed for the current-hungry digital circuits. The new step-up converter named switched capacitor Buck (SCB) converter is presented by adding the switched capacitor network in the Buck converter. The most notable feature of SCB converter is that it achieves the step-up conversion with the Buck-like mode. It means that the transfer function, loop design, output ripple, and other characteristics are almost same as Buck converter, which help the implementation of proposed PMU. A prototype is implemented with a standard 0.18-μm CMOS technology. The whole system achieves high power efficiency of 94.5% For the system's power supply efficiency of SoC, the proposed PMU improves the efficiency by at least 12.5% than that of the conventional scheme.
{"title":"A 94.5% Peak Efficiency, 14mV Output Ripple SC-Buck Step-Up Converter with 1.2-to-5V Output Achieving 20.2% Enhanced Power Efficiency in New PMU Architecture for SoCs","authors":"Zhuoqi Guo, Yongchao Zhang, Meiling Hu, Zhongming Xue, Li Geng","doi":"10.1109/MCSoC57363.2022.00034","DOIUrl":"https://doi.org/10.1109/MCSoC57363.2022.00034","url":null,"abstract":"For SoC and IoT systems, conventional power management unit (PMU) uses Buck converter and LDOs. With the increase of load current consumed by the digital circuits, the overall efficiency of the conventional architecture deteriorates due to the drop-voltage of the LDO. A new PMU architecture is proposed in this paper to break through the bottleneck of efficiency. The LDO is removed and a step-up converter provides the high voltage for the analog domain. The supply efficiency of the whole SoC could be improved because no LDO is needed for the current-hungry digital circuits. The new step-up converter named switched capacitor Buck (SCB) converter is presented by adding the switched capacitor network in the Buck converter. The most notable feature of SCB converter is that it achieves the step-up conversion with the Buck-like mode. It means that the transfer function, loop design, output ripple, and other characteristics are almost same as Buck converter, which help the implementation of proposed PMU. A prototype is implemented with a standard 0.18-μm CMOS technology. The whole system achieves high power efficiency of 94.5% For the system's power supply efficiency of SoC, the proposed PMU improves the efficiency by at least 12.5% than that of the conventional scheme.","PeriodicalId":150801,"journal":{"name":"2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132897232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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