Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838560
U. Dinesh, S. Ram, M. Hariharan, K. Hariharan
Even though the hardware complexity is reduced and precision is increased in the DDFS, the obtained signal is in no match with the ideal signal. This is because of the non-linearity of DACs present in the DDFS architecture. The conventional DDFS architecture doesn't account for the non-linearity of DAC which deteriorates the quality of the signal. This reduces the SNR and SFDR of the signal. This error can be reduced by the optimizing the values using Genetic algorithm.
{"title":"Shaping of non linearity in direct digital frequency synthesizer - An approach by Genetic algorithm","authors":"U. Dinesh, S. Ram, M. Hariharan, K. Hariharan","doi":"10.1109/ICAEE.2014.6838560","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838560","url":null,"abstract":"Even though the hardware complexity is reduced and precision is increased in the DDFS, the obtained signal is in no match with the ideal signal. This is because of the non-linearity of DACs present in the DDFS architecture. The conventional DDFS architecture doesn't account for the non-linearity of DAC which deteriorates the quality of the signal. This reduces the SNR and SFDR of the signal. This error can be reduced by the optimizing the values using Genetic algorithm.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130824827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838563
R. Vijayaraghavan, N. R. Raajan, P. Sowmiya, A. Ragavi, R. Manoorubini, T. Selvi
In an audio speech signal, acoustic noise is a common problem while the speech is processed. Here, we are going to create color noise and add with an audio signal, after that a model are introduced to eliminate that noise. This paper elaborates a new approach for noise cancellation in speech enhancement using an Adaptive LMS (Least Mean Square) filter and with the help of MATLAB Simulink we get the correct speech signal. This filter is used to remove the acoustic noise due to its simplicity in computation & robust behavior when implemented in finite-precision hardware. It provides better communication by suppressing the acoustic noise to a larger extent, since it provides a better balance between complexity & convergence speed. In spite of various methods, the results obtained in this way of noise cancellation are optimistic.
{"title":"Inhibition of acoustic noise using an adaptive LMS filter","authors":"R. Vijayaraghavan, N. R. Raajan, P. Sowmiya, A. Ragavi, R. Manoorubini, T. Selvi","doi":"10.1109/ICAEE.2014.6838563","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838563","url":null,"abstract":"In an audio speech signal, acoustic noise is a common problem while the speech is processed. Here, we are going to create color noise and add with an audio signal, after that a model are introduced to eliminate that noise. This paper elaborates a new approach for noise cancellation in speech enhancement using an Adaptive LMS (Least Mean Square) filter and with the help of MATLAB Simulink we get the correct speech signal. This filter is used to remove the acoustic noise due to its simplicity in computation & robust behavior when implemented in finite-precision hardware. It provides better communication by suppressing the acoustic noise to a larger extent, since it provides a better balance between complexity & convergence speed. In spite of various methods, the results obtained in this way of noise cancellation are optimistic.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131109072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838468
Harshal Agarwal, K. Akhil, Vishnu R Unni, N. Ravi, R. Sujith, S. Iqbal, B. Pesala
Thermoacoustic heat engine (TAHE) converts thermal power (heat) into acoustic power. TAHE has been gaining significant interest because of its non-fuel specific, low cost and high reliability (due to reduced moving parts) compared to conventional IC engines. The performance of TAHE depends upon the various parameters such as stack position, stack length and resonator length. Previously, we built a fixed TAHE which converts heat energy to electrical energy with an efficiency of 2 %. However, the performance of the fixed engine was not fully optimized. To investigate further, another novel tunable TAHE has been built with the goal of optimizing the efficiency by tuning three critical parameters, namely stack position, stack length and resonator length. This paper shows the influence of stack parameters (stack position and stack length) and resonator length on the performance of the thermoacoustic heat engine. The performance is measured in terms of the pressure amplitude generated inside the TAHE using air as the working fluid. It is observed that the stack's position considerably affects the performance. Further, from experiments, it is observed that the maximum acoustic power is generated when the stack is positioned closer to a pressure antinode.
{"title":"Performance optimization of tunable standing wave thermoacoustic engine by varying the stack parameters and resonator length: An experimental study","authors":"Harshal Agarwal, K. Akhil, Vishnu R Unni, N. Ravi, R. Sujith, S. Iqbal, B. Pesala","doi":"10.1109/ICAEE.2014.6838468","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838468","url":null,"abstract":"Thermoacoustic heat engine (TAHE) converts thermal power (heat) into acoustic power. TAHE has been gaining significant interest because of its non-fuel specific, low cost and high reliability (due to reduced moving parts) compared to conventional IC engines. The performance of TAHE depends upon the various parameters such as stack position, stack length and resonator length. Previously, we built a fixed TAHE which converts heat energy to electrical energy with an efficiency of 2 %. However, the performance of the fixed engine was not fully optimized. To investigate further, another novel tunable TAHE has been built with the goal of optimizing the efficiency by tuning three critical parameters, namely stack position, stack length and resonator length. This paper shows the influence of stack parameters (stack position and stack length) and resonator length on the performance of the thermoacoustic heat engine. The performance is measured in terms of the pressure amplitude generated inside the TAHE using air as the working fluid. It is observed that the stack's position considerably affects the performance. Further, from experiments, it is observed that the maximum acoustic power is generated when the stack is positioned closer to a pressure antinode.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132863745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838539
S. Jayaprakash, V. Ramakrishnan
This paper presents a Solar based DC-DC converter for armature voltage controlled separately excited motor. The circuit has two full wave converter connected to boost the voltage and also for the power factor correction (PFC) converters. That the two full wave converter is controlled by MOSFET. Output side of Controlled converter is connected to pi filter. Finally separately excited motor is connected to output side. Controlled voltage is applied to the armature of the motor. Speed of motor, Torque and Armature current are measured by experimental. The circuit with all the component parameters operate at zero-voltage switching which retains the high circuit efficiency. A circuit operation and simulation designed for a 220v dc output arrived and tested.
{"title":"Simulation of solar based DC-DC converter for armature voltage controlled separately excited motor","authors":"S. Jayaprakash, V. Ramakrishnan","doi":"10.1109/ICAEE.2014.6838539","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838539","url":null,"abstract":"This paper presents a Solar based DC-DC converter for armature voltage controlled separately excited motor. The circuit has two full wave converter connected to boost the voltage and also for the power factor correction (PFC) converters. That the two full wave converter is controlled by MOSFET. Output side of Controlled converter is connected to pi filter. Finally separately excited motor is connected to output side. Controlled voltage is applied to the armature of the motor. Speed of motor, Torque and Armature current are measured by experimental. The circuit with all the component parameters operate at zero-voltage switching which retains the high circuit efficiency. A circuit operation and simulation designed for a 220v dc output arrived and tested.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128996647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838506
V. Suganthi, L. Madhuridevi, K. Sindhuja
This paper presents the development of a user-friendly animation software for simulating the various power quality problems using LabVIEW. It aids in better grasping of power quality problems and can be used for classroom teaching and tutorials. The proposed software serves as a visual tool which depicts power quality problems, rendering better perception of concepts. The various power quality problems encountered are discussed, followed by an introduction to LabVIEW. Then the operation of the software tool is described, which includes snapshots to demonstrate its execution.
{"title":"Development of software tool for classroom teaching of power quality using LabVIEW","authors":"V. Suganthi, L. Madhuridevi, K. Sindhuja","doi":"10.1109/ICAEE.2014.6838506","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838506","url":null,"abstract":"This paper presents the development of a user-friendly animation software for simulating the various power quality problems using LabVIEW. It aids in better grasping of power quality problems and can be used for classroom teaching and tutorials. The proposed software serves as a visual tool which depicts power quality problems, rendering better perception of concepts. The various power quality problems encountered are discussed, followed by an introduction to LabVIEW. Then the operation of the software tool is described, which includes snapshots to demonstrate its execution.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129053969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838432
S. Venkatesan, T. S. Manipriya, J. Senthil Kumar
Congestion in the transmission network prevents the implementation of the desired market transaction. This paper proposes a new, simple and effective congestion management scheme, which will meet the objective of ISO (Independent System Operator). To relieve congestion, an auction mechanism for interruptible load has been designed and integrated with congestion relief model. The effectiveness of the proposed method is examined for an ISO operating in a bilateral contract, for the real-time selection of interruptible load offer. The IEEE 30-Bus system and Indian 69-Bus utility Bus systems with considering transactions have been used for validation of various case studies.
{"title":"Demand side management based congestion relief model","authors":"S. Venkatesan, T. S. Manipriya, J. Senthil Kumar","doi":"10.1109/ICAEE.2014.6838432","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838432","url":null,"abstract":"Congestion in the transmission network prevents the implementation of the desired market transaction. This paper proposes a new, simple and effective congestion management scheme, which will meet the objective of ISO (Independent System Operator). To relieve congestion, an auction mechanism for interruptible load has been designed and integrated with congestion relief model. The effectiveness of the proposed method is examined for an ISO operating in a bilateral contract, for the real-time selection of interruptible load offer. The IEEE 30-Bus system and Indian 69-Bus utility Bus systems with considering transactions have been used for validation of various case studies.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129568830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838433
Saad Zafar, Raviteja Adapa
The Fast Inverse Square Root algorithm has been used in 3D games of past for lighting and reflection calculations, because it offers up to four times performance gains. This paper presents a hardware implementation of the algorithm on an FPGA board by designing the complete architecture and successfully mapping it on Xilinx Spartan 3E after thorough functional verification. The results show that this implementation provides a very efficient single-precision floating point inverse square root calculator with practically accurate results being made available after just 12 short clock cycles. This performance measure is far superior to the software counterpart of the algorithm, and is not processor dependent like rsqrtss of x86 SSE instruction set. Results of this work can aid FPGA based vector processors or graphic processing units with 3D rendering. The hardware design can also form part of a larger floating point arithmetic unit for dedicated reciprocal square root calculations.
Fast Inverse Square Root算法在过去的3D游戏中用于照明和反射计算，因为它提供了高达四倍的性能提升。本文给出了该算法在FPGA板上的硬件实现，设计了完整的架构，并经过全面的功能验证，成功地将其映射到Xilinx Spartan 3E上。结果表明，该实现提供了一个非常高效的单精度浮点平方根反计算器，只需12个短时钟周期即可获得几乎准确的结果。这种性能度量远远优于该算法的软件对应，并且不像x86 SSE指令集的rsqrtss那样依赖于处理器。这项工作的结果可以帮助基于FPGA的矢量处理器或图形处理单元进行3D渲染。硬件设计也可以构成一个更大的浮点运算单元的一部分，用于专用的倒数平方根计算。
{"title":"Hardware architecture design and mapping of ‘Fast Inverse Square Root’ algorithm","authors":"Saad Zafar, Raviteja Adapa","doi":"10.1109/ICAEE.2014.6838433","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838433","url":null,"abstract":"The Fast Inverse Square Root algorithm has been used in 3D games of past for lighting and reflection calculations, because it offers up to four times performance gains. This paper presents a hardware implementation of the algorithm on an FPGA board by designing the complete architecture and successfully mapping it on Xilinx Spartan 3E after thorough functional verification. The results show that this implementation provides a very efficient single-precision floating point inverse square root calculator with practically accurate results being made available after just 12 short clock cycles. This performance measure is far superior to the software counterpart of the algorithm, and is not processor dependent like rsqrtss of x86 SSE instruction set. Results of this work can aid FPGA based vector processors or graphic processing units with 3D rendering. The hardware design can also form part of a larger floating point arithmetic unit for dedicated reciprocal square root calculations.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134405382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838458
G. Saramekala, S. Jit, P. Tiwari
Recessed-Source/Drain (Re-S/D) SOI (Silicon on Insulator) MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) offer higher drain current compare to conventional SOI MOSFETs which may be attributed to large source and drain area in recessed S/D devices. The concept of dual-metal-gate has already been incorporated in the recessed S/D SOI MOSFETs by our group and the devices have been named as Re-S/D fully-depleted (FD) SOI MOSFETs. In this work, 2D numerical simulations have been carried out to study the electrical characteristics like surface potential, threshold voltage and drain current of Re-S/D FD SOI MOSFETs. Device parameters like the depth of S/D in the buried oxide and gate length ratio are varied to access their impact on the surface potential, threshold voltage and drain current. All these numerical simulation results are obtained from ATLAS™, a 2-D numerical device simulator from SILVACO Inc.
与传统的SOI mosfet相比，嵌入式源极/漏极(Re-S/D) SOI(绝缘体上硅)mosfet(金属氧化物半导体场效应晶体管)提供更高的漏极电流，这可能归因于嵌入式S/D器件中的大源极和漏极面积。双金属栅极的概念已经被我们的团队整合到嵌入式S/D SOI mosfet中，这些器件被命名为Re-S/D全耗尽(FD) SOI mosfet。本文通过二维数值模拟研究了Re-S/D FD SOI mosfet的表面电位、阈值电压和漏极电流等电特性。改变埋地氧化物中S/D深度和栅极长度比等器件参数，以获得它们对表面电位、阈值电压和漏极电流的影响。所有这些数值模拟结果均来自SILVACO公司的二维数值器件模拟器ATLAS™。
{"title":"ATLAS™ based simulation study of the electrical characteristics of dual-metal-gate (DMG) fully-depleted (FD) recessed-source/drain (Re-S/D) SOI MOSFETs","authors":"G. Saramekala, S. Jit, P. Tiwari","doi":"10.1109/ICAEE.2014.6838458","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838458","url":null,"abstract":"Recessed-Source/Drain (Re-S/D) SOI (Silicon on Insulator) MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) offer higher drain current compare to conventional SOI MOSFETs which may be attributed to large source and drain area in recessed S/D devices. The concept of dual-metal-gate has already been incorporated in the recessed S/D SOI MOSFETs by our group and the devices have been named as Re-S/D fully-depleted (FD) SOI MOSFETs. In this work, 2D numerical simulations have been carried out to study the electrical characteristics like surface potential, threshold voltage and drain current of Re-S/D FD SOI MOSFETs. Device parameters like the depth of S/D in the buried oxide and gate length ratio are varied to access their impact on the surface potential, threshold voltage and drain current. All these numerical simulation results are obtained from ATLAS™, a 2-D numerical device simulator from SILVACO Inc.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125661893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838477
K. Deepa, R. Jeyanthi, Shweta Mohan, M. Kumar
DC-DC converters can be viewed as dc transformers that deliver a DC-DC voltage or current at a different level than the input source. The unregulated DC voltage is converted into regulated DC voltage at required level under varying load and input voltage condition. The control of output voltage is performed in a closed loop using the principle of negative feedback.The fuzzy logic controller for DC-DC converters i.e. Fly-Back Converter offers an alternative way to implement a central action that exploits the inherent variable structure nature of converter. The controller acts fast to changes in the converter output voltage producing good load regulation. This control technique offers converter stability for robustness, good dynamic response and implementation is simple. Hence, this paper is the result of an attempt to design aDC-DC Fly-Back Converter and an FLC for the same. The paper also draws a comparison between a conventional PI and fuzzy controllers for the aforementioned converter.
dc - dc变换器可以看作是提供与输入源不同水平的dc - dc电压或电流的直流变压器。在负载和输入电压变化的情况下，将不稳定的直流电压转换为所需的稳压直流电压。输出电压的控制是利用负反馈原理在闭环中进行的。用于DC-DC变换器即反激变换器的模糊逻辑控制器提供了一种利用变换器固有的可变结构特性来实现中心动作的替代方法。控制器对变换器输出电压的变化反应迅速，产生良好的负载调节效果。该控制方法具有稳健性好、动态响应好、实现简单等优点。因此，本文是尝试设计aDC-DC反激变换器和FLC的结果。本文还对上述变换器的传统PI控制器和模糊控制器进行了比较。
{"title":"Fuzzy based flyback converter","authors":"K. Deepa, R. Jeyanthi, Shweta Mohan, M. Kumar","doi":"10.1109/ICAEE.2014.6838477","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838477","url":null,"abstract":"DC-DC converters can be viewed as dc transformers that deliver a DC-DC voltage or current at a different level than the input source. The unregulated DC voltage is converted into regulated DC voltage at required level under varying load and input voltage condition. The control of output voltage is performed in a closed loop using the principle of negative feedback.The fuzzy logic controller for DC-DC converters i.e. Fly-Back Converter offers an alternative way to implement a central action that exploits the inherent variable structure nature of converter. The controller acts fast to changes in the converter output voltage producing good load regulation. This control technique offers converter stability for robustness, good dynamic response and implementation is simple. Hence, this paper is the result of an attempt to design aDC-DC Fly-Back Converter and an FLC for the same. The paper also draws a comparison between a conventional PI and fuzzy controllers for the aforementioned converter.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124596957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838487
M. Subbarao, C. Sai Babu, S. Satyanarayana, S. S. Kumar
The control technique presented in this paper -Peak Current Mode Control is a simplified power factor correction (PFC) technique for single stage AC/DC converters, By using low cost standard PWM control IC's implementation becomes easy for this controller. In this paper Integrated buck-fly back converter (IBFC) is a single stage AC/DC converter, operating in discontinuous conduction mode (DCM) to achieve high Power factor with fast output voltage regulation. Comparative analysis of Peak current mode controller to hysteresis current controller for 90-230V input, 48V Output and 200W ac-dc converter operating at 100 kHz is presented and MATLAB/SIMULINK is used for implementation and simulation results show the performance improvement of proposed controller.
{"title":"Analysis and design of Peak Current controlled IBFC for high power factor and tight voltage regulation","authors":"M. Subbarao, C. Sai Babu, S. Satyanarayana, S. S. Kumar","doi":"10.1109/ICAEE.2014.6838487","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838487","url":null,"abstract":"The control technique presented in this paper -Peak Current Mode Control is a simplified power factor correction (PFC) technique for single stage AC/DC converters, By using low cost standard PWM control IC's implementation becomes easy for this controller. In this paper Integrated buck-fly back converter (IBFC) is a single stage AC/DC converter, operating in discontinuous conduction mode (DCM) to achieve high Power factor with fast output voltage regulation. Comparative analysis of Peak current mode controller to hysteresis current controller for 90-230V input, 48V Output and 200W ac-dc converter operating at 100 kHz is presented and MATLAB/SIMULINK is used for implementation and simulation results show the performance improvement of proposed controller.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"57 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114041086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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