Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838565
S. Aravind Babu, S. Babu Ramki, K. Sivasankaran
This paper presents an error compensation bias circuit added to a modified encoded booth multiplier to produce a high accuracy fixed-width multiplier. Fixed-width multiplier is employed in many digital signal processing applications, as most of these systems employ iterative structures with fixed precision. The design has been implemented in TSMC 180nm technology. The design is 14.6% faster than the fixed-width multipliers. The design has 37.2% less truncation error as compared to direct truncated fixed width multiplier (DTFM). The design is embedded with operand isolator technique to ensure low power operation when employed in DSP applications.
{"title":"Design and implementation of high speed and high accuracy fixed-width modified booth multiplier for DSP application","authors":"S. Aravind Babu, S. Babu Ramki, K. Sivasankaran","doi":"10.1109/ICAEE.2014.6838565","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838565","url":null,"abstract":"This paper presents an error compensation bias circuit added to a modified encoded booth multiplier to produce a high accuracy fixed-width multiplier. Fixed-width multiplier is employed in many digital signal processing applications, as most of these systems employ iterative structures with fixed precision. The design has been implemented in TSMC 180nm technology. The design is 14.6% faster than the fixed-width multipliers. The design has 37.2% less truncation error as compared to direct truncated fixed width multiplier (DTFM). The design is embedded with operand isolator technique to ensure low power operation when employed in DSP applications.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127791413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838478
A. Gopi, D. Elangovan, R. Saravanakumar
This paper proposes a approach to obtain a high step-up voltage with zero voltage switching (ZVS) with an isolated type DC-DC converter. The entire setup consists of a full bridge converter which utilised proposed phase shift technique and voltage doubler on the output side. The converter operated at 20kHz switching frequency which is high enough to improve the efficiency. Ferrite core transformer is used in place of ordinary air core transformer. Which is small in size with number of turns of the transformer is reduced and the overall power density is increased. The proposed doubler circuit consists of electrolytic capacitors, which are rated at 400V. This circuit results in cost savings of more than 50% in the price of the electrolytic filter capacitors. The circuits were simulated using PSIM software for an input voltage of 200V, an output of 800V obtained. And it is validated with the low power hardware model.
{"title":"Soft-switched high step-up DC-dc converter with voltage doubler","authors":"A. Gopi, D. Elangovan, R. Saravanakumar","doi":"10.1109/ICAEE.2014.6838478","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838478","url":null,"abstract":"This paper proposes a approach to obtain a high step-up voltage with zero voltage switching (ZVS) with an isolated type DC-DC converter. The entire setup consists of a full bridge converter which utilised proposed phase shift technique and voltage doubler on the output side. The converter operated at 20kHz switching frequency which is high enough to improve the efficiency. Ferrite core transformer is used in place of ordinary air core transformer. Which is small in size with number of turns of the transformer is reduced and the overall power density is increased. The proposed doubler circuit consists of electrolytic capacitors, which are rated at 400V. This circuit results in cost savings of more than 50% in the price of the electrolytic filter capacitors. The circuits were simulated using PSIM software for an input voltage of 200V, an output of 800V obtained. And it is validated with the low power hardware model.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124605270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838476
K. Deepa, P. Padmaja, M. Vijaya Kumar
Multi-output DC-DC converters are widely used in many applications such as military, communication automobile, space application etc.. The DC-DC converters which is used for aerospace applications, has important role in ensuring the complete success of the mission. DC-DC converter is used for providing a regulated voltage to various subsystems of satellites with variation in input voltage and output resistive load. Different types of DC-DC converters were analyzed and out of all DC-DC converters, push-pull converter achieves tight regulation in the output voltage, So a push-pull converter for low power is designed for providing regulated power supply to the spacecraft. This paper deals with the design and closed loop implementation details of cascoded multi output push-pull converter with PWM controller IC (UC 3825). The results obtained in simulation and hardware implementation is presented and analyzed in detail for 9W, 50 kHz laboratory prototype developed.
{"title":"Cascoded multi output push-pull converter","authors":"K. Deepa, P. Padmaja, M. Vijaya Kumar","doi":"10.1109/ICAEE.2014.6838476","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838476","url":null,"abstract":"Multi-output DC-DC converters are widely used in many applications such as military, communication automobile, space application etc.. The DC-DC converters which is used for aerospace applications, has important role in ensuring the complete success of the mission. DC-DC converter is used for providing a regulated voltage to various subsystems of satellites with variation in input voltage and output resistive load. Different types of DC-DC converters were analyzed and out of all DC-DC converters, push-pull converter achieves tight regulation in the output voltage, So a push-pull converter for low power is designed for providing regulated power supply to the spacecraft. This paper deals with the design and closed loop implementation details of cascoded multi output push-pull converter with PWM controller IC (UC 3825). The results obtained in simulation and hardware implementation is presented and analyzed in detail for 9W, 50 kHz laboratory prototype developed.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121243560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838567
Gargee Bhattacharyya, Sharmistha Shee, P. Dutta, S. Sarkar
Work function engineering with continuous horizontal mole fraction variation in a binary metal alloy gate has been proposed already on silicon on nothing (SON) MOSFET. Presently, concept of work function engineering by mole fraction variation along both vertical as well as horizontal direction in a binary alloy gate is applied analytically in our model. Effects of this vertical mole fraction variation on various device parameters such as threshold voltage, drain current, transconductance, drain conductance and voltage gain are studied and compared with the model suggested by Manna et al. and an improvement of overall performance has been observed.
{"title":"Influence of mole fraction variation of binary metal gate on SON MOSFET device performance","authors":"Gargee Bhattacharyya, Sharmistha Shee, P. Dutta, S. Sarkar","doi":"10.1109/ICAEE.2014.6838567","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838567","url":null,"abstract":"Work function engineering with continuous horizontal mole fraction variation in a binary metal alloy gate has been proposed already on silicon on nothing (SON) MOSFET. Presently, concept of work function engineering by mole fraction variation along both vertical as well as horizontal direction in a binary alloy gate is applied analytically in our model. Effects of this vertical mole fraction variation on various device parameters such as threshold voltage, drain current, transconductance, drain conductance and voltage gain are studied and compared with the model suggested by Manna et al. and an improvement of overall performance has been observed.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122491296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838450
A. Mishra, P. Richards
Major studies have reported that heart related issues will be a major health risk in developing and developed countries alike. The problem is more acute in developing nations because of the lack of enough trained cardiologists and also because of the high cost of the traditional electro cardio grams (ECGs). In the current work we propose a design for a low-cost and user friendly smartphone based ECG (SmartECG). The major contributions of the work lie in the innovative design of the analog part and in the efficient use of the limited processing power of a smart phone to display and store the ECG, and extract some of the major features from it.
{"title":"SmartECG: An affordable solution for screening cardio-health issues","authors":"A. Mishra, P. Richards","doi":"10.1109/ICAEE.2014.6838450","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838450","url":null,"abstract":"Major studies have reported that heart related issues will be a major health risk in developing and developed countries alike. The problem is more acute in developing nations because of the lack of enough trained cardiologists and also because of the high cost of the traditional electro cardio grams (ECGs). In the current work we propose a design for a low-cost and user friendly smartphone based ECG (SmartECG). The major contributions of the work lie in the innovative design of the analog part and in the efficient use of the limited processing power of a smart phone to display and store the ECG, and extract some of the major features from it.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126300799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838470
P. Sathya, R. Natarajan
Electricity demand is prevailing all over the world now and energy management becomes very complex. This paper aims at providing solution for power demand and energy management by using HB white LED lights for domestic applications. LED lights consume very less power and gives out high energy in the form of brightness. A laboratory model is created in DIALUX 4.11 using CAD window and is illuminated with LED lights. Photometric measurements and energy evaluation are done for the laboratory model with room components of different construction materials in the presence of LED lighting. Reflectivity of different materials under illumination is determined. Simulation is done for varying brightness and calculated results are carried over to Pov-Ray 3.6 for determining the real lighting appearance of the laboratory model. Energy evaluation is done for a year and photometric values of lighting system are measured. The calculated results proves that LED lighting system can be used as an efficient lighting system for domestic purposes when compared to other lighting systems. Simulated results and photometric values of LED lighting are presented here.
{"title":"Energy estimation and photometric measurements of LED lighting in laboratory","authors":"P. Sathya, R. Natarajan","doi":"10.1109/ICAEE.2014.6838470","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838470","url":null,"abstract":"Electricity demand is prevailing all over the world now and energy management becomes very complex. This paper aims at providing solution for power demand and energy management by using HB white LED lights for domestic applications. LED lights consume very less power and gives out high energy in the form of brightness. A laboratory model is created in DIALUX 4.11 using CAD window and is illuminated with LED lights. Photometric measurements and energy evaluation are done for the laboratory model with room components of different construction materials in the presence of LED lighting. Reflectivity of different materials under illumination is determined. Simulation is done for varying brightness and calculated results are carried over to Pov-Ray 3.6 for determining the real lighting appearance of the laboratory model. Energy evaluation is done for a year and photometric values of lighting system are measured. The calculated results proves that LED lighting system can be used as an efficient lighting system for domestic purposes when compared to other lighting systems. Simulated results and photometric values of LED lighting are presented here.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"435 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126471396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838429
T. P. J. Baswam, B. Harshavardhan, E. Venkata Ramesh
This paper proposes Flash Analog to Digital Converter design that reduces static nonlinearity of the track & hold circuit, by that high speed and high linearity obtained at the same time. Comparator is designed using latch type voltage sense amplifier. The sense amplifier is designed with separated input and regeneration stage. This separation offers fast operation over a wide common mode and supply voltage range. Apart from sense amplifier this Analog to Digital converter design uses Thermometer code generator circuit followed by encoder. The input is sampled and held by (S/H) circuit so that there is no need to use bubble correction logic in the design.
{"title":"A distortion compensating flash Analog-to-Digital conversion using bootstrap switch","authors":"T. P. J. Baswam, B. Harshavardhan, E. Venkata Ramesh","doi":"10.1109/ICAEE.2014.6838429","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838429","url":null,"abstract":"This paper proposes Flash Analog to Digital Converter design that reduces static nonlinearity of the track & hold circuit, by that high speed and high linearity obtained at the same time. Comparator is designed using latch type voltage sense amplifier. The sense amplifier is designed with separated input and regeneration stage. This separation offers fast operation over a wide common mode and supply voltage range. Apart from sense amplifier this Analog to Digital converter design uses Thermometer code generator circuit followed by encoder. The input is sampled and held by (S/H) circuit so that there is no need to use bubble correction logic in the design.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132894944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838463
D. Basak, K. L. Baishnab, Fradaric Joseph
In this paper we employed Winner Take All (WTA) circuit for sensing the bit line capacitance. It is an important block in hardware realization of neural networks. The property of a neural logic of selection of the highest intensity signal amongst competing signals highly fits for our design of amplifying the voltage difference between bit lines quickly. A comparative study is done to show the better performance of our proposed design compared to the conventional cross-coupled amplifier. The design and simulation is carried out in Cadence virtuoso platform with UMC 0.18μm process technology.
{"title":"Reduced access time with WTA sense amplifier for standard CMOS SRAM cell","authors":"D. Basak, K. L. Baishnab, Fradaric Joseph","doi":"10.1109/ICAEE.2014.6838463","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838463","url":null,"abstract":"In this paper we employed Winner Take All (WTA) circuit for sensing the bit line capacitance. It is an important block in hardware realization of neural networks. The property of a neural logic of selection of the highest intensity signal amongst competing signals highly fits for our design of amplifying the voltage difference between bit lines quickly. A comparative study is done to show the better performance of our proposed design compared to the conventional cross-coupled amplifier. The design and simulation is carried out in Cadence virtuoso platform with UMC 0.18μm process technology.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121550078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838444
A. Khasnobish, Shreyasi Datta, Monalisa Pal, A. Konar, D. Tibarewala, R. Janarthanan
Touch perception can be decoded from brain signals as well as from tactile pressure signals obtained while holding objects using a sensor. The present work aims to classify object shapes from EEG signals and tactile pressure signals obtained from a capacitive tactile sensor while exploring objects of different shapes; thereby drawing a mutual relation or dependence between these two sources of haptic information in response to the same tactile stimuli. It is evident from the classification results that object-shapes can be classified efficiently from both EEG and tactile signals with mean classification accuracy of 74.21% and 97.12% respectively. Correlation analysis using various metrics show that EEG and tactile signals are non- linearly correlated and only a very small amount of non linear correlation exists. The polynomial fitting of EEG signals on tactile signals depicts that in absence of brain signals tactile signals can successfully predict the corresponding EEG signals.
{"title":"Correlation analysis of object shape recognition from EEG and tactile signals","authors":"A. Khasnobish, Shreyasi Datta, Monalisa Pal, A. Konar, D. Tibarewala, R. Janarthanan","doi":"10.1109/ICAEE.2014.6838444","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838444","url":null,"abstract":"Touch perception can be decoded from brain signals as well as from tactile pressure signals obtained while holding objects using a sensor. The present work aims to classify object shapes from EEG signals and tactile pressure signals obtained from a capacitive tactile sensor while exploring objects of different shapes; thereby drawing a mutual relation or dependence between these two sources of haptic information in response to the same tactile stimuli. It is evident from the classification results that object-shapes can be classified efficiently from both EEG and tactile signals with mean classification accuracy of 74.21% and 97.12% respectively. Correlation analysis using various metrics show that EEG and tactile signals are non- linearly correlated and only a very small amount of non linear correlation exists. The polynomial fitting of EEG signals on tactile signals depicts that in absence of brain signals tactile signals can successfully predict the corresponding EEG signals.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114784145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-19DOI: 10.1109/ICAEE.2014.6838545
T. Prem Sai, S. Ambica Sony, A. Sumathi, S. Umasankar
Transformerless inverters are becoming popular, especially in the field of renewable energy systems because of their compactness in size and higher efficiency. However these topologies are suffering from leakage currents and they can be reduced by clamping the neutral point during freewheeling modes. Two types of basic switching cells are introduced to build the proposed topology. They are positive neutral point clamping cell and negative neutral point clamping cell. Using these two cells proposed topology is clearly explained. In this paper unipolar sinusoidal pulse width modulation (UPSPWM) which is already existing and modified unipolar sinusoidal pulse width modulation (MUPSPWM) which is proposed to these topologies for getting an improved result. These two types used for creating switching pulse pattern for all topologies and then obtained results are compared in respect of THD. Existing topologies like OH5 and full bridge dc bypass (FB-DCBP) are also simulated with both PWM techniques and their results are compared to proposed topology in respect of total harmonic distortion (T.H.D) and number of switches. Results showing in this paper are validated by simulating with MATLAB.
{"title":"Transformerless full bridge neutral point clamped inverter topology for renewable energy sources","authors":"T. Prem Sai, S. Ambica Sony, A. Sumathi, S. Umasankar","doi":"10.1109/ICAEE.2014.6838545","DOIUrl":"https://doi.org/10.1109/ICAEE.2014.6838545","url":null,"abstract":"Transformerless inverters are becoming popular, especially in the field of renewable energy systems because of their compactness in size and higher efficiency. However these topologies are suffering from leakage currents and they can be reduced by clamping the neutral point during freewheeling modes. Two types of basic switching cells are introduced to build the proposed topology. They are positive neutral point clamping cell and negative neutral point clamping cell. Using these two cells proposed topology is clearly explained. In this paper unipolar sinusoidal pulse width modulation (UPSPWM) which is already existing and modified unipolar sinusoidal pulse width modulation (MUPSPWM) which is proposed to these topologies for getting an improved result. These two types used for creating switching pulse pattern for all topologies and then obtained results are compared in respect of THD. Existing topologies like OH5 and full bridge dc bypass (FB-DCBP) are also simulated with both PWM techniques and their results are compared to proposed topology in respect of total harmonic distortion (T.H.D) and number of switches. Results showing in this paper are validated by simulating with MATLAB.","PeriodicalId":151739,"journal":{"name":"2014 International Conference on Advances in Electrical Engineering (ICAEE)","volume":"750 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122970016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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