Pub Date : 1996-02-12DOI: 10.1109/MNNFS.1996.493788
B. Girau, Arnaud Tisserand
A digital hardware implementation of a whole neural network learning is described. It uses on-line arithmetic on FPGAs. The modularity of our solution avoids the development problems that occur with more usual hardware circuits. A precise analysis of the computations required by the back-propagation algorithm allows us to maximize the parallism of our implementation.
{"title":"On-line arithmetic-based reprogrammable hardware implementation of multilayer perceptron back-propagation","authors":"B. Girau, Arnaud Tisserand","doi":"10.1109/MNNFS.1996.493788","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493788","url":null,"abstract":"A digital hardware implementation of a whole neural network learning is described. It uses on-line arithmetic on FPGAs. The modularity of our solution avoids the development problems that occur with more usual hardware circuits. A precise analysis of the computations required by the back-propagation algorithm allows us to maximize the parallism of our implementation.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"979 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123313421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-12DOI: 10.1109/MNNFS.1996.493815
A.P. Maubant, Y. Autret, G. Leonhard, G. Ouvradou, A. Thépaut
This paper presents neural and hybrid (symbolic and subsymbolic) applications downloaded on the distributed computer architecture ArMenX. This machine is articulated around a ring of FPGAs acting as routing resources as well as fine grain computing resources and thus giving great flexibility. More coarse grain computing resources-Transputer and DSP-tightly coupled via FPGAs give a large application spectrum to the machine, making it possible to implement heterogeneous algorithms efficiently involving both low level (computing intensive) and high level (control intensive) tasks. We first introduce the ArMenX project and the main architecture features. Then, after giving details on the computing of propagation and back-propagation of the multi-layer perceptron on ArMenX, we will focus on a handwritten digit (issued from a zip code data base) recognition application. An original and efficient method, involving three neural networks, is developed. The first two neural networks deal with the 'reading process', and the last neural network, which learned to write, helps to make decisions on the first two network outputs, when they are not confident. Before concluding, the paper presents the work of integration of ArMenX into a high level programming environment, designed to make it easier to take advantage of the architecture flexibility.
{"title":"An efficient handwritten digit recognition method on a flexible parallel architecture","authors":"A.P. Maubant, Y. Autret, G. Leonhard, G. Ouvradou, A. Thépaut","doi":"10.1109/MNNFS.1996.493815","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493815","url":null,"abstract":"This paper presents neural and hybrid (symbolic and subsymbolic) applications downloaded on the distributed computer architecture ArMenX. This machine is articulated around a ring of FPGAs acting as routing resources as well as fine grain computing resources and thus giving great flexibility. More coarse grain computing resources-Transputer and DSP-tightly coupled via FPGAs give a large application spectrum to the machine, making it possible to implement heterogeneous algorithms efficiently involving both low level (computing intensive) and high level (control intensive) tasks. We first introduce the ArMenX project and the main architecture features. Then, after giving details on the computing of propagation and back-propagation of the multi-layer perceptron on ArMenX, we will focus on a handwritten digit (issued from a zip code data base) recognition application. An original and efficient method, involving three neural networks, is developed. The first two neural networks deal with the 'reading process', and the last neural network, which learned to write, helps to make decisions on the first two network outputs, when they are not confident. Before concluding, the paper presents the work of integration of ArMenX into a high level programming environment, designed to make it easier to take advantage of the architecture flexibility.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131459951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-12DOI: 10.1109/MNNFS.1996.493777
T. Shibata, M. Konda, Y. Yamashita, T. Nakai, T. Ohmi
Neuron MOS transistor (/spl upsi/MOS) mimicking the fundamental behavior of neurons at a very primitive device level has been applied to construct a real-time event recognition hardware. A neuron MOS associator searches for the most similar event in the past memory to the current event based on Manhattan distance calculation and the minimum distance search by a winner take all (WTA) circuitry in a fully parallel architecture. A unique floating-gate analog EEPROM technology has been developed to build a vast memory system storing the events in the past. Test circuits of key subsystems were fabricated by a double-polysilicon CMOS process and their operation was verified by measurements as well as by simulation. As a simple application of the basic architecture, a motion-vector-search hardware was designed and fabricated. The circuit can find out the two-dimensional motion vector in about 150 nsec by a very simple circuitry.
{"title":"Neuron-MOS-based association hardware for real-time event recognition","authors":"T. Shibata, M. Konda, Y. Yamashita, T. Nakai, T. Ohmi","doi":"10.1109/MNNFS.1996.493777","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493777","url":null,"abstract":"Neuron MOS transistor (/spl upsi/MOS) mimicking the fundamental behavior of neurons at a very primitive device level has been applied to construct a real-time event recognition hardware. A neuron MOS associator searches for the most similar event in the past memory to the current event based on Manhattan distance calculation and the minimum distance search by a winner take all (WTA) circuitry in a fully parallel architecture. A unique floating-gate analog EEPROM technology has been developed to build a vast memory system storing the events in the past. Test circuits of key subsystems were fabricated by a double-polysilicon CMOS process and their operation was verified by measurements as well as by simulation. As a simple application of the basic architecture, a motion-vector-search hardware was designed and fabricated. The circuit can find out the two-dimensional motion vector in about 150 nsec by a very simple circuitry.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"36 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132154182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-12DOI: 10.1109/MNNFS.1996.493800
Valeriu Beiu, J.G. Taylor
The paper overviews recent developments of a VLSI-friendly, constructive algorithm as well as detailing two extensions. The problem is to construct a neural network when m examples of n inputs are given (classification problem). The two extensions discussed are: (i) the use of analog comparators; and (ii) digital as well as analog solution to XOR-like problems. For a simple example (the two-spirals), we are able to show that the algorithm does a very "efficient" encoding of a given problem into the neural network it "builds"-when compared to the entropy of the given problem and to other learning algorithms. We are also able to estimate the number of bits needed to solve any classification problem for the general case. Being interested in the VLSI implementation of such networks, the optimum criteria are not only the classical size and depth, but also the connectivity and the number of bits for representing the weights-as such measures are closer estimates of the area and lead to better approximations of the AT/sup 2/.
{"title":"Direct synthesis of neural networks","authors":"Valeriu Beiu, J.G. Taylor","doi":"10.1109/MNNFS.1996.493800","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493800","url":null,"abstract":"The paper overviews recent developments of a VLSI-friendly, constructive algorithm as well as detailing two extensions. The problem is to construct a neural network when m examples of n inputs are given (classification problem). The two extensions discussed are: (i) the use of analog comparators; and (ii) digital as well as analog solution to XOR-like problems. For a simple example (the two-spirals), we are able to show that the algorithm does a very \"efficient\" encoding of a given problem into the neural network it \"builds\"-when compared to the entropy of the given problem and to other learning algorithms. We are also able to estimate the number of bits needed to solve any classification problem for the general case. Being interested in the VLSI implementation of such networks, the optimum criteria are not only the classical size and depth, but also the connectivity and the number of bits for representing the weights-as such measures are closer estimates of the area and lead to better approximations of the AT/sup 2/.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133145465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-12DOI: 10.1109/MNNFS.1996.493801
R. Dogaru, A. Murgan, S. Ortmann, M. Glesner
A modified RBF neural network model is proposed allowing efficient VLSI implementation in both analog or digital technology. This model is based essentially on replacing the standard Gaussian basis function with a piece-wise linear one and on using a fast allocation unit learning algorithm for determination of unit centers. The modified RBF approximates optimally Gaussians for the whole range of parameters (radius and distance). The learning algorithm is fully on-line and easy to be implemented in VLSI using the proposed neural structures for on-line signal processing tasks. Applying the standard test problem of the chaotic time series prediction, the functional performances of different RBF networks were compared. Experimental results show that the proposed architecture outperforms the standard RBF networks, the main advantages being related with low hardware requirements and fast learning while the learning algorithm can be also efficient embedded in silicon. A suggestion for current-mode implementation is presented together with considerations regarding the computational requirements of the proposed model for digital implementations.
{"title":"A modified RBF neural network for efficient current-mode VLSI implementation","authors":"R. Dogaru, A. Murgan, S. Ortmann, M. Glesner","doi":"10.1109/MNNFS.1996.493801","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493801","url":null,"abstract":"A modified RBF neural network model is proposed allowing efficient VLSI implementation in both analog or digital technology. This model is based essentially on replacing the standard Gaussian basis function with a piece-wise linear one and on using a fast allocation unit learning algorithm for determination of unit centers. The modified RBF approximates optimally Gaussians for the whole range of parameters (radius and distance). The learning algorithm is fully on-line and easy to be implemented in VLSI using the proposed neural structures for on-line signal processing tasks. Applying the standard test problem of the chaotic time series prediction, the functional performances of different RBF networks were compared. Experimental results show that the proposed architecture outperforms the standard RBF networks, the main advantages being related with low hardware requirements and fast learning while the learning algorithm can be also efficient embedded in silicon. A suggestion for current-mode implementation is presented together with considerations regarding the computational requirements of the proposed model for digital implementations.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116102622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-12DOI: 10.1109/MNNFS.1996.493769
T. Morris, S. DeWeerth
In this paper we present analog very large-scale integrated (aVLSI) circuits that facilitate the selection process for initiating and mediating attentive visual processing. We demonstrate the performance of these circuits within a system that implements covert attentional shifts based on an input array that represents saliency across the visual field. The selection process, which enables the transition from preattentive to attentive processing, uses knowledge of previous selections and appropriate duration of selections to perform its task. The circuitry uses local feedback to create a hysteretic effect in the switching from one location of attention to the next. We also include an inhibition-of-return mechanism to facilitate shifting the location of attention even when the input array remains constant. We present test data from a one-dimensional version of the system.
{"title":"Analog VLSI circuits for covert attentional shifts","authors":"T. Morris, S. DeWeerth","doi":"10.1109/MNNFS.1996.493769","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493769","url":null,"abstract":"In this paper we present analog very large-scale integrated (aVLSI) circuits that facilitate the selection process for initiating and mediating attentive visual processing. We demonstrate the performance of these circuits within a system that implements covert attentional shifts based on an input array that represents saliency across the visual field. The selection process, which enables the transition from preattentive to attentive processing, uses knowledge of previous selections and appropriate duration of selections to perform its task. The circuitry uses local feedback to create a hysteretic effect in the switching from one location of attention to the next. We also include an inhibition-of-return mechanism to facilitate shifting the location of attention even when the input array remains constant. We present test data from a one-dimensional version of the system.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123206011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-12DOI: 10.1109/MNNFS.1996.493767
G. Indiveri, J. Kramer, C. Koch
We present three different architectures that make use of analog VLSI velocity sensors for detecting the focus of expansion, time to contact and motion discontinuities respectively. For each of the architectures proposed we describe the functionality of their component modules and their principles of operation. Data measurements obtained from the VLSI chips developed demonstrate their correct performance and their limits of operation.
{"title":"System implementations of analog VLSI velocity sensors","authors":"G. Indiveri, J. Kramer, C. Koch","doi":"10.1109/MNNFS.1996.493767","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493767","url":null,"abstract":"We present three different architectures that make use of analog VLSI velocity sensors for detecting the focus of expansion, time to contact and motion discontinuities respectively. For each of the architectures proposed we describe the functionality of their component modules and their principles of operation. Data measurements obtained from the VLSI chips developed demonstrate their correct performance and their limits of operation.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123763478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-12DOI: 10.1109/MNNFS.1996.493813
M. Diepenhorst, W. Jansen, J. Nijhuis, M. Schreiner, L. Spaanenburg, A. Ypma
Time-delay neural networks are well-suited for prediction purposes. A particular implementation is the Finite Impulse Response neural net. The GREMLIN architecture is introduced to accommodate such networks. It can be micropipelined to achieve a 85 MCPS performance on a conventional connection-serial structure and allows from its Logic-Enhance Memory nature an easily parametrized design. A typical design for biomedical applications can be trained in a Cascade fashion and subsequently mapped.
{"title":"Using the GREMLIN for digital FIR networks","authors":"M. Diepenhorst, W. Jansen, J. Nijhuis, M. Schreiner, L. Spaanenburg, A. Ypma","doi":"10.1109/MNNFS.1996.493813","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493813","url":null,"abstract":"Time-delay neural networks are well-suited for prediction purposes. A particular implementation is the Finite Impulse Response neural net. The GREMLIN architecture is introduced to accommodate such networks. It can be micropipelined to achieve a 85 MCPS performance on a conventional connection-serial structure and allows from its Logic-Enhance Memory nature an easily parametrized design. A typical design for biomedical applications can be trained in a Cascade fashion and subsequently mapped.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"2010 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127352049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-12DOI: 10.1109/MNNFS.1996.493810
M. Rossmann, B. Hesse, K. Goser, A. Buhlmeier, G. Manteuffel
This paper presents the implementation of a biologically inspired neuron-model. Learning is performed on-line in special synapses based on the biologically proved Hebbian learning algorithm. This algorithm is implemented on-chip allowing an architecture of autonomous neural units. The algorithm is transparent so connections between the neurons can easily be engineered. Due to their functionality and their flexibility only few neurons are needed to fulfil basic tasks. A parallel and a serial concept for an implementation in an FPGA (Field Programmable Gate-Array) are discussed. A prototype of the serial approach is developed in a XILINX FPGA series 3090. This solution has one excitatory, one inhibitory, two Hebbian synapses and one output operating with 8 bit resolution. The internal computation is performed at higher resolution to eliminate errors due to overflow. The Hebbian weights are stored at a precision of 19 bit for multiplication. The prototype works at a clock frequency of 5 MHz leading to an update rate of 333 kCUPS.
{"title":"Implementation of a biologically inspired neuron-model in FPGA","authors":"M. Rossmann, B. Hesse, K. Goser, A. Buhlmeier, G. Manteuffel","doi":"10.1109/MNNFS.1996.493810","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493810","url":null,"abstract":"This paper presents the implementation of a biologically inspired neuron-model. Learning is performed on-line in special synapses based on the biologically proved Hebbian learning algorithm. This algorithm is implemented on-chip allowing an architecture of autonomous neural units. The algorithm is transparent so connections between the neurons can easily be engineered. Due to their functionality and their flexibility only few neurons are needed to fulfil basic tasks. A parallel and a serial concept for an implementation in an FPGA (Field Programmable Gate-Array) are discussed. A prototype of the serial approach is developed in a XILINX FPGA series 3090. This solution has one excitatory, one inhibitory, two Hebbian synapses and one output operating with 8 bit resolution. The internal computation is performed at higher resolution to eliminate errors due to overflow. The Hebbian weights are stored at a precision of 19 bit for multiplication. The prototype works at a clock frequency of 5 MHz leading to an update rate of 333 kCUPS.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129301877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-02-12DOI: 10.1109/MNNFS.1996.493791
M. Chiaberge, E. Miranda Sologuren, L. Reyneri
This paper describes a VLSI device design for low-power neuro-fuzzy computation, which is based on coherent pulse width modulation. The device can implement either multi-layer perceptrons, radial basis functions or fuzzy paradigms. In all cases, weights are stored as a voltage on a pair of capacitors, which are sequentially refreshed by a built-in self-refresh circuit.
{"title":"A low-power Neuro-Fuzzy pulse stream system","authors":"M. Chiaberge, E. Miranda Sologuren, L. Reyneri","doi":"10.1109/MNNFS.1996.493791","DOIUrl":"https://doi.org/10.1109/MNNFS.1996.493791","url":null,"abstract":"This paper describes a VLSI device design for low-power neuro-fuzzy computation, which is based on coherent pulse width modulation. The device can implement either multi-layer perceptrons, radial basis functions or fuzzy paradigms. In all cases, weights are stored as a voltage on a pair of capacitors, which are sequentially refreshed by a built-in self-refresh circuit.","PeriodicalId":151891,"journal":{"name":"Proceedings of Fifth International Conference on Microelectronics for Neural Networks","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122259639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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