Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724427
Mathias Soeken, R. Wille, R. Drechsler
Synthesis of reversible circuits is an important research area providing the basis for a design flow of this emerging technology. Recently, in the development of scalable synthesis approaches a significant step forward has been made by a hierarchical method in combination with Shannon decom-position. However, this approach leads to circuits with high costs. In this paper, we propose an alternative that additionally makes use of positive Davio and negative Davio decomposition. We show that the usage of these decomposition types offers several advantages for the synthesis of reversible circuits. Using the proposed approach, on average the number of lines can be reduced by 22%, the number of gates by 22%, and the quantum cost by 32%. In the best case, even reductions of more than 60% are possible.
{"title":"Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition","authors":"Mathias Soeken, R. Wille, R. Drechsler","doi":"10.1109/IDT.2010.5724427","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724427","url":null,"abstract":"Synthesis of reversible circuits is an important research area providing the basis for a design flow of this emerging technology. Recently, in the development of scalable synthesis approaches a significant step forward has been made by a hierarchical method in combination with Shannon decom-position. However, this approach leads to circuits with high costs. In this paper, we propose an alternative that additionally makes use of positive Davio and negative Davio decomposition. We show that the usage of these decomposition types offers several advantages for the synthesis of reversible circuits. Using the proposed approach, on average the number of lines can be reduced by 22%, the number of gates by 22%, and the quantum cost by 32%. In the best case, even reductions of more than 60% are possible.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133452941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724417
M. Safar, M. Shalan
Much of the performance improvement achieved by state-of-the-art SAT solvers is related to the implementation of conflict analysis which enables the solver to perform nonchronological conflict-based backjumping and learn new clauses. However, these techniques have been ignored by the majority of hardware SAT solvers or are executed on some coupled software running on an attached host processor. In this paper, we present a reconfigurable hardware SAT solver that performs a search algorithm combining the advanced techniques: non-chronological backjumping, dynamic backtracking and learning. The whole execution is done in hardware eliminating any runtime communication with the host processor. The feasibility of the proposed approach is experimented through instances from the DIMACS benchmarks suite.
{"title":"A novel conflict directed jumping algorithm for hardware-based SAT solvers","authors":"M. Safar, M. Shalan","doi":"10.1109/IDT.2010.5724417","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724417","url":null,"abstract":"Much of the performance improvement achieved by state-of-the-art SAT solvers is related to the implementation of conflict analysis which enables the solver to perform nonchronological conflict-based backjumping and learn new clauses. However, these techniques have been ignored by the majority of hardware SAT solvers or are executed on some coupled software running on an attached host processor. In this paper, we present a reconfigurable hardware SAT solver that performs a search algorithm combining the advanced techniques: non-chronological backjumping, dynamic backtracking and learning. The whole execution is done in hardware eliminating any runtime communication with the host processor. The feasibility of the proposed approach is experimented through instances from the DIMACS benchmarks suite.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133055365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724400
L. A. Elazm, M. El-Moursy, H. Elsimary, M. Dessouky, F. Shawki
High speed and low power SBOX for Advanced Encryption Standard (AES) is proposed in this paper. Composite Galois Field is used in SBOX architecture to reduce size and delay of the circuit. Transmission gate is employed to reduce power consumption of the circuit. The proposed SBOX architecture consumes 186µw at 10MHz. The delay is reduced by 28.1%, and the average power consumption is reduced by 68.8% as compared to CMOS standard cell composite field design.
{"title":"High speed low power composite field SBOX","authors":"L. A. Elazm, M. El-Moursy, H. Elsimary, M. Dessouky, F. Shawki","doi":"10.1109/IDT.2010.5724400","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724400","url":null,"abstract":"High speed and low power SBOX for Advanced Encryption Standard (AES) is proposed in this paper. Composite Galois Field is used in SBOX architecture to reduce size and delay of the circuit. Transmission gate is employed to reduce power consumption of the circuit. The proposed SBOX architecture consumes 186µw at 10MHz. The delay is reduced by 28.1%, and the average power consumption is reduced by 68.8% as compared to CMOS standard cell composite field design.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117291268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724411
S. Askari, M. Nourani
Negative Bias Temperature Instability and Channel Hot Career degrades the life time of both the analog and digital circuits significantly and should be a major concern in nanoscale regime. These problems are usually addressed by leaving large design margins (called overdesign) or employing complicated calibration algorithm both of which result in larger area as well as excessive power consumption. We present a methodology to grade critical sections of a circuit and selectively overdesign them to harden the circuit characteristics against of these degradation. We have demonstrated our approach for various example circuits. For these examples, compared to conservative overdesign techniques, our approach achieves up to 20% and 33% improvement for area and power, respectively.
{"title":"A design for reliability methodology based on selective overdesign","authors":"S. Askari, M. Nourani","doi":"10.1109/IDT.2010.5724411","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724411","url":null,"abstract":"Negative Bias Temperature Instability and Channel Hot Career degrades the life time of both the analog and digital circuits significantly and should be a major concern in nanoscale regime. These problems are usually addressed by leaving large design margins (called overdesign) or employing complicated calibration algorithm both of which result in larger area as well as excessive power consumption. We present a methodology to grade critical sections of a circuit and selectively overdesign them to harden the circuit characteristics against of these degradation. We have demonstrated our approach for various example circuits. For these examples, compared to conservative overdesign techniques, our approach achieves up to 20% and 33% improvement for area and power, respectively.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"76 37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123421160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724430
S. Hassan, M. Taher, A. Wahba
This paper presents an approach which integrates two formal verification techniques, model checking and the Event-B method in a way that makes it possible to benefit from the advantages of both methods in the design flow. This integration allows the user to write his model and verifies it using model checking techniques/tools. If the model has errors or unverified properties the model checking produced counterexamples and simulation facility can be used to correct the model, this procedure can be repeated till a correct model is produced and verified. The verified model is then automatically translated to the corresponding Event-B model. The translated model can then be further analyzed by the Event-B tool and the user can utilize all the Event-B available tools. The generated model can also be further refined towards a more detailed model that can be used to generate the corresponding C code for the original system.
{"title":"Mapping SMV models to event-B models","authors":"S. Hassan, M. Taher, A. Wahba","doi":"10.1109/IDT.2010.5724430","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724430","url":null,"abstract":"This paper presents an approach which integrates two formal verification techniques, model checking and the Event-B method in a way that makes it possible to benefit from the advantages of both methods in the design flow. This integration allows the user to write his model and verifies it using model checking techniques/tools. If the model has errors or unverified properties the model checking produced counterexamples and simulation facility can be used to correct the model, this procedure can be repeated till a correct model is produced and verified. The verified model is then automatically translated to the corresponding Event-B model. The translated model can then be further analyzed by the Event-B tool and the user can utilize all the Event-B available tools. The generated model can also be further refined towards a more detailed model that can be used to generate the corresponding C code for the original system.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131704825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724403
A. Alma'aitah, Zine-Eddine Abid
In this paper, efficient hardware of one of the most popular encryption algorithms, the Advanced Encryption Standard (AES), is presented. A modified sub-pipelined structure is proposed targeting high speed and low power-delay product of the compact AES design with on-the-fly key expansion unit. By adding 25.8% in hardware complexity to the existing ASIC designs, the throughput is increased more than 158% with better overall power-delay product. Compared to other compact AES implementation the proposed structure can go up to 6Gbit/sec with about 13k gate count.
{"title":"Area efficient-high throughput sub-pipelined design of the AES in CMOS 180nm","authors":"A. Alma'aitah, Zine-Eddine Abid","doi":"10.1109/IDT.2010.5724403","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724403","url":null,"abstract":"In this paper, efficient hardware of one of the most popular encryption algorithms, the Advanced Encryption Standard (AES), is presented. A modified sub-pipelined structure is proposed targeting high speed and low power-delay product of the compact AES design with on-the-fly key expansion unit. By adding 25.8% in hardware complexity to the existing ASIC designs, the throughput is increased more than 158% with better overall power-delay product. Compared to other compact AES implementation the proposed structure can go up to 6Gbit/sec with about 13k gate count.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124922286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724416
Ismail Ktata, Ghaffari Fakhreddine, B. Granado, M. Abid
Actual dynamic applications, executed on real-time systems, have the tendency to be built on dynamically reconfigurable hardware devices. These applications require high performance and flexibility towards user and environment needs. To perform these application requirements, efficient mechanisms to manage hardware device must exist. In this paper we target OLLAF as a dynamically reconfigurable architecture which is designed to support complex and flexible applications. In order to deal with all of the dynamic aspects of such systems, we describe a predictive scheduling allowing an early estimation of our application dynamicity. A vision system of a mobile robot and an application of 3D synthesis images were served to validate the presented scheduling approach.
{"title":"Prediction performance method for dynamic task scheduling, case study: the OLLAF Architecture","authors":"Ismail Ktata, Ghaffari Fakhreddine, B. Granado, M. Abid","doi":"10.1109/IDT.2010.5724416","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724416","url":null,"abstract":"Actual dynamic applications, executed on real-time systems, have the tendency to be built on dynamically reconfigurable hardware devices. These applications require high performance and flexibility towards user and environment needs. To perform these application requirements, efficient mechanisms to manage hardware device must exist. In this paper we target OLLAF as a dynamically reconfigurable architecture which is designed to support complex and flexible applications. In order to deal with all of the dynamic aspects of such systems, we describe a predictive scheduling allowing an early estimation of our application dynamicity. A vision system of a mobile robot and an application of 3D synthesis images were served to validate the presented scheduling approach.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128145670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724398
R. Salem, Abdelrahman ElMously, H. Eissa, M. Dessouky, M. Anis
Lithography and stress variations are two dominant effects that significantly impact the functionality and performance of circuit designs at 45nm and below. Variability-aware circuit analysis methods have been introduced into the circuit design flow as one approach for implementing Design For Manufacturability (DFM) tools. These tools bridge the chip design implementation and manufacturing know-how to deliver high-value equivalent scaling advances. This paper presents an automated DFM framework that evaluates the digital design awareness of the process and physical layout effects on design performance. This study is applied on standard cell libraries and on critical paths of digital designs to monitor their differences in the physical and electrical parameters due to lithography and stress variations. An industrial FIR (Finite Inpulse Response) circuit designed in 45nm technology is used in our experiment. The results show the differences in the timing of the critical paths between the timing simulated from the standard netlist (without context awareness) and the timing simulated by using a randomly generated/actual design context aware netlist. In addition our study indicates that the variation of the timing of the critical paths differs from one industrial library to another. This shows the importance of having a variability-aware method that qualifies the libraries to be adopted for circuit designs.
{"title":"A DFM tool for analyzing lithography and stress effects on standard cells and critical path performance in 45nm digital designs","authors":"R. Salem, Abdelrahman ElMously, H. Eissa, M. Dessouky, M. Anis","doi":"10.1109/IDT.2010.5724398","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724398","url":null,"abstract":"Lithography and stress variations are two dominant effects that significantly impact the functionality and performance of circuit designs at 45nm and below. Variability-aware circuit analysis methods have been introduced into the circuit design flow as one approach for implementing Design For Manufacturability (DFM) tools. These tools bridge the chip design implementation and manufacturing know-how to deliver high-value equivalent scaling advances. This paper presents an automated DFM framework that evaluates the digital design awareness of the process and physical layout effects on design performance. This study is applied on standard cell libraries and on critical paths of digital designs to monitor their differences in the physical and electrical parameters due to lithography and stress variations. An industrial FIR (Finite Inpulse Response) circuit designed in 45nm technology is used in our experiment. The results show the differences in the timing of the critical paths between the timing simulated from the standard netlist (without context awareness) and the timing simulated by using a randomly generated/actual design context aware netlist. In addition our study indicates that the variation of the timing of the critical paths differs from one industrial library to another. This shows the importance of having a variability-aware method that qualifies the libraries to be adopted for circuit designs.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130824499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724397
B. Soudan
This work discusses the Semi-Random Net Reordering (SRNR) technique as a means to improve signal integrity and predictability of timing characteristics for wide signal busses. SRNR is able to reduce induced noise, signal propagation delay, signal transition speed, and their variations amongst the different wires comprising the bus. SRNR produces a faster routing structure that is more uniformly behaved. It has the advantage of zero cost and applicability under the strictest routing methodologies.
{"title":"Improving timing characteristics through Semi-Random Net Reordering","authors":"B. Soudan","doi":"10.1109/IDT.2010.5724397","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724397","url":null,"abstract":"This work discusses the Semi-Random Net Reordering (SRNR) technique as a means to improve signal integrity and predictability of timing characteristics for wide signal busses. SRNR is able to reduce induced noise, signal propagation delay, signal transition speed, and their variations amongst the different wires comprising the bus. SRNR produces a faster routing structure that is more uniformly behaved. It has the advantage of zero cost and applicability under the strictest routing methodologies.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121111622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724428
H. Zhang, R. Wille, R. Drechsler
Reversible circuits, in particular with their application in the domain of quantum computation and low-power design, are seen as promising alternative to conventional circuit technologies. First physical implementations are already available. Hence, researchers started to investigate testing of this kind of circuits. However, so far only simple reversible circuits have been considered. In this paper, we show that automatic test pattern generation of reversible circuits is harder, if additional constraints (like the frequently used constant inputs) occur. As a consequence, we propose an alternative ATPG method that makes use of solvers for Boolean satisfiability (SAT). Experiments demonstrate that with this approach, testsets for reversible circuits can be efficiently generated even if additional constraints like constant inputs have to be considered.
{"title":"SAT-based ATPG for reversible circuits","authors":"H. Zhang, R. Wille, R. Drechsler","doi":"10.1109/IDT.2010.5724428","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724428","url":null,"abstract":"Reversible circuits, in particular with their application in the domain of quantum computation and low-power design, are seen as promising alternative to conventional circuit technologies. First physical implementations are already available. Hence, researchers started to investigate testing of this kind of circuits. However, so far only simple reversible circuits have been considered. In this paper, we show that automatic test pattern generation of reversible circuits is harder, if additional constraints (like the frequently used constant inputs) occur. As a consequence, we propose an alternative ATPG method that makes use of solvers for Boolean satisfiability (SAT). Experiments demonstrate that with this approach, testsets for reversible circuits can be efficiently generated even if additional constraints like constant inputs have to be considered.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131415808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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