Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724423
A. V. Goor, S. Hamdioui
The observation that memory test algorithms have at most one type of complex march operation has resulted in a framework of orthogonal constructs for a novel Memory BIST (MBIST) architecture. It allows for a simple specification of a complete March Element (ME). Because all timingcritical information is available for pre-decoding prior to the application of the ME, high speed implementation is simplified considerably. A ME can specify any kind of operations, including nested operations and hammer operations, such that almost all algorithms and stresses are supported in a simple way.
观察到内存测试算法最多有一种复杂的行军操作，导致了一种新的内存测试算法(MBIST)架构的正交结构框架。它允许对完整的March Element (ME)进行简单的规范。由于在应用ME之前，所有时间关键信息都可用于预解码，因此高速实现大大简化。ME可以指定任何类型的操作，包括嵌套操作和锤击操作，从而以一种简单的方式支持几乎所有的算法和应力。
{"title":"MBIST architecture framework based on orthogonal constructs","authors":"A. V. Goor, S. Hamdioui","doi":"10.1109/IDT.2010.5724423","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724423","url":null,"abstract":"The observation that memory test algorithms have at most one type of complex march operation has resulted in a framework of orthogonal constructs for a novel Memory BIST (MBIST) architecture. It allows for a simple specification of a complete March Element (ME). Because all timingcritical information is available for pre-decoding prior to the application of the ME, high speed implementation is simplified considerably. A ME can specify any kind of operations, including nested operations and hammer operations, such that almost all algorithms and stresses are supported in a simple way.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130087148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724409
N. Haron, S. Hamdioui, Z. Ahyadi
Crossbar memories are promising memory technologies for future data storage. Although the memories offer trillion-capacity of data storage at low cost, they are expected to suffer from high defect densities and fault rates impacting their reliability. Error correction codes (ECCs), e.g., Redundant Residue Number System (RRNS) and Reed Solomon (RS) have been proposed to improve the reliability of memory systems. Yet, the implementation of the ECCs was usually done at software level, which incurs high cost. This paper analyzes ECC design for fault-tolerant crossbar memories. Both RS and RRNS codes are implemented and experimentally compared in terms of their area overhead, speed and error correction capability. The results show that the encoder and decoder of RS requires 7.5× smaller area overhead and operates 8.4× faster as compared to RRNS. Both ECCs has fairly similar error correction capability.
{"title":"ECC design for fault-tolerant crossbar memories: A case study","authors":"N. Haron, S. Hamdioui, Z. Ahyadi","doi":"10.1109/IDT.2010.5724409","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724409","url":null,"abstract":"Crossbar memories are promising memory technologies for future data storage. Although the memories offer trillion-capacity of data storage at low cost, they are expected to suffer from high defect densities and fault rates impacting their reliability. Error correction codes (ECCs), e.g., Redundant Residue Number System (RRNS) and Reed Solomon (RS) have been proposed to improve the reliability of memory systems. Yet, the implementation of the ECCs was usually done at software level, which incurs high cost. This paper analyzes ECC design for fault-tolerant crossbar memories. Both RS and RRNS codes are implemented and experimentally compared in terms of their area overhead, speed and error correction capability. The results show that the encoder and decoder of RS requires 7.5× smaller area overhead and operates 8.4× faster as compared to RRNS. Both ECCs has fairly similar error correction capability.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130992548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724424
S. Irobi, Z. Al-Ars, M. Renovell
The presence of parasitic node capacitance on a defective resistive node can induce dynamic changes in the electrical behavior of the circuit in SRAM devices, which may be referred to as the parasitic memory effect. This effect can cause dynamic faults in SRAMs. This paper presents an analysis of the parasitic memory effect in SRAMs on the defective resistive node. The paper demonstrates that the faulty behavior in SRAMs is exacerbated in the presence of parasitic node capacitance, something that reduces the fault coverage of current memory tests, and increases the defect-per-million rates.
{"title":"Parasitic memory effect in CMOS SRAMs","authors":"S. Irobi, Z. Al-Ars, M. Renovell","doi":"10.1109/IDT.2010.5724424","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724424","url":null,"abstract":"The presence of parasitic node capacitance on a defective resistive node can induce dynamic changes in the electrical behavior of the circuit in SRAM devices, which may be referred to as the parasitic memory effect. This effect can cause dynamic faults in SRAMs. This paper presents an analysis of the parasitic memory effect in SRAMs on the defective resistive node. The paper demonstrates that the faulty behavior in SRAMs is exacerbated in the presence of parasitic node capacitance, something that reduces the fault coverage of current memory tests, and increases the defect-per-million rates.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126008250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-05DOI: 10.1109/IDT.2010.5724415
S. Almukhaizim, Sara Bunian, O. Sinanoglu
Concurrent Error Detection (CED) methods are commonly employed to provide some level of error detection capability at the cost of some area and power overhead. In many applications, however, the error detection capability must be reconfigured dynamically, in order to adapt to the available power budget, criticality of the processed data, a thermal-safe schedule, etc. In this work, we propose a reconfigurable duplication-based CED infrastructure for logic circuits. The key idea is to enable/disable the operation of the duplicate circuit according to a set of control conditions. When CED is disabled, the inputs to the duplicate circuit retain their previous values (i.e., reduction in power dissipation via elimination of switching activity), yet errors are not detected (i.e., reduction in CED coverage). Experimental results using judicious and random selection of control conditions yield the same end-result; power dissipation is commensurate with CED coverage. Therefore, LFSR structures can be used to easily generate and reconfigure conditions, enabling their dynamic adjustment to adapt to the power constraints of the system.
{"title":"Reconfigurable low-power Concurrent Error Detection in logic circuits","authors":"S. Almukhaizim, Sara Bunian, O. Sinanoglu","doi":"10.1109/IDT.2010.5724415","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724415","url":null,"abstract":"Concurrent Error Detection (CED) methods are commonly employed to provide some level of error detection capability at the cost of some area and power overhead. In many applications, however, the error detection capability must be reconfigured dynamically, in order to adapt to the available power budget, criticality of the processed data, a thermal-safe schedule, etc. In this work, we propose a reconfigurable duplication-based CED infrastructure for logic circuits. The key idea is to enable/disable the operation of the duplicate circuit according to a set of control conditions. When CED is disabled, the inputs to the duplicate circuit retain their previous values (i.e., reduction in power dissipation via elimination of switching activity), yet errors are not detected (i.e., reduction in CED coverage). Experimental results using judicious and random selection of control conditions yield the same end-result; power dissipation is commensurate with CED coverage. Therefore, LFSR structures can be used to easily generate and reconfigure conditions, enabling their dynamic adjustment to adapt to the power constraints of the system.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117087731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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