Pub Date : 2012-10-22DOI: 10.1109/ISPCS.2012.6336618
G. Antonova, A. Apostolov, D. Arnold, P. Bedrosian, C. Brunner, D. Bui, W. Dickerson, M. Dood, H. Gerstung, D. Giarratano, R. Harada, C. Hoga, C. Huntley, D. Ingram, H. Kirrmann, S. Klein, T. Ko, S. Kunsman, K. Martin, G. Michel, R. Midence, B. Muschlitz, R. Moore, R. J. Murphy, B. Popescu, C. Preuss, F. Rahmatian, M. Renz, V. Skendzic, K. Stanton, F. Steinhauser, T. Tibbals, J. Tournier, B. Vandiver, J. Waters, J. Wu, B. Xue
This paper provides a summary of the IEEE C37.238-2011 standard, which specifies a subset of PTP parameters and options to provide global time availability, device interoperability, and failure management. This set of PTP parameters and options allows IEEE 1588-based time synchronization to be used in mission critical power system protection, control, automation, and data communication applications utilizing Ethernet communications architecture.
{"title":"Standard profile for use of IEEE Std 1588-2008 Precision Time Protocol (PTP) in power system applications: IEEE PES PSRC Working Group H7/Sub C7 members and guests","authors":"G. Antonova, A. Apostolov, D. Arnold, P. Bedrosian, C. Brunner, D. Bui, W. Dickerson, M. Dood, H. Gerstung, D. Giarratano, R. Harada, C. Hoga, C. Huntley, D. Ingram, H. Kirrmann, S. Klein, T. Ko, S. Kunsman, K. Martin, G. Michel, R. Midence, B. Muschlitz, R. Moore, R. J. Murphy, B. Popescu, C. Preuss, F. Rahmatian, M. Renz, V. Skendzic, K. Stanton, F. Steinhauser, T. Tibbals, J. Tournier, B. Vandiver, J. Waters, J. Wu, B. Xue","doi":"10.1109/ISPCS.2012.6336618","DOIUrl":"https://doi.org/10.1109/ISPCS.2012.6336618","url":null,"abstract":"This paper provides a summary of the IEEE C37.238-2011 standard, which specifies a subset of PTP parameters and options to provide global time availability, device interoperability, and failure management. This set of PTP parameters and options allows IEEE 1588-based time synchronization to be used in mission critical power system protection, control, automation, and data communication applications utilizing Ethernet communications architecture.","PeriodicalId":153925,"journal":{"name":"2012 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication Proceedings","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115909688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-22DOI: 10.1109/ISPCS.2012.6336620
A. Komes, C. Marinescu
Ethernet technologies are widely deployed across different industry sectors. Many applications have the need for accurate time synchronization as well as redundant communication links. The IEEE 1588 Precision Time Protocol was designed to deliver accurate synchronization in network environments using Ethernet technology, but the combination of IEEE 1588 with redundant Ethernet is known to be difficult. This paper introduces a combination solution for IEEE 1588 and redundant Ethernet that is able to increase the average synchronization accuracy compared to non redundant IEEE 1588 synchronization. For this purpose, the main accuracy limiting factor, the clock drift in transparent clocks, has been analyzed and measured. Subsequently, we present approaches that can reduce these undesired effects and improve the average synchronization accuracy. Further, the accuracy improvement of two of our approaches have been demonstrated using a redundant Ethernet implementation that is time synchronized.
{"title":"IEEE 1588 for redundant ethernet networks","authors":"A. Komes, C. Marinescu","doi":"10.1109/ISPCS.2012.6336620","DOIUrl":"https://doi.org/10.1109/ISPCS.2012.6336620","url":null,"abstract":"Ethernet technologies are widely deployed across different industry sectors. Many applications have the need for accurate time synchronization as well as redundant communication links. The IEEE 1588 Precision Time Protocol was designed to deliver accurate synchronization in network environments using Ethernet technology, but the combination of IEEE 1588 with redundant Ethernet is known to be difficult. This paper introduces a combination solution for IEEE 1588 and redundant Ethernet that is able to increase the average synchronization accuracy compared to non redundant IEEE 1588 synchronization. For this purpose, the main accuracy limiting factor, the clock drift in transparent clocks, has been analyzed and measured. Subsequently, we present approaches that can reduce these undesired effects and improve the average synchronization accuracy. Further, the accuracy improvement of two of our approaches have been demonstrated using a redundant Ethernet implementation that is time synchronized.","PeriodicalId":153925,"journal":{"name":"2012 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication Proceedings","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115265871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-22DOI: 10.1109/ISPCS.2012.6336619
R. Harada, A. Abdul, P. Wang
Concerns are raised about the performance of a timing plane in the presence of network redundancy protocols which rely on network fault detection and recovery principle such as RSTP [1]. Since most of the present power substations networks are relying on STP like protocols, coexistence of a timing plane over these networks is imperative. This paper proposed basic principles to transport PTP [2] timing plane reliability over RSTP based networks and evaluate the performance of a timing plane in light of these principles using ring and mesh topologies. Test results show that deterministic timing plane transportation over RSTP networks is possible under most network faults with the exception being the failure of the root bridge in mesh topology.
{"title":"Best practices of transporting PTPv2 over RSTP networks","authors":"R. Harada, A. Abdul, P. Wang","doi":"10.1109/ISPCS.2012.6336619","DOIUrl":"https://doi.org/10.1109/ISPCS.2012.6336619","url":null,"abstract":"Concerns are raised about the performance of a timing plane in the presence of network redundancy protocols which rely on network fault detection and recovery principle such as RSTP [1]. Since most of the present power substations networks are relying on STP like protocols, coexistence of a timing plane over these networks is imperative. This paper proposed basic principles to transport PTP [2] timing plane reliability over RSTP based networks and evaluate the performance of a timing plane in light of these principles using ring and mesh topologies. Test results show that deterministic timing plane transportation over RSTP networks is possible under most network faults with the exception being the failure of the root bridge in mesh topology.","PeriodicalId":153925,"journal":{"name":"2012 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication Proceedings","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128501305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-22DOI: 10.1109/ISPCS.2012.6336624
M. Davis, B. Villain, J. Ridoux, Anne-Cécile Orgerie, D. Veitch
The RADclock is an open source software clock that is highly robust to latency variability. A limitation up to now has been that it could only be used with NTP servers, and was unable to take advantage of IEEE-1588 enabled devices, including PTP masters and NICs with hardware timestamping. This paper benchmarks an early implementation of PTP support for RADclock, with and without hardware timestamping. We evaluate performance under both nominal and stressed conditions against alternative software clients ptpd and timekeeper and find that it compares very well.
{"title":"An IEEE-1588 compatible RADclock","authors":"M. Davis, B. Villain, J. Ridoux, Anne-Cécile Orgerie, D. Veitch","doi":"10.1109/ISPCS.2012.6336624","DOIUrl":"https://doi.org/10.1109/ISPCS.2012.6336624","url":null,"abstract":"The RADclock is an open source software clock that is highly robust to latency variability. A limitation up to now has been that it could only be used with NTP servers, and was unable to take advantage of IEEE-1588 enabled devices, including PTP masters and NICs with hardware timestamping. This paper benchmarks an early implementation of PTP support for RADclock, with and without hardware timestamping. We evaluate performance under both nominal and stressed conditions against alternative software clients ptpd and timekeeper and find that it compares very well.","PeriodicalId":153925,"journal":{"name":"2012 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication Proceedings","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124026734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-22DOI: 10.1109/ISPCS.2012.6336633
H. Kirrmann, J. Tournier
Profiles and extensions of IEEE 1588 have recently been standardized as IEEE C37.238 (for electrical power systems) and IEEE 802.1AS (for audio-video bridging). The working groups focused more on innovation in their application domain than on keeping compatibility with the original default profile of IEEE 1588 J.4. As a result, the profiles cannot share the same network infrastructure, hampering the engineering of mixed system, e.g. integrated power and automation networks. Nodes that support several profiles become complex and have to support three MIBs for SNMP, while one would be sufficient. This position paper presents the peculiarities of IEEE C37.238 and IEEE 802.1AS and makes propositions to ensure at least coexistence on the same network, and possibly allow a reuse of a common trunk with compatible extensions. These propositions imply that all standards should be amended simultaneously at their next revision, with 1588v3 taking over the bulk of the additional features and the other becoming true profiles. This contribution is limited to a mapping on IEEE 802.3, which is the most frequently used technology in industrial automation.
{"title":"Coexistence of IEEE 1588, C37.238 and 802.1AS, issues and recommendations","authors":"H. Kirrmann, J. Tournier","doi":"10.1109/ISPCS.2012.6336633","DOIUrl":"https://doi.org/10.1109/ISPCS.2012.6336633","url":null,"abstract":"Profiles and extensions of IEEE 1588 have recently been standardized as IEEE C37.238 (for electrical power systems) and IEEE 802.1AS (for audio-video bridging). The working groups focused more on innovation in their application domain than on keeping compatibility with the original default profile of IEEE 1588 J.4. As a result, the profiles cannot share the same network infrastructure, hampering the engineering of mixed system, e.g. integrated power and automation networks. Nodes that support several profiles become complex and have to support three MIBs for SNMP, while one would be sufficient. This position paper presents the peculiarities of IEEE C37.238 and IEEE 802.1AS and makes propositions to ensure at least coexistence on the same network, and possibly allow a reuse of a common trunk with compatible extensions. These propositions imply that all standards should be amended simultaneously at their next revision, with 1588v3 taking over the bulk of the additional features and the other becoming true profiles. This contribution is limited to a mapping on IEEE 802.3, which is the most frequently used technology in industrial automation.","PeriodicalId":153925,"journal":{"name":"2012 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication Proceedings","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131046383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-22DOI: 10.1109/ISPCS.2012.6336615
T. Muller, N. Kero
Today's market offers a wide variety of IEEE1588 devices implementing the Precision Time Protocol (PTP) in many different ways. This work presents a new approach of a fully integrated PTP node by focusing on three major attributes: (i) high precision in the range of a few nanoseconds, (ii) being as versatile as possible by implementing a vast part of the standard and (iii) keeping the costs of such a device as low as possible. To satisfy these goals, different ways of implementing such a device as a ready to use System-on-Chip solution are discussed. Advantages and draw-backs of several system architectures are outlined by describing all hard- and software components and finally presenting measurement results of a prototype implementation.
{"title":"A fully integrated versatile PTP node","authors":"T. Muller, N. Kero","doi":"10.1109/ISPCS.2012.6336615","DOIUrl":"https://doi.org/10.1109/ISPCS.2012.6336615","url":null,"abstract":"Today's market offers a wide variety of IEEE1588 devices implementing the Precision Time Protocol (PTP) in many different ways. This work presents a new approach of a fully integrated PTP node by focusing on three major attributes: (i) high precision in the range of a few nanoseconds, (ii) being as versatile as possible by implementing a vast part of the standard and (iii) keeping the costs of such a device as low as possible. To satisfy these goals, different ways of implementing such a device as a ready to use System-on-Chip solution are discussed. Advantages and draw-backs of several system architectures are outlined by describing all hard- and software components and finally presenting measurement results of a prototype implementation.","PeriodicalId":153925,"journal":{"name":"2012 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication Proceedings","volume":"9 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132655238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-22DOI: 10.1109/ISPCS.2012.6336622
R. Exel
Packet-based clock synchronization protocols, such as IEEE 1588, depend on the quality of the timestamps taken at the reception and transmission of packets. As software-based timestamping generates large non-deterministic delays, Ethernet synchronization implementations have moved the timestamping closer to the physical layer. However, most wireless synchronization approaches are restricted to software timestamping due to the lack of hardware timestamping features. This paper presents a physical layer timestamping approach for IEEE 802.11b, which is able to generate timestamps with sub-100 picosecond accuracy. When synchronizing the clocks of two WLAN devices with the proposed approach, the measurements show that the system can reach synchronization accuracies below 1 ns even with standard crystal oscillators.
{"title":"Clock synchronization in IEEE 802.11 wireless LANs using physical layer timestamps","authors":"R. Exel","doi":"10.1109/ISPCS.2012.6336622","DOIUrl":"https://doi.org/10.1109/ISPCS.2012.6336622","url":null,"abstract":"Packet-based clock synchronization protocols, such as IEEE 1588, depend on the quality of the timestamps taken at the reception and transmission of packets. As software-based timestamping generates large non-deterministic delays, Ethernet synchronization implementations have moved the timestamping closer to the physical layer. However, most wireless synchronization approaches are restricted to software timestamping due to the lack of hardware timestamping features. This paper presents a physical layer timestamping approach for IEEE 802.11b, which is able to generate timestamps with sub-100 picosecond accuracy. When synchronizing the clocks of two WLAN devices with the proposed approach, the measurements show that the system can reach synchronization accuracies below 1 ns even with standard crystal oscillators.","PeriodicalId":153925,"journal":{"name":"2012 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication Proceedings","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134064059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-22DOI: 10.1109/ISPCS.2012.6336623
B. Villain, M. Davis, J. Ridoux, D. Veitch, N. Normand
Dealing effectively with latency is the key to accurate and reliable timekeeping over networks. Software components of timekeeping, including synchronisation algorithms such as ntpd, RADclock, and ptpd, must deal with the significant and highly variable latencies inherent to common operating systems. Using the DTrace system profiling tool, we provide an accurate breakdown of the latencies between common timestamping locations in the FreeBSD Operating System. We report on how these latency components react to stress patterns of different kinds, and determine which timestamping strategies result in the lowest latency, and the smallest in-host asymmetry. Our results can be used to improve timestamping and timekeeping for software clocks.
{"title":"Probing the latencies of software timestamping","authors":"B. Villain, M. Davis, J. Ridoux, D. Veitch, N. Normand","doi":"10.1109/ISPCS.2012.6336623","DOIUrl":"https://doi.org/10.1109/ISPCS.2012.6336623","url":null,"abstract":"Dealing effectively with latency is the key to accurate and reliable timekeeping over networks. Software components of timekeeping, including synchronisation algorithms such as ntpd, RADclock, and ptpd, must deal with the significant and highly variable latencies inherent to common operating systems. Using the DTrace system profiling tool, we provide an accurate breakdown of the latencies between common timestamping locations in the FreeBSD Operating System. We report on how these latency components react to stress patterns of different kinds, and determine which timestamping strategies result in the lowest latency, and the smallest in-host asymmetry. Our results can be used to improve timestamping and timekeeping for software clocks.","PeriodicalId":153925,"journal":{"name":"2012 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication Proceedings","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127826901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-22DOI: 10.1109/ISPCS.2012.6336611
P. Moreira, J. Serrano, P. Alvarez, M. Lipinski, T. Wlostowski, I. Darwazeh
Direct Digital frequency Synthesizers (DDS) require a reference local oscillator (LO) to synthesize waveforms with various frequencies. The output clock inherits to a certain degree the frequency stability of the LO. However, very stable clocks, as those generated from atomic standards, employ a prohibitive price to have as LO. In this paper, a system architecture that distributes a frequency reference to multiple slave receivers using the White Rabbit Network is presented. The system architecture aims to be a competitive solution to distribute frequency references over large distances. In addition, the non-ideality of the different system elements as well as the receiver frequency impairments are studied with the view to assess their influence on the quality of the distributed clock.
{"title":"Distributed DDS in a White Rabbit Network: An IEEE 1588 application","authors":"P. Moreira, J. Serrano, P. Alvarez, M. Lipinski, T. Wlostowski, I. Darwazeh","doi":"10.1109/ISPCS.2012.6336611","DOIUrl":"https://doi.org/10.1109/ISPCS.2012.6336611","url":null,"abstract":"Direct Digital frequency Synthesizers (DDS) require a reference local oscillator (LO) to synthesize waveforms with various frequencies. The output clock inherits to a certain degree the frequency stability of the LO. However, very stable clocks, as those generated from atomic standards, employ a prohibitive price to have as LO. In this paper, a system architecture that distributes a frequency reference to multiple slave receivers using the White Rabbit Network is presented. The system architecture aims to be a competitive solution to distribute frequency references over large distances. In addition, the non-ideality of the different system elements as well as the receiver frequency impairments are studied with the view to assess their influence on the quality of the distributed clock.","PeriodicalId":153925,"journal":{"name":"2012 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication Proceedings","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128395214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-22DOI: 10.1109/ISPCS.2012.6336632
Cagri Onal, Hubert Kirrmann
IEEE 1588 Annex K describes a security mechanism for clock synchronization based on authentication of the PTP messages through HMAC. Since the standard was published, several new improved authentication algorithms were implemented and tested, in particular GMAC, XCBCMAC and CMAC, which provide the same level of security. Simulations and measurements show that contrarily to popular belief, these algorithms allow to authenticate on-the-fly the one-step Sync or Pdelay_Resp messages even at 1 Gbit/s. Faster algorithms would improve throughput only marginally. It was also found that the present security association and key management could be improved. These results should be considered for a next revision of Annex K. Such changes should first be coordinated with other protocols, in particular IEC 62351 and IEC 62439-3, to achieve a unified, hardware-implemented security for all Layer 2 protocols.
{"title":"Security improvements for IEEE 1588 Annex K: Implementation and comparison of authentication codes","authors":"Cagri Onal, Hubert Kirrmann","doi":"10.1109/ISPCS.2012.6336632","DOIUrl":"https://doi.org/10.1109/ISPCS.2012.6336632","url":null,"abstract":"IEEE 1588 Annex K describes a security mechanism for clock synchronization based on authentication of the PTP messages through HMAC. Since the standard was published, several new improved authentication algorithms were implemented and tested, in particular GMAC, XCBCMAC and CMAC, which provide the same level of security. Simulations and measurements show that contrarily to popular belief, these algorithms allow to authenticate on-the-fly the one-step Sync or Pdelay_Resp messages even at 1 Gbit/s. Faster algorithms would improve throughput only marginally. It was also found that the present security association and key management could be improved. These results should be considered for a next revision of Annex K. Such changes should first be coordinated with other protocols, in particular IEC 62351 and IEC 62439-3, to achieve a unified, hardware-implemented security for all Layer 2 protocols.","PeriodicalId":153925,"journal":{"name":"2012 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication Proceedings","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125260061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：