Solar energy has the potential to meet the entire world's energy requirements. Previous study revealed that photovoltaic (PV) panel monitoring methods are far more difficult and exclusive. This study examines and proposes an automated internet of things (IoT)-based PV panel monitoring system that allows autonomous monitoring of solar panel properties such as voltage, temperature, humidity, and sun irradiation from anywhere over the internet. Excessive human demand can be reduced by collecting data from solar panels. Many data sets can be collected frequently; for example, thousands of data points can be collected each minute. Continuous monitoring is achievable by gathering real-time data. Because there is no possibility of human error, highly accurate data can be generated.
{"title":"Internet of things based smart photovoltaic panel monitoring system","authors":"Arcot Ramakrishnan Kalaiarasi, Ayyadurai Chinnadurai Vasunthira Devi, Vijayan Yeshwanth, Samuthiraraj Pravinraj, Muthu Prabakaran","doi":"10.11591/ijres.v13.i2.pp341-351","DOIUrl":"https://doi.org/10.11591/ijres.v13.i2.pp341-351","url":null,"abstract":"Solar energy has the potential to meet the entire world's energy requirements. Previous study revealed that photovoltaic (PV) panel monitoring methods are far more difficult and exclusive. This study examines and proposes an automated internet of things (IoT)-based PV panel monitoring system that allows autonomous monitoring of solar panel properties such as voltage, temperature, humidity, and sun irradiation from anywhere over the internet. Excessive human demand can be reduced by collecting data from solar panels. Many data sets can be collected frequently; for example, thousands of data points can be collected each minute. Continuous monitoring is achievable by gathering real-time data. Because there is no possibility of human error, highly accurate data can be generated.","PeriodicalId":158991,"journal":{"name":"International Journal of Reconfigurable and Embedded Systems (IJRES)","volume":"196 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141692855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-01DOI: 10.11591/ijres.v13.i1.pp1-8
Priti Shahane, Rakhi Kurup
Many internet protocol (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on Field programmable gate array (FPGA).
{"title":"Design of fault tolerant algorithm for network on chip router using field programmable gate array","authors":"Priti Shahane, Rakhi Kurup","doi":"10.11591/ijres.v13.i1.pp1-8","DOIUrl":"https://doi.org/10.11591/ijres.v13.i1.pp1-8","url":null,"abstract":"Many internet protocol (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on Field programmable gate array (FPGA).","PeriodicalId":158991,"journal":{"name":"International Journal of Reconfigurable and Embedded Systems (IJRES)","volume":"82 11","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140085071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-01DOI: 10.11591/ijres.v13.i1.pp20-24
Edgar Serrano-Pérez, Anabelem Soberanes-Martín
This work deals with the integration of low-cost electronic devices that were integrated into constructing a dynamic maker that allows the triggering of augmented reality events. A hybrid structure was developed to combine the most favorable aspects of fiducial markers and dynamic markers. The lighting infrared patterns are effectively modifiable through the programming of an ESP8266 microcontroller card. To test the system, an infrared lighting pattern generated was detected through a digital camera, and an augmented reality application was implemented using a web page for displaying text. Electronic shift registers were used for the temporal storage of the infrared illumination pattern. The infrared illumination marker can’t be detected by human eyes, but it is easily recognized due to the inner black square shape embedded into a white wooden structure.
{"title":"Affordable digital electronics for building a hybrid dynamic marker structure with infrared illumination light patterns","authors":"Edgar Serrano-Pérez, Anabelem Soberanes-Martín","doi":"10.11591/ijres.v13.i1.pp20-24","DOIUrl":"https://doi.org/10.11591/ijres.v13.i1.pp20-24","url":null,"abstract":"<p class=\"western\" style=\"orphans: 0; widows: 0; margin-top: 0.08in; margin-bottom: 0in;\" align=\"justify\">This work deals with the integration of low-cost electronic devices that were integrated into constructing a dynamic maker that allows the triggering of augmented reality events. A hybrid structure was developed to combine the most favorable aspects of fiducial markers and dynamic markers. The lighting infrared patterns are effectively modifiable through the programming of an ESP8266 microcontroller card. To test the system, an infrared lighting pattern generated was detected through a digital camera, and an augmented reality application was implemented using a web page for displaying text. Electronic shift registers were used for the temporal storage of the infrared illumination pattern. The infrared illumination marker can’t be detected by human eyes, but it is easily recognized due to the inner black square shape embedded into a white wooden structure.</p>","PeriodicalId":158991,"journal":{"name":"International Journal of Reconfigurable and Embedded Systems (IJRES)","volume":"1 2","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140090847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-01DOI: 10.11591/ijres.v13.i1.pp160-170
Savitha Patil, Mungamuri Sasikala
Recently, plant identification has become an active trend due to encouraging results achieved in plant species detection and plant classification fields among numerous available plants using deep learning methods. Therefore, plant classification analysis is performed in this work to address the problem of accurate plant species detection in the presence of multiple leaves together, flowers, and noise. Thus, a convolutional neural network based deep feature learning and classification (CNN-DFLC) model is designed to analyze patterns of plant leaves and perform classification using generated fine-grained feature weights. The proposed CNN-DFLC model precisely estimates which the given image belongs to which plant species. Several layers and blocks are utilized to design the proposed CNN-DFLC model. Fine-grained feature weights are obtained using convolutional and pooling layers. The obtained feature maps in training are utilized to predict labels and model performance is tested on the Vietnam plant image (VPN-200) dataset. This dataset consists of a total number of 20,000 images and testing results are achieved in terms of classification accuracy, precision, recall, and other performance metrics. The mean classification accuracy obtained using the proposed CNN-DFLC model is 96.42% considering all 200 classes from the VPN-200 dataset.
{"title":"Accurate plant species analysis for plant classification using convolutional neural network architecture","authors":"Savitha Patil, Mungamuri Sasikala","doi":"10.11591/ijres.v13.i1.pp160-170","DOIUrl":"https://doi.org/10.11591/ijres.v13.i1.pp160-170","url":null,"abstract":"Recently, plant identification has become an active trend due to encouraging results achieved in plant species detection and plant classification fields among numerous available plants using deep learning methods. Therefore, plant classification analysis is performed in this work to address the problem of accurate plant species detection in the presence of multiple leaves together, flowers, and noise. Thus, a convolutional neural network based deep feature learning and classification (CNN-DFLC) model is designed to analyze patterns of plant leaves and perform classification using generated fine-grained feature weights. The proposed CNN-DFLC model precisely estimates which the given image belongs to which plant species. Several layers and blocks are utilized to design the proposed CNN-DFLC model. Fine-grained feature weights are obtained using convolutional and pooling layers. The obtained feature maps in training are utilized to predict labels and model performance is tested on the Vietnam plant image (VPN-200) dataset. This dataset consists of a total number of 20,000 images and testing results are achieved in terms of classification accuracy, precision, recall, and other performance metrics. The mean classification accuracy obtained using the proposed CNN-DFLC model is 96.42% considering all 200 classes from the VPN-200 dataset.","PeriodicalId":158991,"journal":{"name":"International Journal of Reconfigurable and Embedded Systems (IJRES)","volume":" 3","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140091547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Monitoring behavior, numerous actions, or any such information is considered as surveillance and is done for information gathering, influencing, managing, or directing purposes. Citizens employ surveillance to safeguard their communities. Governments do this for the purposes of intelligence collection, including espionage, crime prevention, the defense of a method, a person, a group, or an item; or the investigation of criminal activity. Using an internet of things (IoT) rover, the area will be secured with better secrecy and efficiency instead of humans, will provide an additional safety step. In this paper, there is a discussion about an IoT rover for remote surveillance based around a Raspberry Pi microprocessor which will be able to monitor a closed/open space. This rover will allow safer survey operations and would help to reduce the risks involved with it.
监视行为、众多行动或任何此类信息都被视为监视，其目的是收集信息、影响、管理或指挥。公民利用监视来保护自己的社区。政府则是为了收集情报，包括间谍活动、预防犯罪、保护某种方法、个人、团体或物品，或调查犯罪活动。使用物联网（IoT）漫游车，将代替人类以更好的保密性和效率确保该区域的安全，这将提供额外的安全步骤。本文将讨论一种基于 Raspberry Pi 微处理器的远程监控物联网漫游车，它能够监控封闭/开放空间。该漫游车将使勘测作业更加安全，并有助于降低勘测作业所涉及的风险。
{"title":"Remote surveillance of enclosed and open architectures using unmanned vehicle with advanced security","authors":"Ayushman Khetan, Abhirup Sarkar, H. Sabunwala, Eshan Gupta, Harikrishnan Ramachandran, Priti Shahane","doi":"10.11591/ijres.v13.i1.pp126-132","DOIUrl":"https://doi.org/10.11591/ijres.v13.i1.pp126-132","url":null,"abstract":"Monitoring behavior, numerous actions, or any such information is considered as surveillance and is done for information gathering, influencing, managing, or directing purposes. Citizens employ surveillance to safeguard their communities. Governments do this for the purposes of intelligence collection, including espionage, crime prevention, the defense of a method, a person, a group, or an item; or the investigation of criminal activity. Using an internet of things (IoT) rover, the area will be secured with better secrecy and efficiency instead of humans, will provide an additional safety step. In this paper, there is a discussion about an IoT rover for remote surveillance based around a Raspberry Pi microprocessor which will be able to monitor a closed/open space. This rover will allow safer survey operations and would help to reduce the risks involved with it.","PeriodicalId":158991,"journal":{"name":"International Journal of Reconfigurable and Embedded Systems (IJRES)","volume":"17 5","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140086491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-01DOI: 10.11591/ijres.v13.i1.pp25-32
Vijaya Bhaskar Chalampalem, Munaswamy Pidugu
Software defined radios (SDRs) are highly motivated for wireless device modelling due to their flexibility and scalability over alternative wireless design options. The evolutionary structure of finite impulse response (FIR) filters was designed for a proposed reconfigurable canonical sign digit (CSD) approach. Considering the complex trade-off, this is accomplished with many FIR taps, which is a challenging assignment. On the baseband processing side, design is given with parameterization-controlled FIR filter tap selection. Optimal processing models to overcome the reconfigurable design issues associated with the SDR system for a multi-standard wireless communication system root cosine filter standard are often used to implement multiple FIR channelization topologies, each of which is tied to a particular in-phase and quadrature (IQ) symbol. Additionally, it demonstrates the viability of using a multi-modulation baseband modulator in the SDR system for next-generation wireless communication systems to maximise adaptability with the least amount of computational complexity overhead. The proposed multiplier-less FIR filter-based reconfigurable baseband modulator, according to the experimental results, offers a 6% complexity reduction and a 47% improvement in performance efficiency over the current SDR system.
与其他无线设计方案相比，软件定义无线电（SDR）具有灵活性和可扩展性，因此在无线设备建模方面备受推崇。有限脉冲响应（FIR）滤波器的演化结构是为一种拟议的可重构典型符号位数（CSD）方法而设计的。考虑到复杂的权衡问题，需要使用许多 FIR 抽头来完成这项具有挑战性的任务。在基带处理方面，通过参数化控制的 FIR 滤波器抽头选择进行设计。为克服与多标准无线通信系统根余弦滤波器标准的 SDR 系统相关的可重新配置设计问题，优化处理模型通常用于实现多个 FIR 信道化拓扑结构，其中每个拓扑结构都与特定的同相和正交 (IQ) 符号相关联。此外，它还证明了在下一代无线通信系统的 SDR 系统中使用多调制基带调制器的可行性，从而以最小的计算复杂度开销实现最大的适应性。根据实验结果，所提出的基于无乘法器 FIR 滤波器的可重构基带调制器比目前的 SDR 系统降低了 6% 的复杂度，性能效率提高了 47%。
{"title":"An efficient high performance reconfigurable canonical sign digit architecture for software defined radio","authors":"Vijaya Bhaskar Chalampalem, Munaswamy Pidugu","doi":"10.11591/ijres.v13.i1.pp25-32","DOIUrl":"https://doi.org/10.11591/ijres.v13.i1.pp25-32","url":null,"abstract":"Software defined radios (SDRs) are highly motivated for wireless device modelling due to their flexibility and scalability over alternative wireless design options. The evolutionary structure of finite impulse response (FIR) filters was designed for a proposed reconfigurable canonical sign digit (CSD) approach. Considering the complex trade-off, this is accomplished with many FIR taps, which is a challenging assignment. On the baseband processing side, design is given with parameterization-controlled FIR filter tap selection. Optimal processing models to overcome the reconfigurable design issues associated with the SDR system for a multi-standard wireless communication system root cosine filter standard are often used to implement multiple FIR channelization topologies, each of which is tied to a particular in-phase and quadrature (IQ) symbol. Additionally, it demonstrates the viability of using a multi-modulation baseband modulator in the SDR system for next-generation wireless communication systems to maximise adaptability with the least amount of computational complexity overhead. The proposed multiplier-less FIR filter-based reconfigurable baseband modulator, according to the experimental results, offers a 6% complexity reduction and a 47% improvement in performance efficiency over the current SDR system.","PeriodicalId":158991,"journal":{"name":"International Journal of Reconfigurable and Embedded Systems (IJRES)","volume":"91 6","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140086846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-01DOI: 10.11591/ijres.v13.i1.pp41-51
Muhammad Hanafi Mujtahidin, Ahmad Feirdaous Mohd Shah, Ahmadul Sayyidi Amin Jais, K. A. M. Annuar, M. R. Sapiee
The global agriculture system faces significant challenges in meeting the growing demand for food production, particularly given projections that the world's population will reach 70% by 2050. Hydroponic farming is an increasingly popular technique in this field, offering a promising solution to these challenges. This paper will present the improvement of the current traditional hydroponic method by providing a system that can be used to monitor and control the important element in order to help the plant grow up smoothly. This proposed system is quite efficient and user-friendly that can be used by anyone. This is a combination of a traditional hydroponic system, an automatic control system and a smartphone. The primary objective is to develop a smart system capable of monitoring and controlling potential hydrogen (pH) levels, a key factor that affects hydroponic plant growth. Ultimately, this paper offers an alternative approach to address the challenges of the existing agricultural system and promote the production of clean, disease-free, and healthy food for a better future.
{"title":"Design and development of control and monitoring hydroponic system","authors":"Muhammad Hanafi Mujtahidin, Ahmad Feirdaous Mohd Shah, Ahmadul Sayyidi Amin Jais, K. A. M. Annuar, M. R. Sapiee","doi":"10.11591/ijres.v13.i1.pp41-51","DOIUrl":"https://doi.org/10.11591/ijres.v13.i1.pp41-51","url":null,"abstract":"The global agriculture system faces significant challenges in meeting the growing demand for food production, particularly given projections that the world's population will reach 70% by 2050. Hydroponic farming is an increasingly popular technique in this field, offering a promising solution to these challenges. This paper will present the improvement of the current traditional hydroponic method by providing a system that can be used to monitor and control the important element in order to help the plant grow up smoothly. This proposed system is quite efficient and user-friendly that can be used by anyone. This is a combination of a traditional hydroponic system, an automatic control system and a smartphone. The primary objective is to develop a smart system capable of monitoring and controlling potential hydrogen (pH) levels, a key factor that affects hydroponic plant growth. Ultimately, this paper offers an alternative approach to address the challenges of the existing agricultural system and promote the production of clean, disease-free, and healthy food for a better future.","PeriodicalId":158991,"journal":{"name":"International Journal of Reconfigurable and Embedded Systems (IJRES)","volume":"109 37","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140089929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-01DOI: 10.11591/ijres.v13.i1.pp9-19
Santhosh Kumar Gorva, Latha C. Anandachar
Recently, lot of interest have been put forth by researchers to improve workload scheduling in cloud platform. However, execution of scientific workflow on cloud platform is time consuming and expensive. As users are charged based on hour of usage, lot of research work have been emphasized in minimizing processing time for reduction of cost. However, the processing cost can be reduced by minimizing energy consumption especially when resources are heterogeneous in nature; very limited work have been done considering optimizing cost with energy and processing time parameters together in meeting task quality of service (QoS) requirement. This paper presents cost and performance aware workload scheduling (CPA-WS) technique under heterogeneous cloud platform. This paper presents a cost optimization model through minimization of processing time and energy dissipation for execution of task. Experiments are conducted using two widely used workflow such as Inspiral and CyberShake. The outcome shows the CPA-WS significantly reduces energy, time, and cost in comparison with standard workload scheduling model.
{"title":"Cost and performance aware scheduling technique for cloud computing environment","authors":"Santhosh Kumar Gorva, Latha C. Anandachar","doi":"10.11591/ijres.v13.i1.pp9-19","DOIUrl":"https://doi.org/10.11591/ijres.v13.i1.pp9-19","url":null,"abstract":"Recently, lot of interest have been put forth by researchers to improve workload scheduling in cloud platform. However, execution of scientific workflow on cloud platform is time consuming and expensive. As users are charged based on hour of usage, lot of research work have been emphasized in minimizing processing time for reduction of cost. However, the processing cost can be reduced by minimizing energy consumption especially when resources are heterogeneous in nature; very limited work have been done considering optimizing cost with energy and processing time parameters together in meeting task quality of service (QoS) requirement. This paper presents cost and performance aware workload scheduling (CPA-WS) technique under heterogeneous cloud platform. This paper presents a cost optimization model through minimization of processing time and energy dissipation for execution of task. Experiments are conducted using two widely used workflow such as Inspiral and CyberShake. The outcome shows the CPA-WS significantly reduces energy, time, and cost in comparison with standard workload scheduling model.","PeriodicalId":158991,"journal":{"name":"International Journal of Reconfigurable and Embedded Systems (IJRES)","volume":"18 5","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140083994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-01DOI: 10.11591/ijres.v13.i1.pp151-159
Santosh Kumar Sharma, Ajay Pratap, Harsh Dev
Big data as a service (BDaaS) platform is widely used by various organizations for handling and processing the high volume of data generated from different internet of things (IoT) devices. Data generated from these IoT devices are kept in the form of big data with the help of cloud computing technology. Researchers are putting efforts into providing a more secure and protected access environment for the data available on the cloud. In order to create a safe, distributed, and decentralised environment in the cloud, blockchain technology has emerged as a useful tool. In this research paper, we have proposed a system that uses blockchain technology as a tool to regulate data access that is provided by BDaaS platforms. We are securing the access policy of data by using a modified form of ciphertext policy-attribute based encryption (CP-ABE) technique with the help of blockchain technology. For secure data access in BDaaS, algorithms have been created using a mix of CP-ABE with blockchain technology. Proposed smart contract algorithms are implemented using Eclipse 7.0 IDE and the cloud environment has been simulated on CloudSim tool. Results of key generation time, encryption time, and decryption time has been calculated and compared with access control mechanism without blockchain technology.
{"title":"Design of access control framework for big data as a service platform","authors":"Santosh Kumar Sharma, Ajay Pratap, Harsh Dev","doi":"10.11591/ijres.v13.i1.pp151-159","DOIUrl":"https://doi.org/10.11591/ijres.v13.i1.pp151-159","url":null,"abstract":"Big data as a service (BDaaS) platform is widely used by various organizations for handling and processing the high volume of data generated from different internet of things (IoT) devices. Data generated from these IoT devices are kept in the form of big data with the help of cloud computing technology. Researchers are putting efforts into providing a more secure and protected access environment for the data available on the cloud. In order to create a safe, distributed, and decentralised environment in the cloud, blockchain technology has emerged as a useful tool. In this research paper, we have proposed a system that uses blockchain technology as a tool to regulate data access that is provided by BDaaS platforms. We are securing the access policy of data by using a modified form of ciphertext policy-attribute based encryption (CP-ABE) technique with the help of blockchain technology. For secure data access in BDaaS, algorithms have been created using a mix of CP-ABE with blockchain technology. Proposed smart contract algorithms are implemented using Eclipse 7.0 IDE and the cloud environment has been simulated on CloudSim tool. Results of key generation time, encryption time, and decryption time has been calculated and compared with access control mechanism without blockchain technology.","PeriodicalId":158991,"journal":{"name":"International Journal of Reconfigurable and Embedded Systems (IJRES)","volume":"13 10","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140084053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-01DOI: 10.11591/ijres.v13.i1.pp33-40
Abedalmuhdi Almomany, Amin Jarrah
One advantage of the open computing language (OpenCL) software framework is its ability to run on different architectures. Field programmable gate arrays (FPGAs) are a high-speed computing architecture used for computation acceleration. This work develops a set of eight benchmarks (memory synchronization functions, explained in this study) using an OpenCL framework to study the effect of memory access time on overall performance when targeting the general FPGA computing platform. The results indicate the best synchronization mechanism to be adopted to synthesize the proposed design on the FPGA computation architecture. The proposed research results also demonstrate the effectiveness of using a task-parallel model approach to avoid using high-cost synchronization mechanisms within proposed designs that are constructed on the general FPGA computation platform.
{"title":"FPGAs memory synchronization and performance evaluation using the open computing language framework","authors":"Abedalmuhdi Almomany, Amin Jarrah","doi":"10.11591/ijres.v13.i1.pp33-40","DOIUrl":"https://doi.org/10.11591/ijres.v13.i1.pp33-40","url":null,"abstract":"One advantage of the open computing language (OpenCL) software framework is its ability to run on different architectures. Field programmable gate arrays (FPGAs) are a high-speed computing architecture used for computation acceleration. This work develops a set of eight benchmarks (memory synchronization functions, explained in this study) using an OpenCL framework to study the effect of memory access time on overall performance when targeting the general FPGA computing platform. The results indicate the best synchronization mechanism to be adopted to synthesize the proposed design on the FPGA computation architecture. The proposed research results also demonstrate the effectiveness of using a task-parallel model approach to avoid using high-cost synchronization mechanisms within proposed designs that are constructed on the general FPGA computation platform.","PeriodicalId":158991,"journal":{"name":"International Journal of Reconfigurable and Embedded Systems (IJRES)","volume":"47 7","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140085780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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