Pub Date : 2016-10-01DOI: 10.1109/HLDVT.2016.7748257
Jörg Fickenscher, Oliver Reiche, Jens Schlumberger, Frank Hannig, J. Teich
Future Advanced Driver Assistance Systems (ADAS) require the continuous computation of detailed maps of the vehicle's environment. Due to the high demand of accuracy and the enormous amount of data to be fused and processed, common architectures used today, like single-core processors in automotive Electronic Control Units (ECUs), do not provide enough computing power. Here, emerging embedded multi-core architectures are appealing such as embedded Graphics Processing Units (GPUs). In this paper, we (a) identify and analyze common subalgorithms of ADAS algorithms for computing environment maps, such as interval maps, for suitability to be parallelized and run on embedded GPUs. From this analysis, (b) performance models are derived on achievable speedups with respect to sequential single-core CPU implementations. (c) As a third contribution of this paper, these performance models are validated by presenting and comparing a novel parallelized interval map GPU implementation against a parallel occupancy grid map implementation. For both types of environment maps, implementations on an Nvidia Tegra K1 prototype are compared to verify the correctness of the introduced performance models. Finally, the achievable speedups with respect to a single-core CPU solution are reported. These range from 3x to 275x for interval and grid map computations.
{"title":"Modeling, programming and performance analysis of automotive environment map representations on embedded GPUs","authors":"Jörg Fickenscher, Oliver Reiche, Jens Schlumberger, Frank Hannig, J. Teich","doi":"10.1109/HLDVT.2016.7748257","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748257","url":null,"abstract":"Future Advanced Driver Assistance Systems (ADAS) require the continuous computation of detailed maps of the vehicle's environment. Due to the high demand of accuracy and the enormous amount of data to be fused and processed, common architectures used today, like single-core processors in automotive Electronic Control Units (ECUs), do not provide enough computing power. Here, emerging embedded multi-core architectures are appealing such as embedded Graphics Processing Units (GPUs). In this paper, we (a) identify and analyze common subalgorithms of ADAS algorithms for computing environment maps, such as interval maps, for suitability to be parallelized and run on embedded GPUs. From this analysis, (b) performance models are derived on achievable speedups with respect to sequential single-core CPU implementations. (c) As a third contribution of this paper, these performance models are validated by presenting and comparing a novel parallelized interval map GPU implementation against a parallel occupancy grid map implementation. For both types of environment maps, implementations on an Nvidia Tegra K1 prototype are compared to verify the correctness of the introduced performance models. Finally, the achievable speedups with respect to a single-core CPU solution are reported. These range from 3x to 275x for interval and grid map computations.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132808318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/HLDVT.2016.7748249
J. G. Tong, M. Boule, Z. Zilic
In this paper, we show how two key techniques in the testing and verification areas - namely mutation testing and assertion based verification (ABV) - can be combined in a novel way to help improve the effectiveness of verifying design correctness. Through assertion based test generation, multiple mutated designs and their test sequences are concurrently simulated using a GPU, in order to determine an essential question in ABV: are the assertions effective at identifying design errors? Exploiting multiple parallelism factors, we show notable improvements in accelerating the simulations procedures that help to answer this fundamental question.
{"title":"Accelerating assertion assessment using GPUs","authors":"J. G. Tong, M. Boule, Z. Zilic","doi":"10.1109/HLDVT.2016.7748249","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748249","url":null,"abstract":"In this paper, we show how two key techniques in the testing and verification areas - namely mutation testing and assertion based verification (ABV) - can be combined in a novel way to help improve the effectiveness of verifying design correctness. Through assertion based test generation, multiple mutated designs and their test sequences are concurrently simulated using a GPU, in order to determine an essential question in ABV: are the assertions effective at identifying design errors? Exploiting multiple parallelism factors, we show notable improvements in accelerating the simulations procedures that help to answer this fundamental question.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123679118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/HLDVT.2016.7748253
Yusuke Kimura, M. Fujita
It is difficult to specify a system completely with formal methods. There are don't care situations which may not be so clearly defined, and behaviors of some special cases are hard to describe. Recently, it has been found that if the changes inside a design are local (limited within a set of sub-circuits), complete verification becomes feasible with small numbers of simulations. This gives us a way to specify a system as a modification of an existing design. By defining which portions of the existing design should be modified in which ways, it can become a design for the new specification. In this paper, we propose such a specification method, i.e., specifying new designs by giving existing designs and use-cases that discribes the difference from the new specification. The difference may be completely described with a small set of simulation patterns. Illustrative examples and some preliminary experimental results are shown.
{"title":"Specification by existing design plus use-cases","authors":"Yusuke Kimura, M. Fujita","doi":"10.1109/HLDVT.2016.7748253","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748253","url":null,"abstract":"It is difficult to specify a system completely with formal methods. There are don't care situations which may not be so clearly defined, and behaviors of some special cases are hard to describe. Recently, it has been found that if the changes inside a design are local (limited within a set of sub-circuits), complete verification becomes feasible with small numbers of simulations. This gives us a way to specify a system as a modification of an existing design. By defining which portions of the existing design should be modified in which ways, it can become a design for the new specification. In this paper, we propose such a specification method, i.e., specifying new designs by giving existing designs and use-cases that discribes the difference from the new specification. The difference may be completely described with a small set of simulation patterns. Illustrative examples and some preliminary experimental results are shown.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127875741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/HLDVT.2016.7748256
Sebastian Reiter, A. Viehl, O. Bringmann, W. Rosenstiel
The ever-increasing number of safety-related, complex, interconnected electronic systems results in new challenges. We propose a comprehensive fault injection ecosystem applicable along the design process to cope with these challenges. Simulation models are extended with fault injectors and used to assess the effects of faults. Our approach solves challenges specific to abstract system models and the reuse of existing simulation models. The proposed ecosystem consists of a system simulation infrastructure, a fault specification with dynamic fault injection, a fault effect classification and a graphical user interface. The simulation infrastructure enables the reuse and variation of simulation models and supports design space explorations. Our fault specification enables the specification and simulation of faults at different abstraction levels, especially at the abstract system level. The minimal invasive fault injection approach reduces the manual overhead when using existing simulation models and supports models of different abstraction levels. A failure classification extends the traditional verification methods. A graphical user interface simplifies the application and automatic code generation reduces the manual effort. The analysis of a driver assistance system demonstrates the usage of the proposed ecosystem.
{"title":"Fault injection ecosystem for assisted safety validation of automotive systems","authors":"Sebastian Reiter, A. Viehl, O. Bringmann, W. Rosenstiel","doi":"10.1109/HLDVT.2016.7748256","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748256","url":null,"abstract":"The ever-increasing number of safety-related, complex, interconnected electronic systems results in new challenges. We propose a comprehensive fault injection ecosystem applicable along the design process to cope with these challenges. Simulation models are extended with fault injectors and used to assess the effects of faults. Our approach solves challenges specific to abstract system models and the reuse of existing simulation models. The proposed ecosystem consists of a system simulation infrastructure, a fault specification with dynamic fault injection, a fault effect classification and a graphical user interface. The simulation infrastructure enables the reuse and variation of simulation models and supports design space explorations. Our fault specification enables the specification and simulation of faults at different abstraction levels, especially at the abstract system level. The minimal invasive fault injection approach reduces the manual overhead when using existing simulation models and supports models of different abstraction levels. A failure classification extends the traditional verification methods. A graphical user interface simplifies the application and automatic code generation reduces the manual effort. The analysis of a driver assistance system demonstrates the usage of the proposed ecosystem.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117258491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/HLDVT.2016.7748248
Mohamed O. Kayed, Mohamed Abdelsalam, R. Guindi
System Verilog Assertions (SVA) is widely used by hardware designers and verification engineers to apply Assertion Based Verification (ABV) methodology on their hardware designs. However, the complexity in understanding different protocol standards in general and JEDEC memory protocol standards in specific imposes numerous difficulties on designers and verification engineers when translating design specifications into SVA. This motivated us to devise new techniques that can be used to automatically generate SVA for DDR memory protocols with no ambiguity when capturing design requirements from JEDEC standards. Moreover, the proposed assertions generation methods generate "synthesizable SVA", hence allowing hardware designers and verification engineers to use the generated assertions to check the functionality of their design implementation on hardware emulation platforms. The viability and the potential of our work are demonstrated with an Industrial case study using JEDEC LPDDR3 Memory Protocol Standard.
{"title":"Synthesizable SVA protocol checker generation methodology based on TDML and VCD file formats","authors":"Mohamed O. Kayed, Mohamed Abdelsalam, R. Guindi","doi":"10.1109/HLDVT.2016.7748248","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748248","url":null,"abstract":"System Verilog Assertions (SVA) is widely used by hardware designers and verification engineers to apply Assertion Based Verification (ABV) methodology on their hardware designs. However, the complexity in understanding different protocol standards in general and JEDEC memory protocol standards in specific imposes numerous difficulties on designers and verification engineers when translating design specifications into SVA. This motivated us to devise new techniques that can be used to automatically generate SVA for DDR memory protocols with no ambiguity when capturing design requirements from JEDEC standards. Moreover, the proposed assertions generation methods generate \"synthesizable SVA\", hence allowing hardware designers and verification engineers to use the generated assertions to check the functionality of their design implementation on hardware emulation platforms. The viability and the potential of our work are demonstrated with an Industrial case study using JEDEC LPDDR3 Memory Protocol Standard.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128400910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/HLDVT.2016.7748255
Prachi Joshi, G. VedahariNarasimhan, Haibo Zeng, S. Shukla, Chung-Wei Lin, Huafeng Yu
Time Triggered Ethernet (TTE) is a time-triggered network technology with large bandwidth and services for deterministic, safety-relevant communication. Hence, it has gained increasing attention from domains such as aerospace, automotive and industrial applications. In this work, we aim to solve the problem of task mapping and communication scheduling in automotive design. The system model is a dataflow task communication model mapped to a target architecture based on TIE. The design variables are the mapping of tasks onto the end systems in the architecture and the scheduling of all frames. The constraints include the schedulability of tasks and signals, as well as the latency constraints of the critical paths as specified by the designer. It can be shown that the problem is NP· hard. Therefore, we develop a heuristic to solve this problem. The heuristic contains four steps and all of them (except scheduling) are formulated using Integer Linear Programming (ILP). We present experimental results on an industrial benchmark and two synthetic benchmarks which show the efficiency and scalability of our approach.
{"title":"Design space exploration for deterministic ethernet-based architecture of automotive systems","authors":"Prachi Joshi, G. VedahariNarasimhan, Haibo Zeng, S. Shukla, Chung-Wei Lin, Huafeng Yu","doi":"10.1109/HLDVT.2016.7748255","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748255","url":null,"abstract":"Time Triggered Ethernet (TTE) is a time-triggered network technology with large bandwidth and services for deterministic, safety-relevant communication. Hence, it has gained increasing attention from domains such as aerospace, automotive and industrial applications. In this work, we aim to solve the problem of task mapping and communication scheduling in automotive design. The system model is a dataflow task communication model mapped to a target architecture based on TIE. The design variables are the mapping of tasks onto the end systems in the architecture and the scheduling of all frames. The constraints include the schedulability of tasks and signals, as well as the latency constraints of the critical paths as specified by the designer. It can be shown that the problem is NP· hard. Therefore, we develop a heuristic to solve this problem. The heuristic contains four steps and all of them (except scheduling) are formulated using Integer Linear Programming (ILP). We present experimental results on an industrial benchmark and two synthetic benchmarks which show the efficiency and scalability of our approach.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123291786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/HLDVT.2016.7748258
J. Abraham
Computers are pervasive in society because advances in integrated circuit (IC) technology have enabled increased performance and reduced costs. In many critical applications, the ICs need to continue to operate correctly in spite of manufacturing defects, as well as failures during operation due to wearout or external disturbances. Although thorough testing of the ICs is part of the manufacturing cycle, some defects may escape the screening; during operation, interconnects may wear out due to electromigration and transistors could degrade (for example, due to negative bias temperature instability (NBTI)). This could result in incorrect results produced by the circuits. Errors can also be produced during operation due to crosstalk, voltage droops (which lead to increased delays in critical paths), single event upsets due to external radiation, etc. Therefore, systems comprising the ICs need to be designed to be resilient, i.e., detect and correct errors due to failures.
{"title":"Cross-layer resilience: are high-level techniques always better?","authors":"J. Abraham","doi":"10.1109/HLDVT.2016.7748258","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748258","url":null,"abstract":"Computers are pervasive in society because advances in integrated circuit (IC) technology have enabled increased performance and reduced costs. In many critical applications, the ICs need to continue to operate correctly in spite of manufacturing defects, as well as failures during operation due to wearout or external disturbances. Although thorough testing of the ICs is part of the manufacturing cycle, some defects may escape the screening; during operation, interconnects may wear out due to electromigration and transistors could degrade (for example, due to negative bias temperature instability (NBTI)). This could result in incorrect results produced by the circuits. Errors can also be produced during operation due to crosstalk, voltage droops (which lead to increased delays in critical paths), single event upsets due to external radiation, etc. Therefore, systems comprising the ICs need to be designed to be resilient, i.e., detect and correct errors due to failures.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125897858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/HLDVT.2016.7748273
Qinsi Wang, E. Clarke
As biomedical research advances into more complicated systems, there is an increasing need to model and analyze these systems to better understand them. For decades, biologists have been using diagrammatic models to describe and understand the mechanisms and dynamics behind their experimental observations. Although these models are simple to be built and understood, they can only offer a rather static picture of the corresponding biological systems, and scalability is limited. Thus, there is an increasing need to develop formalism into more dynamic forms that can capture time-dependent processes, together with increases in the models scale and complexity. In this invited review paper, we argue that the formal modeling formalisms can be applied fruitfully to biological systems, and can be complementary to the traditional mathematical descriptive modeling approaches used in systems biology. We also discuss one example: a stochastic hybrid model of the effect of estrogen at different levels in species' population in a freshwater ecosystem.
{"title":"Formal modeling of biological systems","authors":"Qinsi Wang, E. Clarke","doi":"10.1109/HLDVT.2016.7748273","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748273","url":null,"abstract":"As biomedical research advances into more complicated systems, there is an increasing need to model and analyze these systems to better understand them. For decades, biologists have been using diagrammatic models to describe and understand the mechanisms and dynamics behind their experimental observations. Although these models are simple to be built and understood, they can only offer a rather static picture of the corresponding biological systems, and scalability is limited. Thus, there is an increasing need to develop formalism into more dynamic forms that can capture time-dependent processes, together with increases in the models scale and complexity. In this invited review paper, we argue that the formal modeling formalisms can be applied fruitfully to biological systems, and can be complementary to the traditional mathematical descriptive modeling approaches used in systems biology. We also discuss one example: a stochastic hybrid model of the effect of estrogen at different levels in species' population in a freshwater ecosystem.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128726836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/HLDVT.2016.7748268
Xiaojun Sun, P. Kalla, Florian Enescu
Reachability analysis is a tool for formal equivalence and model checking of sequential circuits. Conventional techniques are mostly bit-level, in that the reachable states, transition relations and property predicates are all represented using Boolean variables and functions. The problem suffers from exponential space and time complexities; therefore, some form of abstraction is desirable. This paper introduces a new concept of implicit state enumeration of finite state machines (FSMs) performed at the word-level. Using algebraic geometry, we show that the state-space of a sequential circuit can be encoded, canonically, as the zeros of a word-level polynomial F (S) over the Galois field F2k, where S = {s0, ..., sk-1} is the word-level representation of a k-bit state register. Subsequently, concepts of elimination ideals and Grobner bases can be employed for FSM traversal. The paper describes the complete theory of word-level FSM traversal and demonstrates the feasibility of the approach with experiments over a set of sequential circuit benchmarks.
{"title":"Word-level traversal of finite state machines using algebraic geometry","authors":"Xiaojun Sun, P. Kalla, Florian Enescu","doi":"10.1109/HLDVT.2016.7748268","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748268","url":null,"abstract":"Reachability analysis is a tool for formal equivalence and model checking of sequential circuits. Conventional techniques are mostly bit-level, in that the reachable states, transition relations and property predicates are all represented using Boolean variables and functions. The problem suffers from exponential space and time complexities; therefore, some form of abstraction is desirable. This paper introduces a new concept of implicit state enumeration of finite state machines (FSMs) performed at the word-level. Using algebraic geometry, we show that the state-space of a sequential circuit can be encoded, canonically, as the zeros of a word-level polynomial F (S) over the Galois field F2k, where S = {s0, ..., sk-1} is the word-level representation of a k-bit state register. Subsequently, concepts of elimination ideals and Grobner bases can be employed for FSM traversal. The paper describes the complete theory of word-level FSM traversal and demonstrates the feasibility of the approach with experiments over a set of sequential circuit benchmarks.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128844404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/HLDVT.2016.7748265
Eman El Mandouh, A. Wassal
Formal Verification is a computationally expensive step in the verification of today's complex hardware designs. Effective results can be obtained from formal runs by planning ahead the effort and cost that are required for them. Additionally estimating in-advance the expected formal's complexity promotes a lot of potential tricks and clever setup techniques to overcome the initial push-button capacity limitation of the formal verifies and improve their capabilities to handle designs with higher complexity. This paper illustrates the application of regression machine learning (ML) techniques to build an estimation model for the cost of formal verification. Up to 10,000 formal verification runs on RTL designs with good varieties of design/properties attributes are used to learn the relationship between HW designs and the final formal cost in terms of formal run time. We demonstrate the use of Ridge-Regression to decide on the bias-variance trade-off during the regression-model design step as well as the application of Lasso-Regression for the feature selection phase. Finally a comparison between the proposed multiple linear regression approach and another non-parametric K-nearest neighbors kernel based regression technique is done to conclude on the presented work. Our results indicate how the proposed model managed to estimate with reasonable error ratio the expected formal verification effort for new-to-verify HW designs.
{"title":"Estimation of formal verification cost using regression machine learning","authors":"Eman El Mandouh, A. Wassal","doi":"10.1109/HLDVT.2016.7748265","DOIUrl":"https://doi.org/10.1109/HLDVT.2016.7748265","url":null,"abstract":"Formal Verification is a computationally expensive step in the verification of today's complex hardware designs. Effective results can be obtained from formal runs by planning ahead the effort and cost that are required for them. Additionally estimating in-advance the expected formal's complexity promotes a lot of potential tricks and clever setup techniques to overcome the initial push-button capacity limitation of the formal verifies and improve their capabilities to handle designs with higher complexity. This paper illustrates the application of regression machine learning (ML) techniques to build an estimation model for the cost of formal verification. Up to 10,000 formal verification runs on RTL designs with good varieties of design/properties attributes are used to learn the relationship between HW designs and the final formal cost in terms of formal run time. We demonstrate the use of Ridge-Regression to decide on the bias-variance trade-off during the regression-model design step as well as the application of Lasso-Regression for the feature selection phase. Finally a comparison between the proposed multiple linear regression approach and another non-parametric K-nearest neighbors kernel based regression technique is done to conclude on the presented work. Our results indicate how the proposed model managed to estimate with reasonable error ratio the expected formal verification effort for new-to-verify HW designs.","PeriodicalId":166427,"journal":{"name":"2016 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129075497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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