Pub Date : 2018-11-01DOI: 10.1109/ICRC.2018.8638594
N. Ganesh
There is a significant amount of interest in the field of big data and machine learning right now. This has been driven by use of sophisticated learning algorithms along with large datasets and powerful computing hardware to achieve extraordinary success in narrow tasks. Such success has been classified as narrow artificial intelligence (AI), in order to distinguish it from general intelligence, which continues to be the holy grail of computing. If we are to progress from narrow to general AI, it is important to have a better understanding of what intelligence is and what it entails. As we seek to reboot computing across the stack, this is an important question to address, to help us identify the optimal devices, architectures and design techniques that will allow us to build the intelligent systems of the future. In this paper, I will review the fundamental ideas and assumptions that have allowed us to achieve computing in artificial systems over the years. Building off these ideas, I will discuss the important distinction between a good example of a system with general intelligence i.e. ourselves, and the intelligence achieved through our current computational approaches. Following this, I will use recent results to explore a new framework - a physically grounded theory of thermodynamic intelligence, and discuss the design paradigm that seeks to achieve such intelligence in systems.
{"title":"Thermodynamic Intelligence, a Heretical Theory","authors":"N. Ganesh","doi":"10.1109/ICRC.2018.8638594","DOIUrl":"https://doi.org/10.1109/ICRC.2018.8638594","url":null,"abstract":"There is a significant amount of interest in the field of big data and machine learning right now. This has been driven by use of sophisticated learning algorithms along with large datasets and powerful computing hardware to achieve extraordinary success in narrow tasks. Such success has been classified as narrow artificial intelligence (AI), in order to distinguish it from general intelligence, which continues to be the holy grail of computing. If we are to progress from narrow to general AI, it is important to have a better understanding of what intelligence is and what it entails. As we seek to reboot computing across the stack, this is an important question to address, to help us identify the optimal devices, architectures and design techniques that will allow us to build the intelligent systems of the future. In this paper, I will review the fundamental ideas and assumptions that have allowed us to achieve computing in artificial systems over the years. Building off these ideas, I will discuss the important distinction between a good example of a system with general intelligence i.e. ourselves, and the intelligence achieved through our current computational approaches. Following this, I will use recent results to explore a new framework - a physically grounded theory of thermodynamic intelligence, and discuss the design paradigm that seeks to achieve such intelligence in systems.","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115746451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/ICRC.2018.8638603
Catherine E. Graves, W. Ma, X. Sheng, B. Buchanan, Le Zheng, Sity Lam, Xuema Li, S. R. Chalamalasetti, Lennie Kiyama, M. Foltin, Matthew P. Hardy, J. Strachan
Regular expression (RegEx)matching is a key function in network security, where matching of packet data against known malicious signatures filters and alerts against active network intrusions. RegExs are widely used in open source and commercial network security systems as they easily and concisely represent complex patterns like those malicious signatures. However, the latency and power required to perform RegEx matching is incredibly high and approaches to this problem struggle to achieve > 1 Gbps on real-world rulesets while internet wirespeeds continue to increase > 100 Gbps. We propose performing RegEx matching using memristor-based ternary content addressable memories (mTCAMs)with compressed finite automata (CFA)to meet this challenge. In this work, we show fabrication of mTCAM circuits with excellent device properties from 100nm to 20nm device sizes and validate mTCAM operation. SPICE simulations investigate mTCAM performance at scale and a mTCAM dynamic power model using 16nm mTCAM layout parameters demonstrates 0.173 fJ/bit/search energy for a $36times 250$ mTCAM array. Using a tiled architecture to implement a Snort ruleset, we estimate performance of our mTCAM approach to be 47.2 Gbps at 1.21W dynamic search power (39 Gbps/W), compared to a state-of-the-art FPGA approach which achieves 3.9 Gbps at 630mW (6.2 Gbps/W). Preliminary error analysis shows the mTCAM approach allows for arbitrarily low false positive/negative rates using minimal and standard state refresh techniques. Dynamic search power is also calculated prior to applying standard TCAM power-reduction techniques capable of lowering power by $simtimes 10$, further demonstrating the promise of mTCAM for wirespeed RegEx matching at low power.
{"title":"Regular Expression Matching with Memristor TCAMs","authors":"Catherine E. Graves, W. Ma, X. Sheng, B. Buchanan, Le Zheng, Sity Lam, Xuema Li, S. R. Chalamalasetti, Lennie Kiyama, M. Foltin, Matthew P. Hardy, J. Strachan","doi":"10.1109/ICRC.2018.8638603","DOIUrl":"https://doi.org/10.1109/ICRC.2018.8638603","url":null,"abstract":"Regular expression (RegEx)matching is a key function in network security, where matching of packet data against known malicious signatures filters and alerts against active network intrusions. RegExs are widely used in open source and commercial network security systems as they easily and concisely represent complex patterns like those malicious signatures. However, the latency and power required to perform RegEx matching is incredibly high and approaches to this problem struggle to achieve > 1 Gbps on real-world rulesets while internet wirespeeds continue to increase > 100 Gbps. We propose performing RegEx matching using memristor-based ternary content addressable memories (mTCAMs)with compressed finite automata (CFA)to meet this challenge. In this work, we show fabrication of mTCAM circuits with excellent device properties from 100nm to 20nm device sizes and validate mTCAM operation. SPICE simulations investigate mTCAM performance at scale and a mTCAM dynamic power model using 16nm mTCAM layout parameters demonstrates 0.173 fJ/bit/search energy for a $36times 250$ mTCAM array. Using a tiled architecture to implement a Snort ruleset, we estimate performance of our mTCAM approach to be 47.2 Gbps at 1.21W dynamic search power (39 Gbps/W), compared to a state-of-the-art FPGA approach which achieves 3.9 Gbps at 630mW (6.2 Gbps/W). Preliminary error analysis shows the mTCAM approach allows for arbitrarily low false positive/negative rates using minimal and standard state refresh techniques. Dynamic search power is also calculated prior to applying standard TCAM power-reduction techniques capable of lowering power by $simtimes 10$, further demonstrating the promise of mTCAM for wirespeed RegEx matching at low power.","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"44 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116270759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/ICRC.2018.8638595
S. Buckley, A. McCaughan, J. Chiles, R. Mirin, S. Nam, J. Shainline, Grant Bruer, J. Plank, Catherine D. Schuman
We have previously proposed a novel hardware platform (SOEN) for neuromorphic computing based on superconducting optoelectronics that presents many of the features necessary for information processing in the brain. Here we discuss the design and training of networks of neurons and synapses based on this technology. We present circuit models for the simplest neurons and synapses that we can use to build networks. We discuss the further abstracted integrate and fire model that we use for evolutionary optimization of small networks of these neurons. We show that we can use the TENNLab evolutionary optimization programming framework to design small networks for logic, control and classification tasks. We plan to use the results as feedback to inform our neuron design.
{"title":"Design of Superconducting Optoelectronic Networks for Neuromorphic Computing","authors":"S. Buckley, A. McCaughan, J. Chiles, R. Mirin, S. Nam, J. Shainline, Grant Bruer, J. Plank, Catherine D. Schuman","doi":"10.1109/ICRC.2018.8638595","DOIUrl":"https://doi.org/10.1109/ICRC.2018.8638595","url":null,"abstract":"We have previously proposed a novel hardware platform (SOEN) for neuromorphic computing based on superconducting optoelectronics that presents many of the features necessary for information processing in the brain. Here we discuss the design and training of networks of neurons and synapses based on this technology. We present circuit models for the simplest neurons and synapses that we can use to build networks. We discuss the further abstracted integrate and fire model that we use for evolutionary optimization of small networks of these neurons. We show that we can use the TENNLab evolutionary optimization programming framework to design small networks for logic, control and classification tasks. We plan to use the results as feedback to inform our neuron design.","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"1998 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129758030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/icrc.2018.8638615
{"title":"2018 IEEE International Conference on Rebooting Computing, ICRC 2018, McLean, VA, USA, November 7-9, 2018","authors":"","doi":"10.1109/icrc.2018.8638615","DOIUrl":"https://doi.org/10.1109/icrc.2018.8638615","url":null,"abstract":"","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130345113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/ICRC.2018.8638607
Takumi Egawa, T. Ishihara, H. Onodera, A. Shinya, S. Kita, K. Nozaki, K. Takata, M. Notomi
Optical circuits constructed using nanophotonic logic gates have attracted significant attention due to its ultra low-latency operation. This paper first introduces conventional optical logic circuits and their issues when the number of inputs is large. Then, we propose a method of minimizing the latency of large fan-in optical logic circuits using a multi-level optimization method. The proposed optimization method reduces not only the delay but also the attenuation of light involved in the circuits. Experimental results obtained targeting a 1024-bit pattern matching circuit show that the circuit optimized with our method is 1.72 times faster than the traditional optical circuit composed of the optical logic gates connected in series, and it is 3.40 times faster than the CMOS 32 nm circuit.
{"title":"Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics","authors":"Takumi Egawa, T. Ishihara, H. Onodera, A. Shinya, S. Kita, K. Nozaki, K. Takata, M. Notomi","doi":"10.1109/ICRC.2018.8638607","DOIUrl":"https://doi.org/10.1109/ICRC.2018.8638607","url":null,"abstract":"Optical circuits constructed using nanophotonic logic gates have attracted significant attention due to its ultra low-latency operation. This paper first introduces conventional optical logic circuits and their issues when the number of inputs is large. Then, we propose a method of minimizing the latency of large fan-in optical logic circuits using a multi-level optimization method. The proposed optimization method reduces not only the delay but also the attenuation of light involved in the circuits. Experimental results obtained targeting a 1024-bit pattern matching circuit show that the circuit optimized with our method is 1.72 times faster than the traditional optical circuit composed of the optical logic gates connected in series, and it is 3.40 times faster than the CMOS 32 nm circuit.","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124038127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/ICRC.2018.8638604
Ramtin Zand, R. Demara
In this paper, a spintronic neuromorphic reconfigurable Array (SNRA)is developed to fuse together power-efficient probabilistic and in-field programmable deterministic computing during both training and evaluation phases of restricted Boltzmann machines (RBMs). First, probabilistic spin logic devices are used to develop an RBM realization which is adapted to construct deep belief networks (DBNs)having one to three hidden layers of size 10 to 800 neurons each. Second, we design a hardware implementation for the contrastive divergence (CD)algorithm using a four-state finite state machine capable of unsupervised training in N+3 clocks where N denotes the number of neurons in each RBM. The functionality of our proposed CD hardware implementation is validated using ModelSim simulations. We synthesize the developed Verilog HDL implementation of our proposed test/train control circuitry for various DBN topologies where the maximal RBM dimensions yield resource utilization ranging from 51 to 2,421 lookup tables (LUTs). Next, we leverage spin Hall effect (SHE)-magnetic tunnel junction (MTJ)based non-volatile LUTs circuits as an alternative for static random access memory (SRAM)-based LUTs storing the deterministic logic configuration to form a reconfigurable fabric. Finally, we compare the performance of our proposed SNRA with SRAM-based configurable fabrics focusing on the area and power consumption induced by the LUTs used to implement both CD and evaluation modes. The results obtained indicate more than 80% reduction in combined dynamic and static power dissipation, while achieving at least 50% reduction in device count.
{"title":"SNRA: A Spintronic Neuromorphic Reconfigurable Array for In-Circuit Training and Evaluation of Deep Belief Networks","authors":"Ramtin Zand, R. Demara","doi":"10.1109/ICRC.2018.8638604","DOIUrl":"https://doi.org/10.1109/ICRC.2018.8638604","url":null,"abstract":"In this paper, a spintronic neuromorphic reconfigurable Array (SNRA)is developed to fuse together power-efficient probabilistic and in-field programmable deterministic computing during both training and evaluation phases of restricted Boltzmann machines (RBMs). First, probabilistic spin logic devices are used to develop an RBM realization which is adapted to construct deep belief networks (DBNs)having one to three hidden layers of size 10 to 800 neurons each. Second, we design a hardware implementation for the contrastive divergence (CD)algorithm using a four-state finite state machine capable of unsupervised training in N+3 clocks where N denotes the number of neurons in each RBM. The functionality of our proposed CD hardware implementation is validated using ModelSim simulations. We synthesize the developed Verilog HDL implementation of our proposed test/train control circuitry for various DBN topologies where the maximal RBM dimensions yield resource utilization ranging from 51 to 2,421 lookup tables (LUTs). Next, we leverage spin Hall effect (SHE)-magnetic tunnel junction (MTJ)based non-volatile LUTs circuits as an alternative for static random access memory (SRAM)-based LUTs storing the deterministic logic configuration to form a reconfigurable fabric. Finally, we compare the performance of our proposed SNRA with SRAM-based configurable fabrics focusing on the area and power consumption induced by the LUTs used to implement both CD and evaluation modes. The results obtained indicate more than 80% reduction in combined dynamic and static power dissipation, while achieving at least 50% reduction in device count.","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121451471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/ICRC.2018.8638619
Anirudh Jain, S. Srikanth, E. Debenedictis, T. Krishna
Logic-memory integration helps mitigate the von Neumann bottleneck, and this has enabled a new class of architectures that helps accelerate graph analytics and operations on sparse data streams. These utilize merge networks as a key unit of computation. Such networks are highly parallel and their performance increases with tighter coupling between logic and memory when a bitonic algorithm is used. This paper presents energy-efficient on-chip network architectures for merging key-value pairs using both word-parallel and bit-serial paradigms. The proposed architectures are capable of merging two rows of high bandwidth memory (HBM)worth of data in a manner that is completely overlapped with the reading from and writing back to such a row. Furthermore, their energy consumption is about an order of magnitude lower when compared to a naive crossbar based design.
{"title":"Merge Network for a Non-Von Neumann Accumulate Accelerator in a 3D Chip","authors":"Anirudh Jain, S. Srikanth, E. Debenedictis, T. Krishna","doi":"10.1109/ICRC.2018.8638619","DOIUrl":"https://doi.org/10.1109/ICRC.2018.8638619","url":null,"abstract":"Logic-memory integration helps mitigate the von Neumann bottleneck, and this has enabled a new class of architectures that helps accelerate graph analytics and operations on sparse data streams. These utilize merge networks as a key unit of computation. Such networks are highly parallel and their performance increases with tighter coupling between logic and memory when a bitonic algorithm is used. This paper presents energy-efficient on-chip network architectures for merging key-value pairs using both word-parallel and bit-serial paradigms. The proposed architectures are capable of merging two rows of high bandwidth memory (HBM)worth of data in a manner that is completely overlapped with the reading from and writing back to such a row. Furthermore, their energy consumption is about an order of magnitude lower when compared to a naive crossbar based design.","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114328115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/ICRC.2018.8638600
T. C. Jackson, S. Pagliarini, L. Pileggi
Implementing scalable and effective synaptic networks will enable neuromorphic computing to deliver on its promise of revolutionizing computing. RRAM represents the most promising technology for realizing the fully connected synapse network: By using programmable resistive elements as weights, RRAM can modulate the strength of synapses in a neural network architecture. Oscillatory Neural Networks (ONNs)that are based on phase-locked loop (PLL)neurons are compatible with the resistive synapses but otherwise rather impractical. In this paper, A PLL-free ONN is implemented in 28 nm CMOS and compared to its PLL-based counterpart. Our silicon results show that the PLL-free architecture is compatible with resistive synapses, addresses practical implementation issues for improved robustness, and demonstrates favorable energy consumption compared to state-of-the-art NNs.
{"title":"An Oscillatory Neural Network with Programmable Resistive Synapses in 28 Nm CMOS","authors":"T. C. Jackson, S. Pagliarini, L. Pileggi","doi":"10.1109/ICRC.2018.8638600","DOIUrl":"https://doi.org/10.1109/ICRC.2018.8638600","url":null,"abstract":"Implementing scalable and effective synaptic networks will enable neuromorphic computing to deliver on its promise of revolutionizing computing. RRAM represents the most promising technology for realizing the fully connected synapse network: By using programmable resistive elements as weights, RRAM can modulate the strength of synapses in a neural network architecture. Oscillatory Neural Networks (ONNs)that are based on phase-locked loop (PLL)neurons are compatible with the resistive synapses but otherwise rather impractical. In this paper, A PLL-free ONN is implemented in 28 nm CMOS and compared to its PLL-based counterpart. Our silicon results show that the PLL-free architecture is compatible with resistive synapses, addresses practical implementation issues for improved robustness, and demonstrates favorable energy consumption compared to state-of-the-art NNs.","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125857671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/ICRC.2018.8638597
B. Cour, S. Lanham, Corey I. Ostrove
Quantum computers provide a fundamentally new computing paradigm that promises to revolutionize our ability to solve broad classes of problems. Surprisingly, the basic mathematical structures of gate-based quantum computing, such as unitary operations on a finite-dimensional Hilbert space, are not unique to quantum systems but may be found in certain classical systems as well. Previously, it has been shown that one can represent an arbitrary multi-qubit quantum state in terms of classical analog signals using nested quadrature amplitude modulated signals. Furthermore, using digitally controlled analog electronics one may manipulate these signals to perform quantum gate operations and thereby execute quantum algorithms. The computational capacity of a single signal is, however, limited by the required bandwidth, which scales exponentially with the number of qubits when represented using frequency-based encoding. To overcome this limitation, we introduce a method to extend this approach to multiple parallel signals. Doing so allows a larger quantum state to be emulated with the same gate time required for processing frequency-encoded signals. In the proposed representation, each doubling of the number of signals corresponds to an additional qubit in the spatial domain. Single quit gate operations are similarly extended so as to operate on qubits represented using either frequency-based or spatial encoding schemes. Furthermore, we describe a method to perform gate operations between pairs of qubits represented using frequency or spatial encoding or between frequency-based and spatially encoded qubits. Finally, we describe how this approach may be extended to represent qubits in the time domain as well.
{"title":"Parallel Quantum Computing Emulation","authors":"B. Cour, S. Lanham, Corey I. Ostrove","doi":"10.1109/ICRC.2018.8638597","DOIUrl":"https://doi.org/10.1109/ICRC.2018.8638597","url":null,"abstract":"Quantum computers provide a fundamentally new computing paradigm that promises to revolutionize our ability to solve broad classes of problems. Surprisingly, the basic mathematical structures of gate-based quantum computing, such as unitary operations on a finite-dimensional Hilbert space, are not unique to quantum systems but may be found in certain classical systems as well. Previously, it has been shown that one can represent an arbitrary multi-qubit quantum state in terms of classical analog signals using nested quadrature amplitude modulated signals. Furthermore, using digitally controlled analog electronics one may manipulate these signals to perform quantum gate operations and thereby execute quantum algorithms. The computational capacity of a single signal is, however, limited by the required bandwidth, which scales exponentially with the number of qubits when represented using frequency-based encoding. To overcome this limitation, we introduce a method to extend this approach to multiple parallel signals. Doing so allows a larger quantum state to be emulated with the same gate time required for processing frequency-encoded signals. In the proposed representation, each doubling of the number of signals corresponds to an additional qubit in the spatial domain. Single quit gate operations are similarly extended so as to operate on qubits represented using either frequency-based or spatial encoding schemes. Furthermore, we describe a method to perform gate operations between pairs of qubits represented using frequency or spatial encoding or between frequency-based and spatially encoded qubits. Finally, we describe how this approach may be extended to represent qubits in the time domain as well.","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134213114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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