Pub Date : 2018-11-01DOI: 10.1109/ICRC.2018.8638602
Zachary Kahleifeh, S. D. Kumar, H. Thapliyal
In recent years, Hardware Trojans (HT)have become an increasing concern due to outsourcing the manufacturing of Implantable Medical Devices (IMDs). Power Analysis based Side-Channel Attack (SCA)is one of the main methods of detecting HT in IMDs. However, using SCA in detecting trojans is limited by the large process variation effects in IC technology which has reduced detection sensitivity of ultra-small trojans. Along with the safety of IMDs against HTs, the need for power management has also risen in parallel with the increasing complexity of IMDs. In this paper, we are analyzing the usefulness of Differential Power Analysis (DPA)resistant adiabatic logic gates to detect smaller trojans. DPA resistant adiabatic logic gates consume uniform power irrespective of input data transition and also consume lower power compared to conventional CMOS logic gates. When the HT is triggered in the DPA resistant circuits, the circuit will have non-uniform power consumption which will help us to easily identify HTs. In order to validate our proposed methodology, we have implemented a C17 and a carry save adder using a recently proposed DPA resistant adiabatic logic family called Energy-Efficient Secure Positive Feedback Adiabatic Logic Family (EE-SPFAL). Further, in order to calculate the true energy-efficiency of the EE-SPFAL logic, we have proposed a four phase Power Clock Generator (PCG)and integrated with the EE-SPFAL logic circuits. Simulations are performed in Cadence Spectre using 180nm CMOS technology. From our simulations, we have observed the non-uniform power consumption, during the activation of HT, in EE-SPFAL based C17 and carry save adder circuit. Further, EE-SPFAL based C17 and carry save adder along with its PCG consume 25.8% and 31.4% of less power as compared to the conventional CMOS based C17 and carry save adder respectively.
{"title":"Hardware Trojan Detection in Implantable Medical Devices Using Adiabatic Computing","authors":"Zachary Kahleifeh, S. D. Kumar, H. Thapliyal","doi":"10.1109/ICRC.2018.8638602","DOIUrl":"https://doi.org/10.1109/ICRC.2018.8638602","url":null,"abstract":"In recent years, Hardware Trojans (HT)have become an increasing concern due to outsourcing the manufacturing of Implantable Medical Devices (IMDs). Power Analysis based Side-Channel Attack (SCA)is one of the main methods of detecting HT in IMDs. However, using SCA in detecting trojans is limited by the large process variation effects in IC technology which has reduced detection sensitivity of ultra-small trojans. Along with the safety of IMDs against HTs, the need for power management has also risen in parallel with the increasing complexity of IMDs. In this paper, we are analyzing the usefulness of Differential Power Analysis (DPA)resistant adiabatic logic gates to detect smaller trojans. DPA resistant adiabatic logic gates consume uniform power irrespective of input data transition and also consume lower power compared to conventional CMOS logic gates. When the HT is triggered in the DPA resistant circuits, the circuit will have non-uniform power consumption which will help us to easily identify HTs. In order to validate our proposed methodology, we have implemented a C17 and a carry save adder using a recently proposed DPA resistant adiabatic logic family called Energy-Efficient Secure Positive Feedback Adiabatic Logic Family (EE-SPFAL). Further, in order to calculate the true energy-efficiency of the EE-SPFAL logic, we have proposed a four phase Power Clock Generator (PCG)and integrated with the EE-SPFAL logic circuits. Simulations are performed in Cadence Spectre using 180nm CMOS technology. From our simulations, we have observed the non-uniform power consumption, during the activation of HT, in EE-SPFAL based C17 and carry save adder circuit. Further, EE-SPFAL based C17 and carry save adder along with its PCG consume 25.8% and 31.4% of less power as compared to the conventional CMOS based C17 and carry save adder respectively.","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116075246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/ICRC.2018.8638622
Floris Laporte, J. Dambre, P. Bienstman
We propose a new approach for neuromorphic computing on a silicon photonic chip, based on the concept of reservoir computing. The proposed reservoir computer consists of a signal-mixing photonic crystal cavity acting as the reservoir connected to a linear readout layer. The signal mixing cavity has a quarter-stadium shape, which is known to introduce nontrivial mixing of an input wave. This mixing turns out to be very useful in the context of reservoir computing and has been used to tackle several benchmark telecom tasks. We show that the proposed reservoir computer can perform several digital tasks with a very wide region of operation in terms of bitrate, such as up to 6 bit header recognition and performing the XOR between two subsequent bits in a bitstream.
{"title":"Neuromorphic Computing with Signal-Mixing Cavities","authors":"Floris Laporte, J. Dambre, P. Bienstman","doi":"10.1109/ICRC.2018.8638622","DOIUrl":"https://doi.org/10.1109/ICRC.2018.8638622","url":null,"abstract":"We propose a new approach for neuromorphic computing on a silicon photonic chip, based on the concept of reservoir computing. The proposed reservoir computer consists of a signal-mixing photonic crystal cavity acting as the reservoir connected to a linear readout layer. The signal mixing cavity has a quarter-stadium shape, which is known to introduce nontrivial mixing of an input wave. This mixing turns out to be very useful in the context of reservoir computing and has been used to tackle several benchmark telecom tasks. We show that the proposed reservoir computer can perform several digital tasks with a very wide region of operation in terms of bitrate, such as up to 6 bit header recognition and performing the XOR between two subsequent bits in a bitstream.","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116810530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/ICRC.2018.8638610
Naveed Mahmud, E. El-Araby
Quantum algorithms can be efficiently emulated on classical hardware such as field programmable gate arrays (FPGAs), achieving significant speedup over software simulations. However, the increase in the required hardware resources for emulating quantum systems becomes a critical limitation as the number of qubits is increased. In this paper, we propose a scalable emulation framework for modeling quantum algorithms on FPGAs that employs efficient resource scheduling such as space and space-time scheduling. In addition, full floating point precision arithmetic and dataflow non-linear (dynamic)pipelining are also used to achieve higher accuracy and higher throughput. We propose scalable and optimized hardware architectures for Quantum Fourier Transform (QFT)and Grover's search algorithm and demonstrate the scalability of our framework by scaling the system up to 5 fully-entangled qubits. A multi-node (multi-FPGA), state-of-the-art high-performance reconfigurable computer (HPRC)was used for implementation of the proposed architectures. Our experimental results show that by employing efficient resource scheduling techniques, the hardware resource constraints could be mitigated and the proposed emulation framework could be made feasible for emulation of more complex, larger-scale quantum algorithms while maintaining higher accuracy and throughput than existing work.
{"title":"Towards Higher Scalability of Quantum Hardware Emulation Using Efficient Resource Scheduling","authors":"Naveed Mahmud, E. El-Araby","doi":"10.1109/ICRC.2018.8638610","DOIUrl":"https://doi.org/10.1109/ICRC.2018.8638610","url":null,"abstract":"Quantum algorithms can be efficiently emulated on classical hardware such as field programmable gate arrays (FPGAs), achieving significant speedup over software simulations. However, the increase in the required hardware resources for emulating quantum systems becomes a critical limitation as the number of qubits is increased. In this paper, we propose a scalable emulation framework for modeling quantum algorithms on FPGAs that employs efficient resource scheduling such as space and space-time scheduling. In addition, full floating point precision arithmetic and dataflow non-linear (dynamic)pipelining are also used to achieve higher accuracy and higher throughput. We propose scalable and optimized hardware architectures for Quantum Fourier Transform (QFT)and Grover's search algorithm and demonstrate the scalability of our framework by scaling the system up to 5 fully-entangled qubits. A multi-node (multi-FPGA), state-of-the-art high-performance reconfigurable computer (HPRC)was used for implementation of the proposed architectures. Our experimental results show that by employing efficient resource scheduling techniques, the hardware resource constraints could be mitigated and the proposed emulation framework could be made feasible for emulation of more complex, larger-scale quantum algorithms while maintaining higher accuracy and throughput than existing work.","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126318389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/ICRC.2018.8638590
J. George, A. Mehrabian, R. Amin, P. Prucnal, T. El-Ghazawi, V. Sorger
Neural networks require both a weighting of inputs and a nonlinear activation function operating on their sum. Neural network weighting has been demonstrated in integrated photonics with both interferometric and ring-based wavelength division multiplexing. While direct nonlinearity in optics is difficult to achieve without high optical powers, an electro-optic nonlinearity can be created by directly coupling a photodiode to electro-optic modulator. The low capacitance of directly coupling the components results in operating speeds >10 GHz with relatively low power consumption. Here we present a closed form equation for the activation functions created by graphene and quantum well electro-optic absorption modulators capacitively coupled to photodiodes. Our modulator-geometry based and thermal-noise analysis shows that such electro-optic neurons produce SNRs around 60. Performing an MNIST classification inference test on a feed-forward neural network with these electrooptic nodes, with accuracies of about 95% starting a laser power level around 5mW and 20mW for the QW and Graphene-based modulator, respectively. Our findings show regions of realistic operating performance of future optical and photonic neural networks using electro-optic analogue (non-spiking)neurons.
{"title":"Neural Network Activation Functions with Electro-Optic Absorption Modulators","authors":"J. George, A. Mehrabian, R. Amin, P. Prucnal, T. El-Ghazawi, V. Sorger","doi":"10.1109/ICRC.2018.8638590","DOIUrl":"https://doi.org/10.1109/ICRC.2018.8638590","url":null,"abstract":"Neural networks require both a weighting of inputs and a nonlinear activation function operating on their sum. Neural network weighting has been demonstrated in integrated photonics with both interferometric and ring-based wavelength division multiplexing. While direct nonlinearity in optics is difficult to achieve without high optical powers, an electro-optic nonlinearity can be created by directly coupling a photodiode to electro-optic modulator. The low capacitance of directly coupling the components results in operating speeds >10 GHz with relatively low power consumption. Here we present a closed form equation for the activation functions created by graphene and quantum well electro-optic absorption modulators capacitively coupled to photodiodes. Our modulator-geometry based and thermal-noise analysis shows that such electro-optic neurons produce SNRs around 60. Performing an MNIST classification inference test on a feed-forward neural network with these electrooptic nodes, with accuracies of about 95% starting a laser power level around 5mW and 20mW for the QW and Graphene-based modulator, respectively. Our findings show regions of realistic operating performance of future optical and photonic neural networks using electro-optic analogue (non-spiking)neurons.","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128174894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/ICRC.2018.8638612
J. Ambrosi, Aayush Ankit, Rodrigo Antunes, S. R. Chalamalasetti, Soumitra Chatterjee, I. E. Hajj, Guilherme Fachini, P. Faraboschi, M. Foltin, Sitao Huang, Wen-mei W. Hwu, Gustavo Knuppe, Sunil Vishwanathpur Lakshminarasimha, D. Milojicic, Mohan Parthasarathy, Filipe Ribeiro, L. Rosa, K. Roy, P. Silveira, J. Strachan
The increasing deployment of machine learning at the core and at the edge for applications such as video and image recognition has resulted in a number of special purpose accelerators in this domain. However, these accelerators do not have full end-to-end software stacks for application development, resulting in hard-to-develop, proprietary, and suboptimal application programming and executables. In this paper, we describe software stack for a memristor-based hybrid (analog-digital)accelerator. The software stack consists of an ONNX converter, an application optimizer, a compiler, a driver, and emulators. The ONNX converter helps leveraging interoperable neural network models developed on frameworks that support ONNX, such as CNTK, Caffe2, Tensorflow, etc. The application optimization layer adapts these interoperable models to the underlying hardware. The compiler generates executable ISA code that the underlying accelerator can run. Finally, the emulator enables software execution without actual hardware which enables hardware design space exploration and testing. By building a software stack, we have made hybrid memristor-based ML accelerators more accessible to software developers, enabled a generation of better-performing executables, and created an environment that can be leveraged by a multitude of existing neural network models developed using other frameworks to target these accelerators.
{"title":"Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning","authors":"J. Ambrosi, Aayush Ankit, Rodrigo Antunes, S. R. Chalamalasetti, Soumitra Chatterjee, I. E. Hajj, Guilherme Fachini, P. Faraboschi, M. Foltin, Sitao Huang, Wen-mei W. Hwu, Gustavo Knuppe, Sunil Vishwanathpur Lakshminarasimha, D. Milojicic, Mohan Parthasarathy, Filipe Ribeiro, L. Rosa, K. Roy, P. Silveira, J. Strachan","doi":"10.1109/ICRC.2018.8638612","DOIUrl":"https://doi.org/10.1109/ICRC.2018.8638612","url":null,"abstract":"The increasing deployment of machine learning at the core and at the edge for applications such as video and image recognition has resulted in a number of special purpose accelerators in this domain. However, these accelerators do not have full end-to-end software stacks for application development, resulting in hard-to-develop, proprietary, and suboptimal application programming and executables. In this paper, we describe software stack for a memristor-based hybrid (analog-digital)accelerator. The software stack consists of an ONNX converter, an application optimizer, a compiler, a driver, and emulators. The ONNX converter helps leveraging interoperable neural network models developed on frameworks that support ONNX, such as CNTK, Caffe2, Tensorflow, etc. The application optimization layer adapts these interoperable models to the underlying hardware. The compiler generates executable ISA code that the underlying accelerator can run. Finally, the emulator enables software execution without actual hardware which enables hardware design space exploration and testing. By building a software stack, we have made hybrid memristor-based ML accelerators more accessible to software developers, enabled a generation of better-performing executables, and created an environment that can be leveraged by a multitude of existing neural network models developed using other frameworks to target these accelerators.","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132684060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/ICRC.2018.8638626
E. Corti, B. Gotsmann, K. Moselund, I. Stolichnov, A. Ionescu, S. Karg
Oscillator networks are known for their interesting collective behavior such as frequency locking, phase locking, and synchronization. Compared to other artificial neural network implementations, timing rather than amplitude information is used for computation. We have fabricated and simulated small networks of coupled V02 oscillators and investigated the electrical behavior. It is demonstrated experimentally and through simulations that the coupled oscillators lock in frequency and the phase relation can be adjusted by the coupling resistance. Pattern recognition was simulated in resistor-coupled networks with up to nine oscillators (pixels), demonstrating the possibility of implementation of this task with compact VO2 circuits.
{"title":"Resistive Coupled VO2 Oscillators for Image Recognition","authors":"E. Corti, B. Gotsmann, K. Moselund, I. Stolichnov, A. Ionescu, S. Karg","doi":"10.1109/ICRC.2018.8638626","DOIUrl":"https://doi.org/10.1109/ICRC.2018.8638626","url":null,"abstract":"Oscillator networks are known for their interesting collective behavior such as frequency locking, phase locking, and synchronization. Compared to other artificial neural network implementations, timing rather than amplitude information is used for computation. We have fabricated and simulated small networks of coupled V02 oscillators and investigated the electrical behavior. It is demonstrated experimentally and through simulations that the coupled oscillators lock in frequency and the phase relation can be adjusted by the coupling resistance. Pattern recognition was simulated in resistor-coupled networks with up to nine oscillators (pixels), demonstrating the possibility of implementation of this task with compact VO2 circuits.","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123533409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/ICRC.2018.8638614
Jun Shiomi, T. Ishihara, H. Onodera, A. Shinya, M. Notomi
The emergence of nanophotonic devices has enabled to design integrated optical circuits for ultra-high speed on-chip signal processing. This paper proposes an optical implementation of an approximate parallel multiplier for two n-bit integers. The key to ultra-high speed processing is to reduce the number of OptoElectric (OE) converters on a critical path since the OE converters dominantly determine the operating speed of the multiplier. For any n, the proposed approximate multiplier has only three OE converters on a critical path with a deterministic error (11% at the worst case). On the other hand, the number of the counterparts of the conventional parallel multiplier increases as $n$ increases, which implies that the proposed multiplier with large $n$ exhibits much better operating speed than the conventional optical parallel multiplier. Numerical evaluation for n = 16 shows that the proposed multiplier exhibits a 106 ps latency which is 49% less than that of the conventional optical multiplier.
{"title":"An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing","authors":"Jun Shiomi, T. Ishihara, H. Onodera, A. Shinya, M. Notomi","doi":"10.1109/ICRC.2018.8638614","DOIUrl":"https://doi.org/10.1109/ICRC.2018.8638614","url":null,"abstract":"The emergence of nanophotonic devices has enabled to design integrated optical circuits for ultra-high speed on-chip signal processing. This paper proposes an optical implementation of an approximate parallel multiplier for two n-bit integers. The key to ultra-high speed processing is to reduce the number of OptoElectric (OE) converters on a critical path since the OE converters dominantly determine the operating speed of the multiplier. For any n, the proposed approximate multiplier has only three OE converters on a critical path with a deterministic error (11% at the worst case). On the other hand, the number of the counterparts of the conventional parallel multiplier increases as $n$ increases, which implies that the proposed multiplier with large $n$ exhibits much better operating speed than the conventional optical parallel multiplier. Numerical evaluation for n = 16 shows that the proposed multiplier exhibits a 106 ps latency which is 49% less than that of the conventional optical multiplier.","PeriodicalId":169413,"journal":{"name":"2018 IEEE International Conference on Rebooting Computing (ICRC)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121438096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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