Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374376
A. Wahba
The quality of results (QoR) of FPGA synthesis operations is measured by two major criteria; area on chip, and circuit delay. In this paper we address the problem of minimizing the area and delay by filtering the input HDL descriptions to modify the constructs that are harmful to those criteria. A prototype tool was developed to make this filtering automatically, and the obtained results show the efficiency of this approach.
{"title":"HDL filter for optimized area-delay minimization in FPGA synthesis","authors":"A. Wahba","doi":"10.1109/ICEEC.2004.1374376","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374376","url":null,"abstract":"The quality of results (QoR) of FPGA synthesis operations is measured by two major criteria; area on chip, and circuit delay. In this paper we address the problem of minimizing the area and delay by filtering the input HDL descriptions to modify the constructs that are harmful to those criteria. A prototype tool was developed to make this filtering automatically, and the obtained results show the efficiency of this approach.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129349239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374549
A. Ibrahim, M. Khairy
In this paper, we propose a combination of the vertical layered Space-Time architecture (V-BLAST) and the Space-Time Block Codes (STBC) producing VBLAST-STBC, which shows a performance advantage over V-BLAST in frat fading channels. We also propose VBLAST-STBC with Orthogonal Frequency Division Multiplexing (OFDM) producing VBLAST-STBCOFDM, which shows a pevformance advantage over VBLAST-OFDM in frequency selective fading channels. These two schemes provide reliable as well as very high data rate communications over Rayleigh fading channels. The simulations show the advantages of the proposed schemes over the original V-BLAST and VBLAST-OFDM schemes.
{"title":"Multilayered space-time block codes for OFDM systems","authors":"A. Ibrahim, M. Khairy","doi":"10.1109/ICEEC.2004.1374549","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374549","url":null,"abstract":"In this paper, we propose a combination of the vertical layered Space-Time architecture (V-BLAST) and the Space-Time Block Codes (STBC) producing VBLAST-STBC, which shows a performance advantage over V-BLAST in frat fading channels. We also propose VBLAST-STBC with Orthogonal Frequency Division Multiplexing (OFDM) producing VBLAST-STBCOFDM, which shows a pevformance advantage over VBLAST-OFDM in frequency selective fading channels. These two schemes provide reliable as well as very high data rate communications over Rayleigh fading channels. The simulations show the advantages of the proposed schemes over the original V-BLAST and VBLAST-OFDM schemes.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123546361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374423
M. H. El-Shafey
Estimating the frequencies of a number of sinusoids in a signal is considered. It is shown that by passing the signal x(t) through a continuous-time filter f(s) to obtain the filtered signal xit), we can obtain the required frequencies fi-om the eigenvalues of the matrix product my', where X and X, are formed from samples of x and x) respectivel., The result of this paper is a generalization of previous work by the author where xf was the derivative (or integration) of x, i.e. the filter was a differentiator (or integrator). There are two positive points for using a continuous filter instead of a differentiator/integrator: 1relaxing the practical concerns of designing the differentiator/integrator, and 2having some freedom in designing the filter so that attenuation of the noise in the signal is possible especially if the noise spectrum is outside the band of frequencies of interest.
{"title":"Beating the nyquist limit by utilizing samples of filtered sinisoids","authors":"M. H. El-Shafey","doi":"10.1109/ICEEC.2004.1374423","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374423","url":null,"abstract":"Estimating the frequencies of a number of sinusoids in a signal is considered. It is shown that by passing the signal x(t) through a continuous-time filter f(s) to obtain the filtered signal xit), we can obtain the required frequencies fi-om the eigenvalues of the matrix product my', where X and X, are formed from samples of x and x) respectivel., The result of this paper is a generalization of previous work by the author where xf was the derivative (or integration) of x, i.e. the filter was a differentiator (or integrator). There are two positive points for using a continuous filter instead of a differentiator/integrator: 1relaxing the practical concerns of designing the differentiator/integrator, and 2having some freedom in designing the filter so that attenuation of the noise in the signal is possible especially if the noise spectrum is outside the band of frequencies of interest.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124719591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374394
Bahnasy M. Nossier
The purpose of this paper is to compare and analyze the diyerent congestion control and avoidance mechanism which have been proposed for TCP protocol for diyerent network operating systems, namely: Tahoe, Reno, and SACK with diferent Unix and Windows based operating systems. Also, in this paper the previous mechanism shall implemented with Jacobson’s, Kern’s, and Nagle ’s algorithm for jlow control and round trip time calculation. Congestion window for TCP implementation in Unix Solaris, HP-UX and dyerent Microsoft Windows implementation will be investigated.
{"title":"Performance evaluation of TCP congestion control for different network operating systems","authors":"Bahnasy M. Nossier","doi":"10.1109/ICEEC.2004.1374394","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374394","url":null,"abstract":"The purpose of this paper is to compare and analyze the diyerent congestion control and avoidance mechanism which have been proposed for TCP protocol for diyerent network operating systems, namely: Tahoe, Reno, and SACK with diferent Unix and Windows based operating systems. Also, in this paper the previous mechanism shall implemented with Jacobson’s, Kern’s, and Nagle ’s algorithm for jlow control and round trip time calculation. Congestion window for TCP implementation in Unix Solaris, HP-UX and dyerent Microsoft Windows implementation will be investigated.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130023842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374616
H. Khattab, S. Mekhamer, A. Mahmoud
This paper proposes a new approach using a newly heuristic technique for optimal capacitor placement on radial distribution feeders. This technique is modified to allow for the use of fixed capacitor thyristor controlled reactor (FCTCR) for loss reduction and voltage profile improvement for radial distribution feeders. The paper concentrates on the contribution and use of static var compensator (SVC) for the minimization of distribution feeder's losses, rather than using fixed or switched capacitors alone. The SVC can respond continuously to the load variation ensuring a maximum reduction of active losses at all load levels. The proposed method has been tested for two radial distribution feeders available in the literature with superior results. The effect of load variation is also studied and results show that the method leads to reducing losses during different load levels.
{"title":"Thyristor controlled reactors for reactive power compensation in radial distribution feeders: a developed approach","authors":"H. Khattab, S. Mekhamer, A. Mahmoud","doi":"10.1109/ICEEC.2004.1374616","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374616","url":null,"abstract":"This paper proposes a new approach using a newly heuristic technique for optimal capacitor placement on radial distribution feeders. This technique is modified to allow for the use of fixed capacitor thyristor controlled reactor (FCTCR) for loss reduction and voltage profile improvement for radial distribution feeders. The paper concentrates on the contribution and use of static var compensator (SVC) for the minimization of distribution feeder's losses, rather than using fixed or switched capacitors alone. The SVC can respond continuously to the load variation ensuring a maximum reduction of active losses at all load levels. The proposed method has been tested for two radial distribution feeders available in the literature with superior results. The effect of load variation is also studied and results show that the method leads to reducing losses during different load levels.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127851993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374438
T. Hindam
One of the simple distributed ways to coordinate the arrival or release between groups of threads that participate to the same global events is through a logical-tree of hardware agents. This organization transfers the processing responsibility of the intercluster barrier synchronization from the distributed groups of threads to the participating hardware agents. For interconnected multiprocessor clusters that support distributed memorized embedded boards (DMEB), we have developed the software platform to logically connect the hardware agents as nodes in a logical-tree. We restrict our contribution in this paper to the global-barrier synchronization. Index terms barrier operation, communication pattern, and memorized embedded board.
{"title":"Connecting the distributed hardware agents for barrier synchronization operation","authors":"T. Hindam","doi":"10.1109/ICEEC.2004.1374438","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374438","url":null,"abstract":"One of the simple distributed ways to coordinate the arrival or release between groups of threads that participate to the same global events is through a logical-tree of hardware agents. This organization transfers the processing responsibility of the intercluster barrier synchronization from the distributed groups of threads to the participating hardware agents. For interconnected multiprocessor clusters that support distributed memorized embedded boards (DMEB), we have developed the software platform to logically connect the hardware agents as nodes in a logical-tree. We restrict our contribution in this paper to the global-barrier synchronization. Index terms barrier operation, communication pattern, and memorized embedded board.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117076910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374582
S. F. Mekharner, Y.G. Moustafa, Nehad El-Sherif, M. M. Mansour
In this paper, a modified approach, based on the particle swarm optimizer (PSO) is presented and explained in detail. As a case study, this PSO technique is applied to the solution of the economic dispatch (ED) problem of thermal generating units. A piecewise quadratic function is used to represent the fuel cost of each generating unit. The B-coefficient method is used to model the transmission losses. A modification to the standard PSO algorithm is proposed to allow dealing with the power balance equality constraint. Unlike the traditional methods, this modification does not depend on penalizing the infeasible solutions using a pre-defined penalty function. The application of the proposed method to several case studies shows that it is applicable to large networks with multigenerating units including transmission losses with very promising results.
{"title":"A modified particle swarm optimizer applied to the solution of the economic dispatch problem","authors":"S. F. Mekharner, Y.G. Moustafa, Nehad El-Sherif, M. M. Mansour","doi":"10.1109/ICEEC.2004.1374582","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374582","url":null,"abstract":"In this paper, a modified approach, based on the particle swarm optimizer (PSO) is presented and explained in detail. As a case study, this PSO technique is applied to the solution of the economic dispatch (ED) problem of thermal generating units. A piecewise quadratic function is used to represent the fuel cost of each generating unit. The B-coefficient method is used to model the transmission losses. A modification to the standard PSO algorithm is proposed to allow dealing with the power balance equality constraint. Unlike the traditional methods, this modification does not depend on penalizing the infeasible solutions using a pre-defined penalty function. The application of the proposed method to several case studies shows that it is applicable to large networks with multigenerating units including transmission losses with very promising results.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121427878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374532
D. Masmoudi, S. Ben Salem, M. Loulou, L. Kamoun
In this paper we present a design of a current controlled oscillator in 0.35pm CMOS process. Owing to their high degree of controllability, the translinear second generation current conveyer is used as a basic block for our oscillator. Thus, the first step in our design was to improve static and dynamic behaviour of second generation current conveyors. The translinear implementation in CMOS technology was first studied. Then a considerable improvement of the parasitic series resistance on port X is done by proposing a new structure. A reduction of RX by nearly a factor of 10 is observed leading to a notable improvement of the frequency behaviour of the proposed oscillator. As an application example, a current controlled oscillator covering [IOOMHz600MHzI frequency range is proposed. Pspice simulation results are performed using CMOS 0.35 pm process of AMs.
{"title":"A radio frequency CMOS current controlled oscillator based on a new low parasitic resistance CCII","authors":"D. Masmoudi, S. Ben Salem, M. Loulou, L. Kamoun","doi":"10.1109/ICEEC.2004.1374532","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374532","url":null,"abstract":"In this paper we present a design of a current controlled oscillator in 0.35pm CMOS process. Owing to their high degree of controllability, the translinear second generation current conveyer is used as a basic block for our oscillator. Thus, the first step in our design was to improve static and dynamic behaviour of second generation current conveyors. The translinear implementation in CMOS technology was first studied. Then a considerable improvement of the parasitic series resistance on port X is done by proposing a new structure. A reduction of RX by nearly a factor of 10 is observed leading to a notable improvement of the frequency behaviour of the proposed oscillator. As an application example, a current controlled oscillator covering [IOOMHz600MHzI frequency range is proposed. Pspice simulation results are performed using CMOS 0.35 pm process of AMs.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122406428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374584
A.A. Hassan, M. Azzam
This paper presents a robust state feedback controller for the linear brushless dc motor. The controller gains are calculated via solving the inverse dynamical system equations at all loads numerically. It has been found that the controller feedback gains for all the states are nonlinear functions of the load. Therefore, a neural network controller has been designed to provide the necessary gains at all loads. Computer simulations have been carried out in order to validate the effectiveness of the proposed scheme. The results show that accurate tracking performance of the linear brushless dc motor has been achieved. Moreover, the rise and settling times of the position response have been reduced significantly at all loads.
{"title":"Robust position control for a field oriented linear brushless dc motor","authors":"A.A. Hassan, M. Azzam","doi":"10.1109/ICEEC.2004.1374584","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374584","url":null,"abstract":"This paper presents a robust state feedback controller for the linear brushless dc motor. The controller gains are calculated via solving the inverse dynamical system equations at all loads numerically. It has been found that the controller feedback gains for all the states are nonlinear functions of the load. Therefore, a neural network controller has been designed to provide the necessary gains at all loads. Computer simulations have been carried out in order to validate the effectiveness of the proposed scheme. The results show that accurate tracking performance of the linear brushless dc motor has been achieved. Moreover, the rise and settling times of the position response have been reduced significantly at all loads.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131934562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374455
F. A. Elmisery, A. Khalil, A. Salama, F. Algeldawy
Speaker identification is a challenging pattern classification task. It is used enormously in many applications such as security systems, information retrieved services, etc. portable identification systems are expected to be widely used in future in many purposes, such as mobile applications. Implementing the identification technique using a dedicated hardware could be very useful to achieve smart units. In this context, the FPGA could offer an efficient technology to realize a pattern classification strategy. A speaker identification system can be implemented using many classification approaches, one of these , the artificial neural network (ANN), which is considered one of the most powerful classification techniques. Implementing a Neural Network on. an FPGA is a challenging task because of the complexity of the required arithmetic operations. In this paper the nonlinear activation function is adapted to be more suitable for the FPGA implementation. We have reached almost 100% identification rate using Multi Layer Perceptron Neural Network ( MLP NN).
{"title":"Adaptation of ann for FPGA implementation and its application for speaker identification","authors":"F. A. Elmisery, A. Khalil, A. Salama, F. Algeldawy","doi":"10.1109/ICEEC.2004.1374455","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374455","url":null,"abstract":"Speaker identification is a challenging pattern classification task. It is used enormously in many applications such as security systems, information retrieved services, etc. portable identification systems are expected to be widely used in future in many purposes, such as mobile applications. Implementing the identification technique using a dedicated hardware could be very useful to achieve smart units. In this context, the FPGA could offer an efficient technology to realize a pattern classification strategy. A speaker identification system can be implemented using many classification approaches, one of these , the artificial neural network (ANN), which is considered one of the most powerful classification techniques. Implementing a Neural Network on. an FPGA is a challenging task because of the complexity of the required arithmetic operations. In this paper the nonlinear activation function is adapted to be more suitable for the FPGA implementation. We have reached almost 100% identification rate using Multi Layer Perceptron Neural Network ( MLP NN).","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130823935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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