Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374480
M. Sayed, T. Mohamed, Wael Badawy
This paper presents part of University of Calgary contribution in developing BO/IEC JTCl/SC29/WG Il/N5370 as part of the MPEG-4 Part 9: Reference Hardware Description. The main objective of that project is to design a System-on-Chip platform for MPEG-4 applications. The designed modules will be implemented on Annapolis Wildcard II. New motion estimation architecture is presented in this paper. This module replaces the motion estimation software module in the MPEG-4 encoder to assist the MPEG-4 software to achieve the required real-time constrains. The proposed architecture processes one CIF video pame in 8.712 ms using 93 MHz clock frequency. Therefore, it can process up to 114 CIF video frames per second. Index Terms Hardwarehoftware integration, Multimedia, MPEG-4. Motion Estimation.
{"title":"Motion estimation architecture for mpeg-4 part 9: reference hardware description","authors":"M. Sayed, T. Mohamed, Wael Badawy","doi":"10.1109/ICEEC.2004.1374480","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374480","url":null,"abstract":"This paper presents part of University of Calgary contribution in developing BO/IEC JTCl/SC29/WG Il/N5370 as part of the MPEG-4 Part 9: Reference Hardware Description. The main objective of that project is to design a System-on-Chip platform for MPEG-4 applications. The designed modules will be implemented on Annapolis Wildcard II. New motion estimation architecture is presented in this paper. This module replaces the motion estimation software module in the MPEG-4 encoder to assist the MPEG-4 software to achieve the required real-time constrains. The proposed architecture processes one CIF video pame in 8.712 ms using 93 MHz clock frequency. Therefore, it can process up to 114 CIF video frames per second. Index Terms Hardwarehoftware integration, Multimedia, MPEG-4. Motion Estimation.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"417 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115926272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374595
S. E. El Safty, H. El Dessoiki, K. Shebl, E.S. Gaber
The objective of this paper is to present an approach for isolating the harmonic contents in both voltage and current waveforms at the outage feeder of Gharb Talkha substation (66/11 kv). A novel technique using Discrete Wavelet transform (DWT) for the analysis of the waveforms harmonics content. At the beginning the substation is simulated using Sirnulink toolbox in Matlab program with and without the presence of capacitor bank The obtained voltage and current waveforms are compared to the actual data. The proposed model is used to study the effect of replacing the capacitor bank with single tuned parallel passive fiter. The resulting current and voltage waveforms are analyzed using the proposed DWT technique. The analysis showed that the Total Harmonic Distortion (THD) of both voltage and current waveforms is improved as well as the power factor.
{"title":"Harmonic elimination of gharb talkha substation using discrete wavelet transform","authors":"S. E. El Safty, H. El Dessoiki, K. Shebl, E.S. Gaber","doi":"10.1109/ICEEC.2004.1374595","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374595","url":null,"abstract":"The objective of this paper is to present an approach for isolating the harmonic contents in both voltage and current waveforms at the outage feeder of Gharb Talkha substation (66/11 kv). A novel technique using Discrete Wavelet transform (DWT) for the analysis of the waveforms harmonics content. At the beginning the substation is simulated using Sirnulink toolbox in Matlab program with and without the presence of capacitor bank The obtained voltage and current waveforms are compared to the actual data. The proposed model is used to study the effect of replacing the capacitor bank with single tuned parallel passive fiter. The resulting current and voltage waveforms are analyzed using the proposed DWT technique. The analysis showed that the Total Harmonic Distortion (THD) of both voltage and current waveforms is improved as well as the power factor.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124208559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374401
A. Alfantookh
In this paper, the problem of SQL Injection attacks to web-based applications is discussed and described. The previous work on this problem is presented and the main problem of using manual solutions is highlighted. An automated universal server level solution calIed AUSELSQI is proposed and illustrated. The solution is shown to be universal for any Ype of web server and is applied automatically to all existing and future web applications residing on a web server. Experiments conducted show that the overhead of applying this solution is negligible. Comparison with other techniques is also presented.
{"title":"An automated universal server level solution for SQL injection security flaw","authors":"A. Alfantookh","doi":"10.1109/ICEEC.2004.1374401","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374401","url":null,"abstract":"In this paper, the problem of SQL Injection attacks to web-based applications is discussed and described. The previous work on this problem is presented and the main problem of using manual solutions is highlighted. An automated universal server level solution calIed AUSELSQI is proposed and illustrated. The solution is shown to be universal for any Ype of web server and is applied automatically to all existing and future web applications residing on a web server. Experiments conducted show that the overhead of applying this solution is negligible. Comparison with other techniques is also presented.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128577769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374592
H. A. Darwish, M. Izzularab, N. Elkalashy
A new real-time testing technique for hvdc breakers using the Electromagnetic Transient Program (EMTP) has been proposed. In this paper, different topologies of hvdc systems with full-size controlled converters are accurately modeled and the hvdc circuit breakers are appropriately located. Then, miscellaneous switching duties are examined. Metallic Return Protecting Breaker (MRPB) and fault clearing processes are fully analyzed for the first time. The test results validate the efficacy of the proposed real-time testing procedure.
{"title":"Real-time testing of hvdc circuit breakers part II: real-time cases","authors":"H. A. Darwish, M. Izzularab, N. Elkalashy","doi":"10.1109/ICEEC.2004.1374592","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374592","url":null,"abstract":"A new real-time testing technique for hvdc breakers using the Electromagnetic Transient Program (EMTP) has been proposed. In this paper, different topologies of hvdc systems with full-size controlled converters are accurately modeled and the hvdc circuit breakers are appropriately located. Then, miscellaneous switching duties are examined. Metallic Return Protecting Breaker (MRPB) and fault clearing processes are fully analyzed for the first time. The test results validate the efficacy of the proposed real-time testing procedure.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130122585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374638
N. Rahim, Z. Islam
Abstract This paper presents a new control approach for harmonic control and its practical implementation for a single-phase hybrid active power filter. It is a combined system of shunt passive filter and small rated series active filter. For the control of the active power filter a simple digital controller is used. This simplification is made by without calculating the load current for opposite harmonic component injection to the system. For active power filter control a sinusoidal pulse width modulation is developed and the modulation index is selected by calculating the DC bus voltage of the active filter through a digital controller based on Proportional-Integral-Derivative principle. Prototype hardware is developed and tested. Simulation and experimental results show that the proposed active power filter topology is capable of compensating the load current and voltage harmonic specijied by IEEE.
{"title":"A single-phase series active power filter design","authors":"N. Rahim, Z. Islam","doi":"10.1109/ICEEC.2004.1374638","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374638","url":null,"abstract":"Abstract This paper presents a new control approach for harmonic control and its practical implementation for a single-phase hybrid active power filter. It is a combined system of shunt passive filter and small rated series active filter. For the control of the active power filter a simple digital controller is used. This simplification is made by without calculating the load current for opposite harmonic component injection to the system. For active power filter control a sinusoidal pulse width modulation is developed and the modulation index is selected by calculating the DC bus voltage of the active filter through a digital controller based on Proportional-Integral-Derivative principle. Prototype hardware is developed and tested. Simulation and experimental results show that the proposed active power filter topology is capable of compensating the load current and voltage harmonic specijied by IEEE.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132474507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374430
A.M.B. Albassal, A. Wahdan
In this paper a new attack for block cipher based on the ability of neural networks to pe$orm an approximation of mapping is proposed. Feistel block cipher is explained and a brief about modern attacks is given. A complete problem formulation is explained and implementation of the attack on some hypothetical Feistel cipher is presented. Results and comments are given as appropriate.
{"title":"Neural network based cryptanalysis of a feistel type block cipher","authors":"A.M.B. Albassal, A. Wahdan","doi":"10.1109/ICEEC.2004.1374430","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374430","url":null,"abstract":"In this paper a new attack for block cipher based on the ability of neural networks to pe$orm an approximation of mapping is proposed. Feistel block cipher is explained and a brief about modern attacks is given. A complete problem formulation is explained and implementation of the attack on some hypothetical Feistel cipher is presented. Results and comments are given as appropriate.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131011586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374585
A. El-Dib, H. Youssef, M. El-Metwally, Z. Osman
Load flow (LF) is an important tool in the planning and operation of power systems. It is usually solved using conventional numerical techniques like Newton-Raphson (NR) or GaussSeidel (GS) methods. This paper presents an application of particle swarm optimization (PSO) in solving the load flow problem as an optimization problem. Examples on test systems are given to demonstrate the validity and applicability of the proposed method.
{"title":"Load flow solution using hybrid particle swarm optimization","authors":"A. El-Dib, H. Youssef, M. El-Metwally, Z. Osman","doi":"10.1109/ICEEC.2004.1374585","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374585","url":null,"abstract":"Load flow (LF) is an important tool in the planning and operation of power systems. It is usually solved using conventional numerical techniques like Newton-Raphson (NR) or GaussSeidel (GS) methods. This paper presents an application of particle swarm optimization (PSO) in solving the load flow problem as an optimization problem. Examples on test systems are given to demonstrate the validity and applicability of the proposed method.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125588668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374569
M. Fakhfakh, M. Loulou, N. Masmoudi
V C C I Abstract -In this paper, a design automation procedure is presented. It is an algorithm driven methodology which is capable of designing and optimizing SI circuits. we applied the proposed methodology to design optimal S21 class AB grounded gate memory cells. Owing to this procedure, this cell designed using the CMOS 0.35pm process under a single 3.3Vpower supply voltage, achieves 80 dB as dynamic range at 16 MHz sampling frequency. Besides it reaches less than 0.5 ns as settling time when priori@ is given to design high speed cells.
{"title":"An improved algorithm-driven methodology to optimize switched current memory cells by transistor sizing","authors":"M. Fakhfakh, M. Loulou, N. Masmoudi","doi":"10.1109/ICEEC.2004.1374569","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374569","url":null,"abstract":"V C C I Abstract -In this paper, a design automation procedure is presented. It is an algorithm driven methodology which is capable of designing and optimizing SI circuits. we applied the proposed methodology to design optimal S21 class AB grounded gate memory cells. Owing to this procedure, this cell designed using the CMOS 0.35pm process under a single 3.3Vpower supply voltage, achieves 80 dB as dynamic range at 16 MHz sampling frequency. Besides it reaches less than 0.5 ns as settling time when priori@ is given to design high speed cells.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122235004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374637
A. El-Zonkoly
This paper presents a new simulation method for pei$onning equipment sensitivity study during power quality events. Power quality wavefonn events such as voltage sags, swells, transients, etc. may cause sensitive loads to trip or mis-operate. For better coordination between the system and the equipment, it is necessary that the effects of specific events on the equipment behavior be thoroughly evaluated. This paper serves such a purpose. A library has been designed for generating various types of event waveforms. By imposing these Waveforms on the equipment and tuning various waveform features, the equipment behavior can be correlated to specijk event parameters. Methods and case studies as well as sof iare implementation issues in MA TLAB environment are illustrated.
{"title":"Design of waveform generator for equipment sensitivity study during power quality events","authors":"A. El-Zonkoly","doi":"10.1109/ICEEC.2004.1374637","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374637","url":null,"abstract":"This paper presents a new simulation method for pei$onning equipment sensitivity study during power quality events. Power quality wavefonn events such as voltage sags, swells, transients, etc. may cause sensitive loads to trip or mis-operate. For better coordination between the system and the equipment, it is necessary that the effects of specific events on the equipment behavior be thoroughly evaluated. This paper serves such a purpose. A library has been designed for generating various types of event waveforms. By imposing these Waveforms on the equipment and tuning various waveform features, the equipment behavior can be correlated to specijk event parameters. Methods and case studies as well as sof iare implementation issues in MA TLAB environment are illustrated.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121070377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-05DOI: 10.1109/ICEEC.2004.1374397
M. Bhattacharyya, A. Kumar, M. Bayoumi
Minimizing energy consumption is important for prolonging the life of battery powered sensor nodes. A major portion of the power consumption is spent in communication with other nodes. In this paper we discuss a new energy saving routing algorithm, which uses cache based routing and also incorporates interferenceJailed communication and levels of security.
{"title":"Communication protocol with interference awareness for sensor networks with security enhancemments","authors":"M. Bhattacharyya, A. Kumar, M. Bayoumi","doi":"10.1109/ICEEC.2004.1374397","DOIUrl":"https://doi.org/10.1109/ICEEC.2004.1374397","url":null,"abstract":"Minimizing energy consumption is important for prolonging the life of battery powered sensor nodes. A major portion of the power consumption is spent in communication with other nodes. In this paper we discuss a new energy saving routing algorithm, which uses cache based routing and also incorporates interferenceJailed communication and levels of security.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121136380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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