{"title":"Session details: Session 7: Machine Learning for Physical Design (2/2)","authors":"S. Nath","doi":"10.1145/3457131","DOIUrl":"https://doi.org/10.1145/3457131","url":null,"abstract":"","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123585420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Session details: Session 4: Driving Research in Placement: a Retrospective","authors":"Igor Markov","doi":"10.1145/3457129","DOIUrl":"https://doi.org/10.1145/3457129","url":null,"abstract":"","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"402 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123523911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Placement is central to IC physical design: it determines spatial embedding, and hence parasitics and performance. From coarse-to fine-grain, placement is conjointly optimized with logic, performance, clock and power distribution, routability and manufacturability. This paper gives some personal thoughts on futures for placement research in IC physical design. Revisiting placement as optimization prompts a new look at placement requirements, optimization quality, and scalability with resources. Placement must also evolve to meet a growing need for co-optimizations and for co-operation with other design steps. "New" challenges will naturally arise from scaling, both at the end of the 2D scaling roadmap and in the context of future 2.5D/3D/4D integrations. And, the nexus of machine learning and placement optimization will continue to be an area of intense focus for research and practice. In general, placement research is likely to see more flow-scale optimization contexts, open source, benchmarking of progress toward optimality, and attention to translations into real-world practice.
{"title":"Advancing Placement","authors":"A. Kahng","doi":"10.1145/3439706.3446884","DOIUrl":"https://doi.org/10.1145/3439706.3446884","url":null,"abstract":"Placement is central to IC physical design: it determines spatial embedding, and hence parasitics and performance. From coarse-to fine-grain, placement is conjointly optimized with logic, performance, clock and power distribution, routability and manufacturability. This paper gives some personal thoughts on futures for placement research in IC physical design. Revisiting placement as optimization prompts a new look at placement requirements, optimization quality, and scalability with resources. Placement must also evolve to meet a growing need for co-optimizations and for co-operation with other design steps. \"New\" challenges will naturally arise from scaling, both at the end of the 2D scaling roadmap and in the context of future 2.5D/3D/4D integrations. And, the nexus of machine learning and placement optimization will continue to be an area of intense focus for research and practice. In general, placement research is likely to see more flow-scale optimization contexts, open source, benchmarking of progress toward optimality, and attention to translations into real-world practice.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"288 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123043877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Session details: Session 11: Third Keynote","authors":"I. Jiang","doi":"10.1145/3457134","DOIUrl":"https://doi.org/10.1145/3457134","url":null,"abstract":"","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"46 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116447613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Chen, Chi-Chun Fang, Wai-Kei Mak, Ting-Chi Wang
Conventional lithography techniques are unable to achieve the resolution required by advance technology nodes. Multiple patterning lithography (MPL) has been introduced as a viable solution. Besides, new standard cell structure with multiple middle-of-line (MOL) layers is adopted to improve intra-cell routability. A mixed-cell-height standard cell library, consisting of cells of single-row and multiple-row heights, is also used in designs for power, performance and area concerns. As a result, it becomes increasingly difficult to get a feasible placement for a mixed-cell-height design where multiple cell layers require MPL. In this paper, we present a methodology to refine a given mixed-cell-height standard cell placement for satisfying MPL requirements on multiple cell layers as much as possible, while minimizing the total cell displacement. We introduce the concept of uncolored cell group (UCG) to facilitate the effective removal of coloring conflicts. By eliminating UCGs without generating any new coloring conflict around them, the number of UCGs is effectively reduced in the local and global refinement stages of our methodology. We report promising experimental results to demonstrate the efficacy of our methodology.
{"title":"Multiple-Layer Multiple-Patterning Aware Placement Refinement for Mixed-Cell-Height Designs","authors":"B. Chen, Chi-Chun Fang, Wai-Kei Mak, Ting-Chi Wang","doi":"10.1145/3439706.3447048","DOIUrl":"https://doi.org/10.1145/3439706.3447048","url":null,"abstract":"Conventional lithography techniques are unable to achieve the resolution required by advance technology nodes. Multiple patterning lithography (MPL) has been introduced as a viable solution. Besides, new standard cell structure with multiple middle-of-line (MOL) layers is adopted to improve intra-cell routability. A mixed-cell-height standard cell library, consisting of cells of single-row and multiple-row heights, is also used in designs for power, performance and area concerns. As a result, it becomes increasingly difficult to get a feasible placement for a mixed-cell-height design where multiple cell layers require MPL. In this paper, we present a methodology to refine a given mixed-cell-height standard cell placement for satisfying MPL requirements on multiple cell layers as much as possible, while minimizing the total cell displacement. We introduce the concept of uncolored cell group (UCG) to facilitate the effective removal of coloring conflicts. By eliminating UCGs without generating any new coloring conflict around them, the number of UCGs is effectively reduced in the local and global refinement stages of our methodology. We report promising experimental results to demonstrate the efficacy of our methodology.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132847939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ismail Bustany, Jinwook Jung, P. Madden, Natarajan Viswanathan, Stephen Yang
Circuit benchmarks for VLSI physical design have been growing in size and complexity, helping the industry tackle new problems and find new approaches. In this paper, we take a look back at how benchmarking efforts have shaped the research community, consider trade-offs that have been made, and speculate on what may come next.
{"title":"Still Benchmarking After All These Years","authors":"Ismail Bustany, Jinwook Jung, P. Madden, Natarajan Viswanathan, Stephen Yang","doi":"10.1145/3439706.3446885","DOIUrl":"https://doi.org/10.1145/3439706.3446885","url":null,"abstract":"Circuit benchmarks for VLSI physical design have been growing in size and complexity, helping the industry tackle new problems and find new approaches. In this paper, we take a look back at how benchmarking efforts have shaped the research community, consider trade-offs that have been made, and speculate on what may come next.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128163403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Session details: Session 6: Second Keynote","authors":"Ismail Bustany","doi":"10.1145/3457130","DOIUrl":"https://doi.org/10.1145/3457130","url":null,"abstract":"","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125026633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Reinforcement learning is a machine learning technique that has been applied in many domains, including robotics, game playing, and finance. This talk will briefly introduce reinforcement learning with two use cases related to compiler optimization and chip design. Interested participants will also have materials suggested to learn a more at a technical or non-technical level about this exciting tool.
{"title":"Reinforcement Learning for Electronic Design Automation: Successes and Opportunities","authors":"Matthew E. Taylor","doi":"10.1145/3439706.3446882","DOIUrl":"https://doi.org/10.1145/3439706.3446882","url":null,"abstract":"Reinforcement learning is a machine learning technique that has been applied in many domains, including robotics, game playing, and finance. This talk will briefly introduce reinforcement learning with two use cases related to compiler optimization and chip design. Interested participants will also have materials suggested to learn a more at a technical or non-technical level about this exciting tool.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130872862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Session details: Session 12: Physical Design at Advanced Technology Nodes","authors":"Magna Mankalale","doi":"10.1145/3457135","DOIUrl":"https://doi.org/10.1145/3457135","url":null,"abstract":"","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124681449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bentian Jiang, Xiaopeng Zhang, Lixin Liu, Evangeline F. Y. Young
With the continuous shrinkage of device technology node, the tremendously increasing demands for resolution enhancement technologies (RETs) have created severe concerns over the balance between computational affordability and model accuracy. Having realized the analogies between computational lithography tasks and deep learning-based computer vision applications (e.g., medical image analysis), both industry and academia start gradually migrating various RETs to deep learning-enabled platforms. In this paper, we propose a unified self-training paradigm for building up an end-to-end mask optimization framework from undisclosable layout patterns. Our proposed flow comprises (1) a learning-based pattern generation stage to massively synthesize diverse and realistic layout patterns following the distribution of the undisclosable target layouts, while keeping these confidential layouts blind for any successive training stage, and (2) a complete self-training stage for building up an end-to-end on-neural-network mask optimization framework from scratch, which only requires the aforementioned generated patterns and a compact lithography simulation model as the inputs. Quantitative results demonstrate that our proposed flow achieves comparable state-of-the-art (SOTA) performance in terms of both mask printability and mask correction time while reducing 66% of the turn around time for flow construction.
{"title":"Building up End-to-end Mask Optimization Framework with Self-training","authors":"Bentian Jiang, Xiaopeng Zhang, Lixin Liu, Evangeline F. Y. Young","doi":"10.1145/3439706.3447050","DOIUrl":"https://doi.org/10.1145/3439706.3447050","url":null,"abstract":"With the continuous shrinkage of device technology node, the tremendously increasing demands for resolution enhancement technologies (RETs) have created severe concerns over the balance between computational affordability and model accuracy. Having realized the analogies between computational lithography tasks and deep learning-based computer vision applications (e.g., medical image analysis), both industry and academia start gradually migrating various RETs to deep learning-enabled platforms. In this paper, we propose a unified self-training paradigm for building up an end-to-end mask optimization framework from undisclosable layout patterns. Our proposed flow comprises (1) a learning-based pattern generation stage to massively synthesize diverse and realistic layout patterns following the distribution of the undisclosable target layouts, while keeping these confidential layouts blind for any successive training stage, and (2) a complete self-training stage for building up an end-to-end on-neural-network mask optimization framework from scratch, which only requires the aforementioned generated patterns and a compact lithography simulation model as the inputs. Quantitative results demonstrate that our proposed flow achieves comparable state-of-the-art (SOTA) performance in terms of both mask printability and mask correction time while reducing 66% of the turn around time for flow construction.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127958742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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