{"title":"Session details: Session 11: Third Keynote","authors":"I. Jiang","doi":"10.1145/3457134","DOIUrl":"https://doi.org/10.1145/3457134","url":null,"abstract":"","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"46 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116447613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Session details: Session 4: Driving Research in Placement: a Retrospective","authors":"Igor Markov","doi":"10.1145/3457129","DOIUrl":"https://doi.org/10.1145/3457129","url":null,"abstract":"","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"402 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123523911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Session details: Session 7: Machine Learning for Physical Design (2/2)","authors":"S. Nath","doi":"10.1145/3457131","DOIUrl":"https://doi.org/10.1145/3457131","url":null,"abstract":"","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123585420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ismail Bustany, Jinwook Jung, P. Madden, Natarajan Viswanathan, Stephen Yang
Circuit benchmarks for VLSI physical design have been growing in size and complexity, helping the industry tackle new problems and find new approaches. In this paper, we take a look back at how benchmarking efforts have shaped the research community, consider trade-offs that have been made, and speculate on what may come next.
{"title":"Still Benchmarking After All These Years","authors":"Ismail Bustany, Jinwook Jung, P. Madden, Natarajan Viswanathan, Stephen Yang","doi":"10.1145/3439706.3446885","DOIUrl":"https://doi.org/10.1145/3439706.3446885","url":null,"abstract":"Circuit benchmarks for VLSI physical design have been growing in size and complexity, helping the industry tackle new problems and find new approaches. In this paper, we take a look back at how benchmarking efforts have shaped the research community, consider trade-offs that have been made, and speculate on what may come next.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128163403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Placement is central to IC physical design: it determines spatial embedding, and hence parasitics and performance. From coarse-to fine-grain, placement is conjointly optimized with logic, performance, clock and power distribution, routability and manufacturability. This paper gives some personal thoughts on futures for placement research in IC physical design. Revisiting placement as optimization prompts a new look at placement requirements, optimization quality, and scalability with resources. Placement must also evolve to meet a growing need for co-optimizations and for co-operation with other design steps. "New" challenges will naturally arise from scaling, both at the end of the 2D scaling roadmap and in the context of future 2.5D/3D/4D integrations. And, the nexus of machine learning and placement optimization will continue to be an area of intense focus for research and practice. In general, placement research is likely to see more flow-scale optimization contexts, open source, benchmarking of progress toward optimality, and attention to translations into real-world practice.
{"title":"Advancing Placement","authors":"A. Kahng","doi":"10.1145/3439706.3446884","DOIUrl":"https://doi.org/10.1145/3439706.3446884","url":null,"abstract":"Placement is central to IC physical design: it determines spatial embedding, and hence parasitics and performance. From coarse-to fine-grain, placement is conjointly optimized with logic, performance, clock and power distribution, routability and manufacturability. This paper gives some personal thoughts on futures for placement research in IC physical design. Revisiting placement as optimization prompts a new look at placement requirements, optimization quality, and scalability with resources. Placement must also evolve to meet a growing need for co-optimizations and for co-operation with other design steps. \"New\" challenges will naturally arise from scaling, both at the end of the 2D scaling roadmap and in the context of future 2.5D/3D/4D integrations. And, the nexus of machine learning and placement optimization will continue to be an area of intense focus for research and practice. In general, placement research is likely to see more flow-scale optimization contexts, open source, benchmarking of progress toward optimality, and attention to translations into real-world practice.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"288 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123043877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Chen, Chi-Chun Fang, Wai-Kei Mak, Ting-Chi Wang
Conventional lithography techniques are unable to achieve the resolution required by advance technology nodes. Multiple patterning lithography (MPL) has been introduced as a viable solution. Besides, new standard cell structure with multiple middle-of-line (MOL) layers is adopted to improve intra-cell routability. A mixed-cell-height standard cell library, consisting of cells of single-row and multiple-row heights, is also used in designs for power, performance and area concerns. As a result, it becomes increasingly difficult to get a feasible placement for a mixed-cell-height design where multiple cell layers require MPL. In this paper, we present a methodology to refine a given mixed-cell-height standard cell placement for satisfying MPL requirements on multiple cell layers as much as possible, while minimizing the total cell displacement. We introduce the concept of uncolored cell group (UCG) to facilitate the effective removal of coloring conflicts. By eliminating UCGs without generating any new coloring conflict around them, the number of UCGs is effectively reduced in the local and global refinement stages of our methodology. We report promising experimental results to demonstrate the efficacy of our methodology.
{"title":"Multiple-Layer Multiple-Patterning Aware Placement Refinement for Mixed-Cell-Height Designs","authors":"B. Chen, Chi-Chun Fang, Wai-Kei Mak, Ting-Chi Wang","doi":"10.1145/3439706.3447048","DOIUrl":"https://doi.org/10.1145/3439706.3447048","url":null,"abstract":"Conventional lithography techniques are unable to achieve the resolution required by advance technology nodes. Multiple patterning lithography (MPL) has been introduced as a viable solution. Besides, new standard cell structure with multiple middle-of-line (MOL) layers is adopted to improve intra-cell routability. A mixed-cell-height standard cell library, consisting of cells of single-row and multiple-row heights, is also used in designs for power, performance and area concerns. As a result, it becomes increasingly difficult to get a feasible placement for a mixed-cell-height design where multiple cell layers require MPL. In this paper, we present a methodology to refine a given mixed-cell-height standard cell placement for satisfying MPL requirements on multiple cell layers as much as possible, while minimizing the total cell displacement. We introduce the concept of uncolored cell group (UCG) to facilitate the effective removal of coloring conflicts. By eliminating UCGs without generating any new coloring conflict around them, the number of UCGs is effectively reduced in the local and global refinement stages of our methodology. We report promising experimental results to demonstrate the efficacy of our methodology.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132847939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Reinforcement learning is a machine learning technique that has been applied in many domains, including robotics, game playing, and finance. This talk will briefly introduce reinforcement learning with two use cases related to compiler optimization and chip design. Interested participants will also have materials suggested to learn a more at a technical or non-technical level about this exciting tool.
{"title":"Reinforcement Learning for Electronic Design Automation: Successes and Opportunities","authors":"Matthew E. Taylor","doi":"10.1145/3439706.3446882","DOIUrl":"https://doi.org/10.1145/3439706.3446882","url":null,"abstract":"Reinforcement learning is a machine learning technique that has been applied in many domains, including robotics, game playing, and finance. This talk will briefly introduce reinforcement learning with two use cases related to compiler optimization and chip design. Interested participants will also have materials suggested to learn a more at a technical or non-technical level about this exciting tool.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130872862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Session details: Session 6: Second Keynote","authors":"Ismail Bustany","doi":"10.1145/3457130","DOIUrl":"https://doi.org/10.1145/3457130","url":null,"abstract":"","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125026633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The 2021 International Symposium on Physical Design lifetime achievement award goes to Dr. Louis K. Scheffer for his outstand contributions to the field. This autobiography in Lou's own words provides a glimpse of what has happened through his career.
2021年国际物理设计研讨会终身成就奖授予Louis K. Scheffer博士，以表彰他在该领域的杰出贡献。这本自传用卢自己的话讲述了他职业生涯中发生的事情。
{"title":"A Lifetime of ICs, and Cross-field Exploration: ISPD 2021 Lifetime Achievement Award Bio","authors":"L. Scheffer","doi":"10.1145/3439706.3447046","DOIUrl":"https://doi.org/10.1145/3439706.3447046","url":null,"abstract":"The 2021 International Symposium on Physical Design lifetime achievement award goes to Dr. Louis K. Scheffer for his outstand contributions to the field. This autobiography in Lou's own words provides a glimpse of what has happened through his career.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115723851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Groeneveld, Michael James, V. Kibardin, I. Sharapov, Marvin Tom, Leo Wang
Solving 3-D partial differential equations in a Finite Element model is computationally intensive and requires extremely high memory and communication bandwidth. This paper describes a novel way where the Finite Element mesh points of varying resolution are mapped on a large 2-D homogenous array of processors. Cerebras developed a novel supercomputer that is powered by a 21.5cm by 21.5cm Wafer-Scale Engine (WSE) with 850,000 programmable compute cores. With 2.6 trillion transistors in a 7nm process this is by far the largest chip in the world. It is structured as a regular array of 800 by 1060 identical processing elements, each with its own local fast SRAM memory and direct high bandwidth connection to its neighboring cores. For the 2021 ISPD competition we propose a challenge to optimize placement of computational physics problems to achieve the highest possible performance on the Cerebras supercomputer. The objectives are to maximize performance and accuracy by optimizing the mapping of the problem to cores in the system. This involves partitioning and placement algorithms.
{"title":"ISPD 2021 Wafer-Scale Physics Modeling Contest: A New Frontier for Partitioning, Placement and Routing","authors":"P. Groeneveld, Michael James, V. Kibardin, I. Sharapov, Marvin Tom, Leo Wang","doi":"10.1145/3439706.3446904","DOIUrl":"https://doi.org/10.1145/3439706.3446904","url":null,"abstract":"Solving 3-D partial differential equations in a Finite Element model is computationally intensive and requires extremely high memory and communication bandwidth. This paper describes a novel way where the Finite Element mesh points of varying resolution are mapped on a large 2-D homogenous array of processors. Cerebras developed a novel supercomputer that is powered by a 21.5cm by 21.5cm Wafer-Scale Engine (WSE) with 850,000 programmable compute cores. With 2.6 trillion transistors in a 7nm process this is by far the largest chip in the world. It is structured as a regular array of 800 by 1060 identical processing elements, each with its own local fast SRAM memory and direct high bandwidth connection to its neighboring cores. For the 2021 ISPD competition we propose a challenge to optimize placement of computational physics problems to achieve the highest possible performance on the Cerebras supercomputer. The objectives are to maximize performance and accuracy by optimizing the mapping of the problem to cores in the system. This involves partitioning and placement algorithms.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115383250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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