Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509428
Omair Rafique, K. Schneider
We transfer the concept of plug-and-play devices from general purpose operating systems to sensors and actuators in model-based designs of embedded systems. So far, device vendors take the liberty of writing their device drivers for specific operating systems using their own vendor-specific implementation style. Consequently, the diversity of drivers limits the application of the device and the absence of standardization has even exposed faulty drivers leading to system crashes. In this paper, we therefore introduce the concept of the driver engine framework which generates drivers automatically from a specification provided by device vendors using our standard templates for a model-based design. Moreover, the generality is preserved by using an architecture description language which provides an abstract representation for interaction interfaces of devices.
{"title":"Towards the standardization of plug-and-play devices for model-based designs of embedded systems","authors":"Omair Rafique, K. Schneider","doi":"10.1109/SIES.2016.7509428","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509428","url":null,"abstract":"We transfer the concept of plug-and-play devices from general purpose operating systems to sensors and actuators in model-based designs of embedded systems. So far, device vendors take the liberty of writing their device drivers for specific operating systems using their own vendor-specific implementation style. Consequently, the diversity of drivers limits the application of the device and the absence of standardization has even exposed faulty drivers leading to system crashes. In this paper, we therefore introduce the concept of the driver engine framework which generates drivers automatically from a specification provided by device vendors using our standard templates for a model-based design. Moreover, the generality is preserved by using an architecture description language which provides an abstract representation for interaction interfaces of devices.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124089694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509421
Pedro Benedicte, Leonidas Kosmidis, E. Quiñones, J. Abella, F. Cazorla
Timing is a key non-functional property in embedded real-time systems (ERTS). ERTS increasingly require higher levels of performance that can only be sensibly provided by deploying high-performance hardware, which however complicates timing analysis. Measurement-Based Probabilistic Timing Analysis (MBPTA) aims at analysing the timing behaviour of ERTS deploying complex hardware features such as caches. A key parameter for MBPTA to provide reliable results is the number of runs to perform to ensure probabilistic representativeness of the execution time measurements taken at analysis time with respect to execution times that can occur during system operation. In this paper, focusing on the cache - acknowledged as one of the most complex resources to time analyse - we address the problem of determining whether the number of observations taken at analysis, as part of the normal MBPTA application process, captures the cache events significantly impacting execution time and Worst-Case Execution Time (WCET). If this is not the case, our techniques provide the user with the number of extra runs to perform to guarantee that those cache events are captured ensuring confidence on provided WCET estimates.
{"title":"Modelling the confidence of timing analysis for time randomised caches","authors":"Pedro Benedicte, Leonidas Kosmidis, E. Quiñones, J. Abella, F. Cazorla","doi":"10.1109/SIES.2016.7509421","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509421","url":null,"abstract":"Timing is a key non-functional property in embedded real-time systems (ERTS). ERTS increasingly require higher levels of performance that can only be sensibly provided by deploying high-performance hardware, which however complicates timing analysis. Measurement-Based Probabilistic Timing Analysis (MBPTA) aims at analysing the timing behaviour of ERTS deploying complex hardware features such as caches. A key parameter for MBPTA to provide reliable results is the number of runs to perform to ensure probabilistic representativeness of the execution time measurements taken at analysis time with respect to execution times that can occur during system operation. In this paper, focusing on the cache - acknowledged as one of the most complex resources to time analyse - we address the problem of determining whether the number of observations taken at analysis, as part of the normal MBPTA application process, captures the cache events significantly impacting execution time and Worst-Case Execution Time (WCET). If this is not the case, our techniques provide the user with the number of extra runs to perform to guarantee that those cache events are captured ensuring confidence on provided WCET estimates.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134024950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509433
Joakim Oscarsson, Max Stolz-Sundnes, N. Mohan, V. Izosimov
Highly automated, cooperative driving vehicles will allow for a more fluid flow of traffic, resulting in more efficient, eco-friendly and safe traffic situations. The automotive industry however, is safety critical and current safety standards were not designed to deal with cooperative driving. In this paper, we apply a modern safety analysis method, Systems-Theoretic Process Analysis, in the context of cooperative driving as part of the Grand Cooperative Driving Challenge (GCDC) and present our reflections on the method.
{"title":"Applying systems-theoretic process analysis in the context of cooperative driving","authors":"Joakim Oscarsson, Max Stolz-Sundnes, N. Mohan, V. Izosimov","doi":"10.1109/SIES.2016.7509433","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509433","url":null,"abstract":"Highly automated, cooperative driving vehicles will allow for a more fluid flow of traffic, resulting in more efficient, eco-friendly and safe traffic situations. The automotive industry however, is safety critical and current safety standards were not designed to deal with cooperative driving. In this paper, we apply a modern safety analysis method, Systems-Theoretic Process Analysis, in the context of cooperative driving as part of the Grand Cooperative Driving Challenge (GCDC) and present our reflections on the method.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121880460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509414
Tomasz Kloda, Bruno d'Ausbourg, L. Santinelli
Time-triggered architectures bring to the applications a considerable degree of determinism and a strong conformity between their execution and their logical model. The Extended Timing Definition Language (E-TDL) is a time-triggered framework for programming real-time applications that can be structured through multiple independent components with fully adaptive behaviors. In this paper, we propose a schedulability test for E-TDL applications executed under Earliest Deadline First on a single processor. We derive an efficient solution for evaluating the maximal processor demand over the time intervals during which application may change its operational modes. We provide a detailed insight into the schedulability test procedure and discuss its complexity. Simulation results illustrate the performance of the current implementation of the test.
{"title":"EDF schedulability test for the E-TDL time-triggered framework","authors":"Tomasz Kloda, Bruno d'Ausbourg, L. Santinelli","doi":"10.1109/SIES.2016.7509414","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509414","url":null,"abstract":"Time-triggered architectures bring to the applications a considerable degree of determinism and a strong conformity between their execution and their logical model. The Extended Timing Definition Language (E-TDL) is a time-triggered framework for programming real-time applications that can be structured through multiple independent components with fully adaptive behaviors. In this paper, we propose a schedulability test for E-TDL applications executed under Earliest Deadline First on a single processor. We derive an efficient solution for evaluating the maximal processor demand over the time intervals during which application may change its operational modes. We provide a detailed insight into the schedulability test procedure and discuss its complexity. Simulation results illustrate the performance of the current implementation of the test.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130469782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509415
Christian Scholer, Rene Krenz-Baath, Ayman Murshed, R. Obermaisser
Multi-cluster systems with time-triggered networks are suitable for large safety-critical systems, which benefit from the inherent fault isolation and temporal predictability of the time-triggered paradigm. These networks depend on communication schedules that determine the global points in time for the transmission of messages with conflict-free paths through the switches, while satisfying real-time requirements and precedence constraints. On the basis of a state-of-the-art SMT solver, this paper introduces a novel optimal scheduler for time-triggered networks that is optimized for Boolean conditions and clause learning as required for efficient SMT solving. The ensuing improvements with respect to runtime, memory requirements and scalability are demonstrated by an experimental evaluation in the paper. Furthermore, we present techniques to parallelize the scheduling problem, which make the scheduler more efficient in distributed systems. Due to the lower runtime and memory requirements, the presented scheduler can even be suitable for dynamic computation of schedules in the embedded system itself as required for fault recovery by reconfiguration.
{"title":"Computing optimal communication schedules for time-triggered networks using an SMT solver","authors":"Christian Scholer, Rene Krenz-Baath, Ayman Murshed, R. Obermaisser","doi":"10.1109/SIES.2016.7509415","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509415","url":null,"abstract":"Multi-cluster systems with time-triggered networks are suitable for large safety-critical systems, which benefit from the inherent fault isolation and temporal predictability of the time-triggered paradigm. These networks depend on communication schedules that determine the global points in time for the transmission of messages with conflict-free paths through the switches, while satisfying real-time requirements and precedence constraints. On the basis of a state-of-the-art SMT solver, this paper introduces a novel optimal scheduler for time-triggered networks that is optimized for Boolean conditions and clause learning as required for efficient SMT solving. The ensuing improvements with respect to runtime, memory requirements and scalability are demonstrated by an experimental evaluation in the paper. Furthermore, we present techniques to parallelize the scheduling problem, which make the scheduler more efficient in distributed systems. Due to the lower runtime and memory requirements, the presented scheduler can even be suitable for dynamic computation of schedules in the embedded system itself as required for fault recovery by reconfiguration.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130984834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509407
D. Calvaresi, Paolo Sernani, Mauro Marinoni, A. Claudi, Alessio Balsini, A. Dragoni, G. Buttazzo
Robots interacting with human beings are widespread in modern environments, and those performing intelligent tasks without human supervision need to take into account potential criticalities. Making robots compete enable their evaluation with respect to navigation, mapping, object recognition, tracking and manipulation capabilities. Robot competitions date back to the early '80s proving to be useful for educational and research purposes. Several competitions are focused on human-robot interaction, even though they rarely produce as outcome robots capable to seamlessly interact with human beings. The main reason for this is the lack of understanding of human intentions and the failure to rapidly react to human actions. In other words, an ideal robot must be able to communicate and coordinate with humans or with other robots, to act autonomously, and to react under real-time constraints. This paper proposes a new framework to simplify the development of intelligent robots, testing them in a real robot competition. The framework combines (i) a multi-agent system to interact with humans, other robots and perform object identification and pathfinding, and (ii) a real-time motion control deployed on the Erika RTOS, to move the robot and react in a timely fashion to changes in the environment. In the considered competition scenario, the robot is required to identify and collect common objects in a bounded arena with dynamic obstacles in a limited amount of time, receiving commands from humans and competing with other robots. This approach confirms the powerful combination of multi-agent systems, computer vision, and real-time systems.
{"title":"A framework based on real-time OS and multi-agents for intelligent autonomous robot competitions","authors":"D. Calvaresi, Paolo Sernani, Mauro Marinoni, A. Claudi, Alessio Balsini, A. Dragoni, G. Buttazzo","doi":"10.1109/SIES.2016.7509407","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509407","url":null,"abstract":"Robots interacting with human beings are widespread in modern environments, and those performing intelligent tasks without human supervision need to take into account potential criticalities. Making robots compete enable their evaluation with respect to navigation, mapping, object recognition, tracking and manipulation capabilities. Robot competitions date back to the early '80s proving to be useful for educational and research purposes. Several competitions are focused on human-robot interaction, even though they rarely produce as outcome robots capable to seamlessly interact with human beings. The main reason for this is the lack of understanding of human intentions and the failure to rapidly react to human actions. In other words, an ideal robot must be able to communicate and coordinate with humans or with other robots, to act autonomously, and to react under real-time constraints. This paper proposes a new framework to simplify the development of intelligent robots, testing them in a real robot competition. The framework combines (i) a multi-agent system to interact with humans, other robots and perform object identification and pathfinding, and (ii) a real-time motion control deployed on the Erika RTOS, to move the robot and react in a timely fashion to changes in the environment. In the considered competition scenario, the robot is required to identify and collect common objects in a bounded arena with dynamic obstacles in a limited amount of time, receiving commands from humans and competing with other robots. This approach confirms the powerful combination of multi-agent systems, computer vision, and real-time systems.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126814087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509420
F. Guet, L. Santinelli, J. Morio
Task execution is heavily affected by the different elements composing real-time systems. Modeling and analyzing such effects would allow reducing the pessimism lying behind the worst-cases. A measurement-based probabilistic approach is developed in order to characterize cache behavior with probabilistic average and worst-case profiles. The approach applies also statistics for studying the impact that different system configurations have on the profiles as well as for evaluating the impact of caches on task execution times. The quality of the probabilistic models is verified through test cases with benchmark tasks running on non time-randomized multi-core real-time systems.
{"title":"Probabilistic analysis of cache memories and cache memories impacts on multi-core embedded systems","authors":"F. Guet, L. Santinelli, J. Morio","doi":"10.1109/SIES.2016.7509420","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509420","url":null,"abstract":"Task execution is heavily affected by the different elements composing real-time systems. Modeling and analyzing such effects would allow reducing the pessimism lying behind the worst-cases. A measurement-based probabilistic approach is developed in order to characterize cache behavior with probabilistic average and worst-case profiles. The approach applies also statistics for studying the impact that different system configurations have on the profiles as well as for evaluating the impact of caches on task execution times. The quality of the probabilistic models is verified through test cases with benchmark tasks running on non time-randomized multi-core real-time systems.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125516274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509413
Muhammad Ali Awan, D. Masson, E. Tovar
Heterogeneous multicore platforms are becoming an attractive choice to deploy mixed criticality systems demanding diverse computational requirements. One of the major challenges is to efficiently harness the computational power of these multicore platforms while deploying mixed criticality applications with timeliness properties. Energy efficiency is also one of the desired requirements in the design phase, and therefore it is often difficult for the system designer to simultaneously satisfy those sometimes contradictory requirements. In this paper, we propose a novel partitioning algorithm for unrelated heterogeneous multicore platforms to map mixed criticality applications. The algorithm not only ensures the timeliness in different modes of execution but also tries to allocate the applications to their energy-wise favourite cores. We considered a realistic power model that further increases the relevance of the proposed approach. We have performed an extensive set of experiments to evaluate the performance of the proposed approach, and we show that in the best-case, we achieve a 23.8% gain in the average power dissipation over the state-of-the-art partitioned algorithm. Our proposed algorithm also has a better weighted schedulability when compared to the existing partitioned algorithms.
{"title":"Energy efficient mapping of mixed criticality applications on unrelated heterogeneous multicore platforms","authors":"Muhammad Ali Awan, D. Masson, E. Tovar","doi":"10.1109/SIES.2016.7509413","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509413","url":null,"abstract":"Heterogeneous multicore platforms are becoming an attractive choice to deploy mixed criticality systems demanding diverse computational requirements. One of the major challenges is to efficiently harness the computational power of these multicore platforms while deploying mixed criticality applications with timeliness properties. Energy efficiency is also one of the desired requirements in the design phase, and therefore it is often difficult for the system designer to simultaneously satisfy those sometimes contradictory requirements. In this paper, we propose a novel partitioning algorithm for unrelated heterogeneous multicore platforms to map mixed criticality applications. The algorithm not only ensures the timeliness in different modes of execution but also tries to allocate the applications to their energy-wise favourite cores. We considered a realistic power model that further increases the relevance of the proposed approach. We have performed an extensive set of experiments to evaluate the performance of the proposed approach, and we show that in the best-case, we achieve a 23.8% gain in the average power dissipation over the state-of-the-art partitioned algorithm. Our proposed algorithm also has a better weighted schedulability when compared to the existing partitioned algorithms.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127672389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509441
J. Jalle, E. Quiñones, J. Abella, L. Fossati, Marco Zulianello, F. Cazorla
Memory access contention is one of the main contributors to tasks' execution time variability in real-time multicores. Existing techniques to control memory contention based on time-sharing memory access do not scale well with increasing complexity of multicores, leading to a rapid increase of WCET estimates. This is due to fact that requests from different tasks interleave in the access to memory, and for each of its requests a task has to make worst-case time allowances to account for the memory state left by the previous request, that may belong to a different task. In this paper, we propose a memory organization that controls contention by dividing the data bus into narrower independent data buses, thus removing conflicts among different tasks accessing memory. While narrower data buses require extra transfers, they allow exploiting memory locality, hence only slightly affecting average performance. Our evaluation on a solid space case-study shows that the proposed memory organization provides contention-free memory access facilitating timing analysis and tightening WCET estimates.
{"title":"Data Bus Slicing for Contention-Free Multicore Real-Time Memory Systems","authors":"J. Jalle, E. Quiñones, J. Abella, L. Fossati, Marco Zulianello, F. Cazorla","doi":"10.1109/SIES.2016.7509441","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509441","url":null,"abstract":"Memory access contention is one of the main contributors to tasks' execution time variability in real-time multicores. Existing techniques to control memory contention based on time-sharing memory access do not scale well with increasing complexity of multicores, leading to a rapid increase of WCET estimates. This is due to fact that requests from different tasks interleave in the access to memory, and for each of its requests a task has to make worst-case time allowances to account for the memory state left by the previous request, that may belong to a different task. In this paper, we propose a memory organization that controls contention by dividing the data bus into narrower independent data buses, thus removing conflicts among different tasks accessing memory. While narrower data buses require extra transfers, they allow exploiting memory locality, hence only slightly affecting average performance. Our evaluation on a solid space case-study shows that the proposed memory organization provides contention-free memory access facilitating timing analysis and tightening WCET estimates.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116904632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509442
Antonio Barros, P. Yomsi, L. M. Pinho
Software transactional memory (STM) is a synchronisation paradigm which improves the parallelism and composability of modern applications executing on a multi-core architecture. However, to abort and retry a transaction multiple times may have a negative impact on the temporal characteristics of a real-time task set. This paper addresses this issue: It provides a framework in which an upper-bound on the worst-case response time of each task is derived, assuming that tasks are scheduled by following either the Non-Preemptive During Attempt (NPDA), Non-Preemptive Until Commit (NPUC) or Stack Resource Policy for Transactional Memory (SRPTM) policy.
{"title":"Response time analysis of hard real-time tasks sharing software transactional memory data under fully partitioned scheduling","authors":"Antonio Barros, P. Yomsi, L. M. Pinho","doi":"10.1109/SIES.2016.7509442","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509442","url":null,"abstract":"Software transactional memory (STM) is a synchronisation paradigm which improves the parallelism and composability of modern applications executing on a multi-core architecture. However, to abort and retry a transaction multiple times may have a negative impact on the temporal characteristics of a real-time task set. This paper addresses this issue: It provides a framework in which an upper-bound on the worst-case response time of each task is derived, assuming that tasks are scheduled by following either the Non-Preemptive During Attempt (NPDA), Non-Preemptive Until Commit (NPUC) or Stack Resource Policy for Transactional Memory (SRPTM) policy.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"277 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121363238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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