Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509408
Luca Rizzon, R. Passerone
To analyze embedded systems, engineers use tools that can simulate the performance of software components executed on hardware architectures. When the embedded system functionality is strongly correlated to physical quantities, as in the case of Cyber-Physical System (CPS), we need to model physical processes to determine the overall behavior of the system. Unfortunately, embedded systems simulators are not generally suitable to evaluate physical processes, and in the same way physical model simulators hardly capture the functionality of computing systems. In this work, we present a methodology to concurrently explore these aspects using the METROII design framework. In this work, we provide guidelines for the implementation of these models in the design environment, and discuss the results gathered with the simulator for two case studies.
{"title":"Cyber/physical co-design in practice: Case studies in metroII","authors":"Luca Rizzon, R. Passerone","doi":"10.1109/SIES.2016.7509408","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509408","url":null,"abstract":"To analyze embedded systems, engineers use tools that can simulate the performance of software components executed on hardware architectures. When the embedded system functionality is strongly correlated to physical quantities, as in the case of Cyber-Physical System (CPS), we need to model physical processes to determine the overall behavior of the system. Unfortunately, embedded systems simulators are not generally suitable to evaluate physical processes, and in the same way physical model simulators hardly capture the functionality of computing systems. In this work, we present a methodology to concurrently explore these aspects using the METROII design framework. In this work, we provide guidelines for the implementation of these models in the design environment, and discuss the results gathered with the simulator for two case studies.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"28 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120845844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509438
S. Adyanthaya, M. Geilen, T. Basten, J. Voeten, R. Schiffelers
We present a three-step binding algorithm for applications in the form of directed acyclic graphs (DAGs) of tasks with deadlines, that need to be bound to a shared memory multiprocessor platform. The aim of the algorithm is to obtain a good binding that results in low makespans of the schedules of the DAGs. It first clusters tasks assuming unlimited resources using a deadline-aware shared memory extension of the existing dominant sequence clustering algorithm. Second, the clusters produced are merged based on communication dependencies to fit into the number of available platform resources. As a final step, the clusters are allocated to the available resources by balancing the workload. The approach is compared to the state of the art bounded dominant sequence clustering (BDSC) algorithm that also performs clustering on a limited number of resources. We show that our three-step algorithm makes better use of the shared memory communication structure and produces significantly lower makespans than BDSC on benchmark cases.
{"title":"Communication aware multiprocessor binding for shared memory systems","authors":"S. Adyanthaya, M. Geilen, T. Basten, J. Voeten, R. Schiffelers","doi":"10.1109/SIES.2016.7509438","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509438","url":null,"abstract":"We present a three-step binding algorithm for applications in the form of directed acyclic graphs (DAGs) of tasks with deadlines, that need to be bound to a shared memory multiprocessor platform. The aim of the algorithm is to obtain a good binding that results in low makespans of the schedules of the DAGs. It first clusters tasks assuming unlimited resources using a deadline-aware shared memory extension of the existing dominant sequence clustering algorithm. Second, the clusters produced are merged based on communication dependencies to fit into the number of available platform resources. As a final step, the clusters are allocated to the available resources by balancing the workload. The approach is compared to the state of the art bounded dominant sequence clustering (BDSC) algorithm that also performs clustering on a limited number of resources. We show that our three-step algorithm makes better use of the shared memory communication structure and produces significantly lower makespans than BDSC on benchmark cases.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114315633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509431
R. Medina, Etienne Borde, L. Pautet
The safety-critical industry is compelled to continually increase the number of functionalities in embedded systems. These platforms tend to integrate software with various non-functional requirements, in particular different levels of criticality. As a consequence, Mixed-Criticality Systems emerged in order to assure robustness, safety and predictability for these embedded platforms. Although Mixed-Critcality Systems show promising results, formal methods to quantify availability are still missing for this type of systems and will most likely be required for deployment. This paper presents a transformation process that first produces a formal model of a Mixed-Criticality System. From this formal model, it generates a PRISM automaton in order to compute availability.
{"title":"Availability analysis for synchronous data-flow graphs in mixed-criticality systems","authors":"R. Medina, Etienne Borde, L. Pautet","doi":"10.1109/SIES.2016.7509431","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509431","url":null,"abstract":"The safety-critical industry is compelled to continually increase the number of functionalities in embedded systems. These platforms tend to integrate software with various non-functional requirements, in particular different levels of criticality. As a consequence, Mixed-Criticality Systems emerged in order to assure robustness, safety and predictability for these embedded platforms. Although Mixed-Critcality Systems show promising results, formal methods to quantify availability are still missing for this type of systems and will most likely be required for deployment. This paper presents a transformation process that first produces a formal model of a Mixed-Criticality System. From this formal model, it generates a PRISM automaton in order to compute availability.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131450708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509425
Dimitry Solet, Jean-Luc Béchennec, M. Briday, S. Faucou, S. Pillement
This paper discusses an implementation of runtime verification for embedded software running on a System-on-Programmable-Chip (SoPC) composed of a micro-controller and a FPGA. The goal is to verify at runtime that the execution of the software on the micro-controller conforms to a set of properties. To do so, a minimal instrumentation of the software is used to send events to a set of monitors implemented in the FPGA. These monitors are synthesised from a formal specification of the expected behavior of the system expressed as a set of past-time linear temporal logic (ptLTL) formulas.
{"title":"Hardware runtime verification of embedded software in SoPC","authors":"Dimitry Solet, Jean-Luc Béchennec, M. Briday, S. Faucou, S. Pillement","doi":"10.1109/SIES.2016.7509425","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509425","url":null,"abstract":"This paper discusses an implementation of runtime verification for embedded software running on a System-on-Programmable-Chip (SoPC) composed of a micro-controller and a FPGA. The goal is to verify at runtime that the execution of the software on the micro-controller conforms to a set of properties. To do so, a minimal instrumentation of the software is used to send events to a set of monitors implemented in the FPGA. These monitors are synthesised from a formal specification of the expected behavior of the system expressed as a set of past-time linear temporal logic (ptLTL) formulas.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133698444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509418
Martin Lowinski, D. Ziegenbein, S. Glesner
Real-time automotive software becomes increasingly complex due to the integration of more functionalities. At the same time, the computation power of electronic control units grows by increasing the number of cores instead of the core performance. Thus, in the near future a single task will require more computation power than a single core can offer. We propose an approach that solves this problem by splitting a task into multiple parallel task partitions with minimal synchronization overhead while maintaining all data dependencies of the functionalities inside the original task. The approach is successfully validated on a real-world engine management system.
{"title":"Splitting tasks for migrating real-time automotive applications to multi-core ECUs","authors":"Martin Lowinski, D. Ziegenbein, S. Glesner","doi":"10.1109/SIES.2016.7509418","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509418","url":null,"abstract":"Real-time automotive software becomes increasingly complex due to the integration of more functionalities. At the same time, the computation power of electronic control units grows by increasing the number of cores instead of the core performance. Thus, in the near future a single task will require more computation power than a single core can offer. We propose an approach that solves this problem by splitting a task into multiple parallel task partitions with minimal synchronization overhead while maintaining all data dependencies of the functionalities inside the original task. The approach is successfully validated on a real-world engine management system.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125952239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509427
Padma Iyenghar, Arne Noyer, Joachim Engelhardt, E. Pulvermüller, C. Westerkamp
Extending model-based Non-Functional Property (NFP) analysis approaches to Embedded Software Engineering (ESE) projects cutting across heterogeneous modeling domains is an emerging research challenge. Towards this direction, a generic workflow for timing validation and a methodology for synchronization of timing attributes (before performing a timing analysis) in ESE projects developed using heterogeneous modeling domains is proposed in this paper. An experimental evaluation of the proposed approach, in a state-of-the-art timing analysis tool, using a real life, light-weight ESE project, developed using Unified Modeling Language (UML) and Simulink is presented.
{"title":"End-to-end path delay estimation in embedded software involving heterogeneous models","authors":"Padma Iyenghar, Arne Noyer, Joachim Engelhardt, E. Pulvermüller, C. Westerkamp","doi":"10.1109/SIES.2016.7509427","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509427","url":null,"abstract":"Extending model-based Non-Functional Property (NFP) analysis approaches to Embedded Software Engineering (ESE) projects cutting across heterogeneous modeling domains is an emerging research challenge. Towards this direction, a generic workflow for timing validation and a methodology for synchronization of timing attributes (before performing a timing analysis) in ESE projects developed using heterogeneous modeling domains is proposed in this paper. An experimental evaluation of the proposed approach, in a state-of-the-art timing analysis tool, using a real life, light-weight ESE project, developed using Unified Modeling Language (UML) and Simulink is presented.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129407535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509416
G. Cena, S. Scanzio, L. Seno, A. Valenzano
Wireless networks are typically deemed not reliable enough to address real-time requirements typical of industrial distributed control applications. Several solutions were proposed in the past years to overcome their limitations and make them suitable for those (soft) real-time applications where a limited percentage of deadlines can be missed. A promising approach relies on centralized transmission (and retransmission) scheduling and exploits well-known results for feasibility analysis to provide a priori guarantees on performance. This paper focuses on a framework based on non-preemptive EDF transmission scheduling and takes into account two retransmission strategies. A prototype framework implementation, relying on conventional Linux platforms and employing Wi-Fi technology, is then exploited to perform a preliminary performance assessment. To provide useful implementation guidelines, the paper investigates how the choice of retransmission strategy and of the parameters to be used in feasibility analysis may affect performance.
{"title":"A soft real-time scheduling framework for wireless industrial sensor actuator networks","authors":"G. Cena, S. Scanzio, L. Seno, A. Valenzano","doi":"10.1109/SIES.2016.7509416","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509416","url":null,"abstract":"Wireless networks are typically deemed not reliable enough to address real-time requirements typical of industrial distributed control applications. Several solutions were proposed in the past years to overcome their limitations and make them suitable for those (soft) real-time applications where a limited percentage of deadlines can be missed. A promising approach relies on centralized transmission (and retransmission) scheduling and exploits well-known results for feasibility analysis to provide a priori guarantees on performance. This paper focuses on a framework based on non-preemptive EDF transmission scheduling and takes into account two retransmission strategies. A prototype framework implementation, relying on conventional Linux platforms and employing Wi-Fi technology, is then exploited to perform a preliminary performance assessment. To provide useful implementation guidelines, the paper investigates how the choice of retransmission strategy and of the parameters to be used in feasibility analysis may affect performance.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121486254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509424
Maya H. Safieddine, F. Zaraket, Mohamad Jaber, R. Kanj, M. Saghir
Embedded system designs have IP components that each may be implemented as either software or realtime accelerated hardware depending on the logic and the available resources. FPGA implementations are desirable hardware implementations for embedded systems since they are reconfigurable and several IP components can be deployed on the same FPGA board. BIP is a framework that facilitates correct-by-construction design of embedded systems by leveraging (1) a component based design paradigm and (2) the separation of behavior, interaction, and priority concerns. In this paper, we present the first automated design flow that takes a BIP design into an efficient FPGA implementation. We first transform the design into a one loop program implemented in C/C++ and then take the program into a sequential circuit implemented on an FPGA. We evaluate the design flow with the ATM and Quorom designs. We compare the results in terms of efficiency and performance of the software realizations of the BIP design such as regular BIP, enhanced flat BIP, and C/C++ simulations. We rely on the BIP engine to simulate regular BIP and flat BIP. The FPGA implementation is shown to be at least 16x-30x faster than the enhanced flat BIP implementation and 7x-10x faster than the C/C++ software realization running on state-of-the-art processors. Our experiments show higher performance improvement for larger design systems.
{"title":"Automated FPGA implementations of BIP designs","authors":"Maya H. Safieddine, F. Zaraket, Mohamad Jaber, R. Kanj, M. Saghir","doi":"10.1109/SIES.2016.7509424","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509424","url":null,"abstract":"Embedded system designs have IP components that each may be implemented as either software or realtime accelerated hardware depending on the logic and the available resources. FPGA implementations are desirable hardware implementations for embedded systems since they are reconfigurable and several IP components can be deployed on the same FPGA board. BIP is a framework that facilitates correct-by-construction design of embedded systems by leveraging (1) a component based design paradigm and (2) the separation of behavior, interaction, and priority concerns. In this paper, we present the first automated design flow that takes a BIP design into an efficient FPGA implementation. We first transform the design into a one loop program implemented in C/C++ and then take the program into a sequential circuit implemented on an FPGA. We evaluate the design flow with the ATM and Quorom designs. We compare the results in terms of efficiency and performance of the software realizations of the BIP design such as regular BIP, enhanced flat BIP, and C/C++ simulations. We rely on the BIP engine to simulate regular BIP and flat BIP. The FPGA implementation is shown to be at least 16x-30x faster than the enhanced flat BIP implementation and 7x-10x faster than the C/C++ software realization running on state-of-the-art processors. Our experiments show higher performance improvement for larger design systems.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131824559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509426
K. H. Salem, Yann Kieffer, S. Mancini
In the field of embedded vision systems, meeting the constraints on design criteria such as performance, area, and power consumption can be a real challenge. In fact, to alleviate the well known “Memory Mall”, it is mandatory to provide efficient memory hierarchies to reach usable performance for the system to be designed when it has to handle non-linear image treatments. To address this problematic, Mancini and Rousseau (Proc.DATE, 2012) have designed a software generator of memory hierarchies for each non-linear image operation. It allows one to improve dramatically the performance of the system, while moderately increasing its area and energy consumption. The trade-offs between these three parameters are then taken to the level of the design of the operation of this memory hierarchy, a problem that can be formalized as a 3-objective optimization problem. In this study, we formalize this problem and give new approaches both for the problem and particular sub-problems. The results on the same real-world data set as used by Mancini and Rousseau (Proc.DATE, 2012) show a very significant improvement and reduce the amount of transferred data up to 30% and a reduction of the computing time up to 15%.
{"title":"Efficient algorithms for memory management in embedded vision systems","authors":"K. H. Salem, Yann Kieffer, S. Mancini","doi":"10.1109/SIES.2016.7509426","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509426","url":null,"abstract":"In the field of embedded vision systems, meeting the constraints on design criteria such as performance, area, and power consumption can be a real challenge. In fact, to alleviate the well known “Memory Mall”, it is mandatory to provide efficient memory hierarchies to reach usable performance for the system to be designed when it has to handle non-linear image treatments. To address this problematic, Mancini and Rousseau (Proc.DATE, 2012) have designed a software generator of memory hierarchies for each non-linear image operation. It allows one to improve dramatically the performance of the system, while moderately increasing its area and energy consumption. The trade-offs between these three parameters are then taken to the level of the design of the operation of this memory hierarchy, a problem that can be formalized as a 3-objective optimization problem. In this study, we formalize this problem and give new approaches both for the problem and particular sub-problems. The results on the same real-world data set as used by Mancini and Rousseau (Proc.DATE, 2012) show a very significant improvement and reduce the amount of transferred data up to 30% and a reduction of the computing time up to 15%.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115492986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509411
Stephan Schnitzer, Simon Gansel, Frank Dürr, K. Rothermel
3D graphical functions in cars enjoy growing popularity. For instance, analog instruments of the instrument cluster are replaced by digital 3D displays as shown by Mercedes-Benz in the F125 prototype car. The trend to use 3D applications expands into two directions: towards more safety-relevant applications such as the speedometer and towards third-party applications, e.g., from an app store. In order to save cost, energy, and installation space, all these applications should share a single GPU. GPU sharing brings up the problem of providing real-time guarantees for rendering content of time-sensitive applications like the speedometer. To solve this problem, we present a real-time GPU scheduling framework which provides strong guarantees for critical applications while still giving as much GPU resources to less important applications as possible, thus ensuring a high GPU utilization. Since current GPUs are not preemptible, we use the estimated execution time of each GPU rendering job to make the scheduling decisions. Our evaluations show that our scheduler guarantees given real-time constraints, while achieving a high GPU utilization of 97%. Moreover, scheduling is performed highly efficient in real-time with less than 10 μs latency.
{"title":"Real-time scheduling for 3D GPU rendering","authors":"Stephan Schnitzer, Simon Gansel, Frank Dürr, K. Rothermel","doi":"10.1109/SIES.2016.7509411","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509411","url":null,"abstract":"3D graphical functions in cars enjoy growing popularity. For instance, analog instruments of the instrument cluster are replaced by digital 3D displays as shown by Mercedes-Benz in the F125 prototype car. The trend to use 3D applications expands into two directions: towards more safety-relevant applications such as the speedometer and towards third-party applications, e.g., from an app store. In order to save cost, energy, and installation space, all these applications should share a single GPU. GPU sharing brings up the problem of providing real-time guarantees for rendering content of time-sensitive applications like the speedometer. To solve this problem, we present a real-time GPU scheduling framework which provides strong guarantees for critical applications while still giving as much GPU resources to less important applications as possible, thus ensuring a high GPU utilization. Since current GPUs are not preemptible, we use the estimated execution time of each GPU rendering job to make the scheduling decisions. Our evaluations show that our scheduler guarantees given real-time constraints, while achieving a high GPU utilization of 97%. Moreover, scheduling is performed highly efficient in real-time with less than 10 μs latency.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"619 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123322748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：