Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509409
D. Darvas, I. Majzik, E. B. Viñuela
Verification of industrial control systems' software is an important task, as the cost of failure in these systems is typically high. Formal verification methods can complement the currently used testing techniques, especially if requirements are formally specified. Behavioural specifications can be used to perform conformance checking against the implementation. However, the typical conformance relations are often more sensitive to differences than the controlled processes in case of many control systems, resulting in counterexamples during verification that are considered as false positives in practice. To overcome this issue, we introduce conformance relations adapted to control systems based on programmable logic controllers (PLCs) with different levels of permissibility. The relations can be selected by the control engineers, depending on the required compliance levels. Defining the new relations and a model checking-based method to check them makes conformance checking a powerful tool for the verification of industrial control systems.
{"title":"Conformance checking for programmable logic controller programs and specifications","authors":"D. Darvas, I. Majzik, E. B. Viñuela","doi":"10.1109/SIES.2016.7509409","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509409","url":null,"abstract":"Verification of industrial control systems' software is an important task, as the cost of failure in these systems is typically high. Formal verification methods can complement the currently used testing techniques, especially if requirements are formally specified. Behavioural specifications can be used to perform conformance checking against the implementation. However, the typical conformance relations are often more sensitive to differences than the controlled processes in case of many control systems, resulting in counterexamples during verification that are considered as false positives in practice. To overcome this issue, we introduce conformance relations adapted to control systems based on programmable logic controllers (PLCs) with different levels of permissibility. The relations can be selected by the control engineers, depending on the required compliance levels. Defining the new relations and a model checking-based method to check them makes conformance checking a powerful tool for the verification of industrial control systems.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115865120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509437
R. Brzoza-Woch, Marek Konieczny, Piotr Nawrocki, T. Szydlo, K. Zielinski
The goal of this paper is to discuss the application of fog computing concept realized with embedded systems for environment monitoring in case of emergency situations such as flood, earthquakes, landslides, etc. We also present a practical realization of a hardware-software platform for such a system by applying the described ideas to a smart levee monitoring station. The realization of our concept is based on a multi-variant embedded platform for an autonomous data acquisition and processing station. The system is being tested in an experimental setup in a life-size artificial levee.
{"title":"Embedded systems in the application of fog computing — Levee monitoring use case","authors":"R. Brzoza-Woch, Marek Konieczny, Piotr Nawrocki, T. Szydlo, K. Zielinski","doi":"10.1109/SIES.2016.7509437","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509437","url":null,"abstract":"The goal of this paper is to discuss the application of fog computing concept realized with embedded systems for environment monitoring in case of emergency situations such as flood, earthquakes, landslides, etc. We also present a practical realization of a hardware-software platform for such a system by applying the described ideas to a smart levee monitoring station. The realization of our concept is based on a multi-variant embedded platform for an autonomous data acquisition and processing station. The system is being tested in an experimental setup in a life-size artificial levee.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127791871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509443
J. Fonseca, Geoffrey Nelissen, Vincent Nélis, L. M. Pinho
Several schedulability analyses have been proposed for a variety of parallel task systems with real-time constraints. However, these analyses are mostly restricted to global scheduling policies. The problem with global scheduling is that it adds uncertainty to the lower-level timing analysis which on multicore systems are heavily context-dependent. As parallel tasks typically exhibit intense communication and concurrency among their sequential computational units, this problem is further exacerbated. This paper considers instead the schedulability of partitioned parallel tasks. More precisely, we present a response time analysis for sporadic DAG tasks atop multiprocessors under partitioned fixed-priority scheduling. We assume the partitioning to be given. We show that a partitioned DAG task can be modeled as a set of self-suspending tasks. We then propose an algorithm to traverse a DAG and characterize such worst-case scheduling scenario. With minor modifications, any state-of-the-art technique for sporadic self-suspending tasks can thus be used to derived the worst-case response time of a partitioned DAG task. Experiments show that the proposed approach significantly tightens the worst-case response time of partitioned parallel tasks comparatively to the state-of-the-art when the most accurate technique is chosen.
{"title":"Response time analysis of sporadic DAG tasks under partitioned scheduling","authors":"J. Fonseca, Geoffrey Nelissen, Vincent Nélis, L. M. Pinho","doi":"10.1109/SIES.2016.7509443","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509443","url":null,"abstract":"Several schedulability analyses have been proposed for a variety of parallel task systems with real-time constraints. However, these analyses are mostly restricted to global scheduling policies. The problem with global scheduling is that it adds uncertainty to the lower-level timing analysis which on multicore systems are heavily context-dependent. As parallel tasks typically exhibit intense communication and concurrency among their sequential computational units, this problem is further exacerbated. This paper considers instead the schedulability of partitioned parallel tasks. More precisely, we present a response time analysis for sporadic DAG tasks atop multiprocessors under partitioned fixed-priority scheduling. We assume the partitioning to be given. We show that a partitioned DAG task can be modeled as a set of self-suspending tasks. We then propose an algorithm to traverse a DAG and characterize such worst-case scheduling scenario. With minor modifications, any state-of-the-art technique for sporadic self-suspending tasks can thus be used to derived the worst-case response time of a partitioned DAG task. Experiments show that the proposed approach significantly tightens the worst-case response time of partitioned parallel tasks comparatively to the state-of-the-art when the most accurate technique is chosen.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127646781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509430
Louis-Marie Givel, Jean-Luc Béchennec, M. Brun, S. Faucou, O. Roux
Real-time embedded systems are complex, and as such need to be tested with regards to real-time constraints. However, because of this complexity, some states of the systems can be hard to reach through acting on the input sequence alone, because of seemingly non-deterministic behaviors. In this paper, we introduce a solution based on runtime enforcement which forces a real-time system to reach a chosen state. This can allow for testing of the consequences of reaching this state for the system. Let us consider for example a fault tolerance mechanism that activates when a state of the system is reached. Our solution makes it possible to force the system to consistently reach the state in which the fault tolerance mechanism is started. The solution is based on both an offline analysis and a runtime enforcement step which uses the result of the offline analysis. The runtime enforcement is achieved through the introduction of delays during the execution of the system.
{"title":"Testing real-time embedded software using runtime enforcement","authors":"Louis-Marie Givel, Jean-Luc Béchennec, M. Brun, S. Faucou, O. Roux","doi":"10.1109/SIES.2016.7509430","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509430","url":null,"abstract":"Real-time embedded systems are complex, and as such need to be tested with regards to real-time constraints. However, because of this complexity, some states of the systems can be hard to reach through acting on the input sequence alone, because of seemingly non-deterministic behaviors. In this paper, we introduce a solution based on runtime enforcement which forces a real-time system to reach a chosen state. This can allow for testing of the consequences of reaching this state for the system. Let us consider for example a fault tolerance mechanism that activates when a state of the system is reached. Our solution makes it possible to force the system to consistently reach the state in which the fault tolerance mechanism is started. The solution is based on both an offline analysis and a runtime enforcement step which uses the result of the offline analysis. The runtime enforcement is achieved through the introduction of delays during the execution of the system.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131281979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509404
G. Corradi
These keynotes discuss the following: Heterogeneous processors in SoC simplifies integration of IEC61508 and ISO26262 functional safety designs; What is happening to Cyber Physical Systems?; and Scalable (yet precise) Timing Verification of Embedded Software.
{"title":"Keynote at SIES: Heterogeneous processors in SoC simplifies integration of IEC61508 and ISO26262 functional safety designs. The ZYNQ7000 experience","authors":"G. Corradi","doi":"10.1109/SIES.2016.7509404","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509404","url":null,"abstract":"These keynotes discuss the following: Heterogeneous processors in SoC simplifies integration of IEC61508 and ISO26262 functional safety designs; What is happening to Cyber Physical Systems?; and Scalable (yet precise) Timing Verification of Embedded Software.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134298427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509417
L. Hatvani, R. J. Bril
Fixed priority preemption threshold scheduling (FPTS) may significantly improve the schedulability ratio of task sets compared to both fixed-priority pre-emptive scheduling (FPPS) and fixed-priority non-preemptive scheduling (FPNS). Moreover, FPTS reduces stack memory requirements compared to FPPS. Unfortunately, the scheduling policy defined by the standard automotive platform AUTOSAR/OSEK only supports a restricted version of FPTS. In earlier work, the consequences of these limitations have been investigated for the schedulability ratio of task sets on a uniprocessor platform. This paper considers the consequences for the stack memory requirements. To that end, it presents a preemption threshold assignment algorithm for minimizing stack usage under FPTS on an AUTOSAR/OSEK platform. The paper includes a comparative evaluation of the stack usage of FPTS without restrictions and FPTS as defined by AUTOSAR/OSEK.
{"title":"Minimizing stack usage for AUTOSAR/OSEK's restricted fixed-priority preemption threshold support","authors":"L. Hatvani, R. J. Bril","doi":"10.1109/SIES.2016.7509417","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509417","url":null,"abstract":"Fixed priority preemption threshold scheduling (FPTS) may significantly improve the schedulability ratio of task sets compared to both fixed-priority pre-emptive scheduling (FPPS) and fixed-priority non-preemptive scheduling (FPNS). Moreover, FPTS reduces stack memory requirements compared to FPPS. Unfortunately, the scheduling policy defined by the standard automotive platform AUTOSAR/OSEK only supports a restricted version of FPTS. In earlier work, the consequences of these limitations have been investigated for the schedulability ratio of task sets on a uniprocessor platform. This paper considers the consequences for the stack memory requirements. To that end, it presents a preemption threshold assignment algorithm for minimizing stack usage under FPTS on an AUTOSAR/OSEK platform. The paper includes a comparative evaluation of the stack usage of FPTS without restrictions and FPTS as defined by AUTOSAR/OSEK.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116311284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509406
Róbinson Medina Sánchez, S. Stuijk, Dip Goswami, T. Basten
Image-based control systems are becoming common in domains such as robotics, healthcare and industrial automation. Coping with a long sample period because of the latency of the image processing algorithm is an open challenge. Modern multi-core platforms allow to address this challenge by pipelining the sensing algorithm. Often, such systems share the resources with other tasks. We show that the performance of an image-based controller can be improved by pipelining the image processing algorithm on unallocated cores. It can be further improved by dynamically allocating (i.e. reconfiguring) cores that are temporarily not used by other tasks to the sensing pipeline. We present a state-based modelling strategy for pipelined and reconfigurable pipelined sensing. We introduce a control design strategy for reconfigurable pipelined systems that assures stability and shows improvement in the control performance.
{"title":"Reconfigurable pipelined sensing for image-based control","authors":"Róbinson Medina Sánchez, S. Stuijk, Dip Goswami, T. Basten","doi":"10.1109/SIES.2016.7509406","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509406","url":null,"abstract":"Image-based control systems are becoming common in domains such as robotics, healthcare and industrial automation. Coping with a long sample period because of the latency of the image processing algorithm is an open challenge. Modern multi-core platforms allow to address this challenge by pipelining the sensing algorithm. Often, such systems share the resources with other tasks. We show that the performance of an image-based controller can be improved by pipelining the image processing algorithm on unallocated cores. It can be further improved by dynamically allocating (i.e. reconfiguring) cores that are temporarily not used by other tasks to the sensing pipeline. We present a state-based modelling strategy for pipelined and reconfigurable pipelined sensing. We introduce a control design strategy for reconfigurable pipelined systems that assures stability and shows improvement in the control performance.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132965795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509432
Dominik Schoenwetter, Alexander Ditter, D. Fey, Ralph Mader
High level simulation and modeling techniques have matured significantly over the last years and have become more and more important in practice, e.g., in the industrial hardware development and especially the automotive domain. Complex and detailed modeling requires a lot of time during preparation and execution, is quite error prone and thus, reduces the average time-to-market significantly. One popular approach to mitigate this problem is statistical modeling and simulation. In this paper, we focus on another high level simulation approach for determining accurate runtimes of applications using instruction accurate modeling and simulation. We extend the basic instruction accurate simulation technology from OVP using cache models in conjunction with a statistical cost function, which enables high precision runtime predictions with an significant improvement over the pure instruction accurate approach.
{"title":"Improving instruction accurate simulation for parallel automotive applications","authors":"Dominik Schoenwetter, Alexander Ditter, D. Fey, Ralph Mader","doi":"10.1109/SIES.2016.7509432","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509432","url":null,"abstract":"High level simulation and modeling techniques have matured significantly over the last years and have become more and more important in practice, e.g., in the industrial hardware development and especially the automotive domain. Complex and detailed modeling requires a lot of time during preparation and execution, is quite error prone and thus, reduces the average time-to-market significantly. One popular approach to mitigate this problem is statistical modeling and simulation. In this paper, we focus on another high level simulation approach for determining accurate runtimes of applications using instruction accurate modeling and simulation. We extend the basic instruction accurate simulation technology from OVP using cache models in conjunction with a statistical cost function, which enables high precision runtime predictions with an significant improvement over the pure instruction accurate approach.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127854809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509440
J. Jalle, Mikel Fernández, J. Abella, J. Andersson, Mathieu Patte, L. Fossati, Marco Zulianello, F. Cazorla
Tasks running in MPSoCs experience contention delays when accessing MPSoC's shared resources, complicating task timing analysis and deriving execution time bounds. Understanding the Actual Contention Delay (ACD) each task suffers due to other corunning tasks, and the particular hardware shared resources in which contention occurs, is of prominent importance to increase confidence on derived execution time bounds of tasks. And, whenever those bounds are violated, ACD provides information on the reasons for overruns. Unfortunately, existing MPSoC designs considered in real-time domains offer limited hardware support to measure tasks' ACD losing all these potential benefits. In this paper we propose the Contention Cycle Stack (CCS), a mechanism that extends performance monitoring counters to track specific events that allow estimating the ACD that each task suffers from every contending task on every hardware shared resource. We build the CCS using a set of specialized low-overhead Performance Monitoring Counters for the Cobham Gaisler GR740 (NGMP) MPSoC - used in the space domain - for which we show CCS's benefits.
{"title":"Contention-aware performance monitoring counter support for real-time MPSoCs","authors":"J. Jalle, Mikel Fernández, J. Abella, J. Andersson, Mathieu Patte, L. Fossati, Marco Zulianello, F. Cazorla","doi":"10.1109/SIES.2016.7509440","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509440","url":null,"abstract":"Tasks running in MPSoCs experience contention delays when accessing MPSoC's shared resources, complicating task timing analysis and deriving execution time bounds. Understanding the Actual Contention Delay (ACD) each task suffers due to other corunning tasks, and the particular hardware shared resources in which contention occurs, is of prominent importance to increase confidence on derived execution time bounds of tasks. And, whenever those bounds are violated, ACD provides information on the reasons for overruns. Unfortunately, existing MPSoC designs considered in real-time domains offer limited hardware support to measure tasks' ACD losing all these potential benefits. In this paper we propose the Contention Cycle Stack (CCS), a mechanism that extends performance monitoring counters to track specific events that allow estimating the ACD that each task suffers from every contending task on every hardware shared resource. We build the CCS using a set of specialized low-overhead Performance Monitoring Counters for the Cobham Gaisler GR740 (NGMP) MPSoC - used in the space domain - for which we show CCS's benefits.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117029353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/SIES.2016.7509444
Hadi Alizadeh Ara, M. Geilen, T. Basten, A. Behrouzian, M. Hendriks, Dip Goswami
We present an analysis method that provides tight temporal bounds for applications modeled by Synchronous Dataflow Graphs and mapped to shared resources. We consider the resource sharing effects on the temporal behaviour of the application by embedding worst case resource availability curves in the symbolic simulation of the application graph. Symbolic simulation of the application results in a (max, +) characterization matrix. This matrix specifies a set of recursive linear equations in (max, +) algebra that bound the worst case execution of the application. We obtain tighter temporal bounds on the completion times of tasks than state of the art analysis. This is achieved by improving the response times of the tasks by identifying possible consecutive task executions on the resources. This enables us to use accumulated response times which are less pessimistic. Applying the new approach to real-life applications gives significant improvements over the bounds compared to state of the art.
{"title":"Tight temporal bounds for dataflow applications mapped onto shared resources","authors":"Hadi Alizadeh Ara, M. Geilen, T. Basten, A. Behrouzian, M. Hendriks, Dip Goswami","doi":"10.1109/SIES.2016.7509444","DOIUrl":"https://doi.org/10.1109/SIES.2016.7509444","url":null,"abstract":"We present an analysis method that provides tight temporal bounds for applications modeled by Synchronous Dataflow Graphs and mapped to shared resources. We consider the resource sharing effects on the temporal behaviour of the application by embedding worst case resource availability curves in the symbolic simulation of the application graph. Symbolic simulation of the application results in a (max, +) characterization matrix. This matrix specifies a set of recursive linear equations in (max, +) algebra that bound the worst case execution of the application. We obtain tighter temporal bounds on the completion times of tasks than state of the art analysis. This is achieved by improving the response times of the tasks by identifying possible consecutive task executions on the resources. This enables us to use accumulated response times which are less pessimistic. Applying the new approach to real-life applications gives significant improvements over the bounds compared to state of the art.","PeriodicalId":185636,"journal":{"name":"2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)","volume":"386 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121244726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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