Pub Date : 2022-12-02DOI: 10.1109/UPCON56432.2022.9986362
M. L. S. S. Kumar, Kiran Teeparthi, Sreenadh Batchu
Transient stability constrained optimal power flow (TSC-OPF) is a well known problem in the literature. Several nu-merical based and heuristic based approaches have been applied to solve this problem so far. In the literature, it is shown that meta heuristic-population based methods are fast and effective in handling this problem. This paper proposes a heuristic method based workflow known as, search space reduction algorithm (SSRA) based workflow to solve the TSC-OPF problem. The SSRA based TSC-OPF solution make changes in active power generations of the generators in the power system such that both the goals, system economy of operation and stability requirements are reconciled, satisfying both the static and dynamic constraints. The proposed method is tested on 10 machine 39 bus system and results indicates that the proposed approach has capability to explore and exploit efficiently, the search range to reach a near global optimal point. The results are compared with different evolutionary algorithms like PSO and GWO, and the comparison results shows that the proposed method achieves more near global optimum compared with its counterparts. Further, the effect of the algorithm tuning parameters on its convergence characteristics has also been investigated in a systematic manner.
{"title":"A Search Space Reduction Algorithm Applied for Transient Stability Constrained Optimal Power Flow","authors":"M. L. S. S. Kumar, Kiran Teeparthi, Sreenadh Batchu","doi":"10.1109/UPCON56432.2022.9986362","DOIUrl":"https://doi.org/10.1109/UPCON56432.2022.9986362","url":null,"abstract":"Transient stability constrained optimal power flow (TSC-OPF) is a well known problem in the literature. Several nu-merical based and heuristic based approaches have been applied to solve this problem so far. In the literature, it is shown that meta heuristic-population based methods are fast and effective in handling this problem. This paper proposes a heuristic method based workflow known as, search space reduction algorithm (SSRA) based workflow to solve the TSC-OPF problem. The SSRA based TSC-OPF solution make changes in active power generations of the generators in the power system such that both the goals, system economy of operation and stability requirements are reconciled, satisfying both the static and dynamic constraints. The proposed method is tested on 10 machine 39 bus system and results indicates that the proposed approach has capability to explore and exploit efficiently, the search range to reach a near global optimal point. The results are compared with different evolutionary algorithms like PSO and GWO, and the comparison results shows that the proposed method achieves more near global optimum compared with its counterparts. Further, the effect of the algorithm tuning parameters on its convergence characteristics has also been investigated in a systematic manner.","PeriodicalId":185782,"journal":{"name":"2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126696136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-02DOI: 10.1109/UPCON56432.2022.9986363
Buddhi Prakash Sharma, Anu Gupta, C. Shekhar
The regenerative latch comparator prototype for high-speed up to 1 Giga Hertz analog-to-digital conversion is shown in this article. Cascading structure of different modules makes the proposed comparator a suitable choice for various converters like SAR, Pipelined, Flash, etc. The proposed comparator achieves efficiency in terms of propagation latency, power consumption, and area as compared to the present state of the art mentioned in this work. Additionally, it uses the cadence schematic editor tool to illustrate how the performance of a comparator changes depending on its common-mode voltage (Vcm) and input (Vid) on TSMC 180 nm CMOS technology.
{"title":"Design & Analysis of Performance-efficient Comparator for IoT Application","authors":"Buddhi Prakash Sharma, Anu Gupta, C. Shekhar","doi":"10.1109/UPCON56432.2022.9986363","DOIUrl":"https://doi.org/10.1109/UPCON56432.2022.9986363","url":null,"abstract":"The regenerative latch comparator prototype for high-speed up to 1 Giga Hertz analog-to-digital conversion is shown in this article. Cascading structure of different modules makes the proposed comparator a suitable choice for various converters like SAR, Pipelined, Flash, etc. The proposed comparator achieves efficiency in terms of propagation latency, power consumption, and area as compared to the present state of the art mentioned in this work. Additionally, it uses the cadence schematic editor tool to illustrate how the performance of a comparator changes depending on its common-mode voltage (Vcm) and input (Vid) on TSMC 180 nm CMOS technology.","PeriodicalId":185782,"journal":{"name":"2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124395816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-02DOI: 10.1109/UPCON56432.2022.9986367
Arun Singh Bhadwal, K. Kumar
Molecule generation refers to the process of designing new chemicals with certain chemical properties and then optimising these properties. Following prior research, we encode chemicals as continuous vectors and decode the embedding vectors back into molecules using the variational autoencoder architecture. The encoder and decoder of the proposed variational atoencoder are based on gated recurrent unit cells. The gated recurrent unit cells limit the amount of learnable parameters in the variational autoencoder. The variational autoencoder based on gated recurrent units provides validity of 92.32 % and reconstruction accuracy of 89.63% percent, which is superior to other state-of-the-art techniques. The proposed model is effective in generating compounds with diverse properties.
{"title":"GVA: Gated Variational Autoencoder for de novo molecule generation","authors":"Arun Singh Bhadwal, K. Kumar","doi":"10.1109/UPCON56432.2022.9986367","DOIUrl":"https://doi.org/10.1109/UPCON56432.2022.9986367","url":null,"abstract":"Molecule generation refers to the process of designing new chemicals with certain chemical properties and then optimising these properties. Following prior research, we encode chemicals as continuous vectors and decode the embedding vectors back into molecules using the variational autoencoder architecture. The encoder and decoder of the proposed variational atoencoder are based on gated recurrent unit cells. The gated recurrent unit cells limit the amount of learnable parameters in the variational autoencoder. The variational autoencoder based on gated recurrent units provides validity of 92.32 % and reconstruction accuracy of 89.63% percent, which is superior to other state-of-the-art techniques. The proposed model is effective in generating compounds with diverse properties.","PeriodicalId":185782,"journal":{"name":"2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122467020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-02DOI: 10.1109/UPCON56432.2022.9986485
A. Verma, V. Patel, Dipayan Guha
This paper has attempted to assess the effectiveness of a disturbance observer-based fractional-order sliding mode controller applied to a nonlinear magnetic levitation system. The performance of the designed robust controller has been assessed considering parametric uncertainty and exogenous system disturbances. The main motivation for introducing fractional-order calculus and disturbance observer is to mitigate the problem of chattering in the control input. The presented result of the simulation shows the mastery of the suggested robust controller in coping with unknown/uncertain system disturbances. Moreover, improvement in chattering at the output of the controller is also considerably attenuated with the augmentation of the proposed scheme.
{"title":"Disturbance Observer-based Resilient Controller for Nonlinear Maglev System","authors":"A. Verma, V. Patel, Dipayan Guha","doi":"10.1109/UPCON56432.2022.9986485","DOIUrl":"https://doi.org/10.1109/UPCON56432.2022.9986485","url":null,"abstract":"This paper has attempted to assess the effectiveness of a disturbance observer-based fractional-order sliding mode controller applied to a nonlinear magnetic levitation system. The performance of the designed robust controller has been assessed considering parametric uncertainty and exogenous system disturbances. The main motivation for introducing fractional-order calculus and disturbance observer is to mitigate the problem of chattering in the control input. The presented result of the simulation shows the mastery of the suggested robust controller in coping with unknown/uncertain system disturbances. Moreover, improvement in chattering at the output of the controller is also considerably attenuated with the augmentation of the proposed scheme.","PeriodicalId":185782,"journal":{"name":"2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126302393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-02DOI: 10.1109/UPCON56432.2022.9986423
Mohammad Zaid, A. Pampori, Y. Chauhan
In this paper, we propose a 16W S-Band Power Amplifier using coupler based design. The design procedure involves the use of power splitting and combining in order to achieve high power of operation. The power amplifier has a measured gain of 14.37 dB at 2.6 GHz, an output power of 42 dBm, and a measured Power Added Efficiency (PAE) of 48.7%. In terms of linearity, the circuit has a measured Output 1-dB compression point OP1dB of 34 dBm and an output Third Order Intercept (OIP3) value of 44.8 dBm.
{"title":"16 Watt S-Band GaN Based Power Amplifier Using Replicating Stages","authors":"Mohammad Zaid, A. Pampori, Y. Chauhan","doi":"10.1109/UPCON56432.2022.9986423","DOIUrl":"https://doi.org/10.1109/UPCON56432.2022.9986423","url":null,"abstract":"In this paper, we propose a 16W S-Band Power Amplifier using coupler based design. The design procedure involves the use of power splitting and combining in order to achieve high power of operation. The power amplifier has a measured gain of 14.37 dB at 2.6 GHz, an output power of 42 dBm, and a measured Power Added Efficiency (PAE) of 48.7%. In terms of linearity, the circuit has a measured Output 1-dB compression point OP1dB of 34 dBm and an output Third Order Intercept (OIP3) value of 44.8 dBm.","PeriodicalId":185782,"journal":{"name":"2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124645238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-02DOI: 10.1109/UPCON56432.2022.9986413
Prateek Kumar Mishra, P. Behera, M. Pattnaik
Nowadays, multilevel inverters (MLIs) are receiving profound attention to cater the power requirements of industry 4.0. In this context, newer MLI topologies are being explored as well as proposed with reduced component counts to attain higher levels of output voltage. In this context, this article illustrates the comparative analysis of sinusoidal pulse width modulation (SPWM) with two different carrier wave and low frequency modulation (LFM) for a 3-phase symmetrical modular multilevel inverter (M-MLI) with reduced component counts. Since, this topography is uncomplicated and modular, it could be extended to several levels by rising the number of cells. The M-MLI topology having 3-levels in each pole with a single fundamental cell in each phase is simulated in MATLAB/Simulink. The %THD of M-MLI using LFM scheme is found less compared to other two techniques which are demonstrated through FFT analysis.
{"title":"Comparative Evaluation and Analysis of Different Switching Schemes for a Three-Phase Symmetrical Multilevel Inverter with Reduced Switch Count","authors":"Prateek Kumar Mishra, P. Behera, M. Pattnaik","doi":"10.1109/UPCON56432.2022.9986413","DOIUrl":"https://doi.org/10.1109/UPCON56432.2022.9986413","url":null,"abstract":"Nowadays, multilevel inverters (MLIs) are receiving profound attention to cater the power requirements of industry 4.0. In this context, newer MLI topologies are being explored as well as proposed with reduced component counts to attain higher levels of output voltage. In this context, this article illustrates the comparative analysis of sinusoidal pulse width modulation (SPWM) with two different carrier wave and low frequency modulation (LFM) for a 3-phase symmetrical modular multilevel inverter (M-MLI) with reduced component counts. Since, this topography is uncomplicated and modular, it could be extended to several levels by rising the number of cells. The M-MLI topology having 3-levels in each pole with a single fundamental cell in each phase is simulated in MATLAB/Simulink. The %THD of M-MLI using LFM scheme is found less compared to other two techniques which are demonstrated through FFT analysis.","PeriodicalId":185782,"journal":{"name":"2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128401698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-02DOI: 10.1109/UPCON56432.2022.9986448
Onkar S. Joshi, Amit D. Joshi, S. Sawant
Magnetic Resonance Imaging is often used in medical imaging techniques. The particular magnetic resonance imaging needs to be clear and sharp for precise and effective medical diagnosis. The image quality can be severely harmed by a slight movement in the muscle or the intended area. It is difficult to obtain high-quality scans due to hardware limitations and health risks associated with magnetic resonance imaging radiation. The existing research has shown that the generative adversarial network approach with deep neural networks gives impressive results compared to traditional approaches such as bicubic interpolation. In the proposed methodology, generative adversarial networks is used to improve the resolution and quality of the magnetic resonance imaging. The proposed architecture converts the low-resolution image input to high-resolution image output. Two different neural networks are used in the generative adversarial network i. e., the discriminator and the generator. These two architecture compete against one another to enhance the final output. The high-resolution results are generated by a generator, and the generator's performance is improved by a discriminator.
{"title":"Enhancing Two Dimensional Magnetic Resonance Image Using Generative Adversarial Network","authors":"Onkar S. Joshi, Amit D. Joshi, S. Sawant","doi":"10.1109/UPCON56432.2022.9986448","DOIUrl":"https://doi.org/10.1109/UPCON56432.2022.9986448","url":null,"abstract":"Magnetic Resonance Imaging is often used in medical imaging techniques. The particular magnetic resonance imaging needs to be clear and sharp for precise and effective medical diagnosis. The image quality can be severely harmed by a slight movement in the muscle or the intended area. It is difficult to obtain high-quality scans due to hardware limitations and health risks associated with magnetic resonance imaging radiation. The existing research has shown that the generative adversarial network approach with deep neural networks gives impressive results compared to traditional approaches such as bicubic interpolation. In the proposed methodology, generative adversarial networks is used to improve the resolution and quality of the magnetic resonance imaging. The proposed architecture converts the low-resolution image input to high-resolution image output. Two different neural networks are used in the generative adversarial network i. e., the discriminator and the generator. These two architecture compete against one another to enhance the final output. The high-resolution results are generated by a generator, and the generator's performance is improved by a discriminator.","PeriodicalId":185782,"journal":{"name":"2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130323990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-02DOI: 10.1109/UPCON56432.2022.9986371
C. M, Savitha P B
Electric vehicles (EV's) are the promising technology of today's world. Electric vehicles use battery as the primary source of input and batteries are controlled by the help of DC-DC converters. Hence the DC-DC converter modeling and simulation plays a vital role in understanding its dynamics. In this paper, mathematical modeling of a non-ideal asynchornus buck boost converter is modeled using the basic equations of volt-sec and amp-sec balance. The transfer functions of constant voltage $frac{widehat{mathrm{v}_{0}}}{hat{mathrm{d}}}$ for non - ideal asynchronous and synchronous converters are also modeled using State Space averaging (SSA) technique and analyzed using MATLAB software. To validate the obtained Gvd Generalized Circuit averaging technique is used with LTspice simulation tool. Gvd obtained from different control techniques were found to be similar. However, a small variation is found in LT-Spice tool.
{"title":"Average Current Control of Buck-Boost Converter","authors":"C. M, Savitha P B","doi":"10.1109/UPCON56432.2022.9986371","DOIUrl":"https://doi.org/10.1109/UPCON56432.2022.9986371","url":null,"abstract":"Electric vehicles (EV's) are the promising technology of today's world. Electric vehicles use battery as the primary source of input and batteries are controlled by the help of DC-DC converters. Hence the DC-DC converter modeling and simulation plays a vital role in understanding its dynamics. In this paper, mathematical modeling of a non-ideal asynchornus buck boost converter is modeled using the basic equations of volt-sec and amp-sec balance. The transfer functions of constant voltage $frac{widehat{mathrm{v}_{0}}}{hat{mathrm{d}}}$ for non - ideal asynchronous and synchronous converters are also modeled using State Space averaging (SSA) technique and analyzed using MATLAB software. To validate the obtained Gvd Generalized Circuit averaging technique is used with LTspice simulation tool. Gvd obtained from different control techniques were found to be similar. However, a small variation is found in LT-Spice tool.","PeriodicalId":185782,"journal":{"name":"2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130845201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-02DOI: 10.1109/UPCON56432.2022.9986375
Sudhanshu Rawat, M. Biswas
We have proposed a method based on the heat method for computing geodesic distance on triangular meshes. The heat method is a very efficient and robust method for computing geodesics on many surfaces. The heat method develops a vector unit field having a gradient the same as that of the distance function and integrates this vector field over the surface by solving a Poisson equation which is required to solve two linear sparse equations. The original heat method uses the direct method to solve those linear equations. The proposed method uses a solver consisting of the algebraic multigrid preconditioned conjugate gradient for solving the linear equations to get the geodesic distance. We observed that using an iterative solver reduces the memory footprint and gives us the option to trade-off between performance and accuracy. The result shows that the proposed method needs less time to compute the geodesic distance for bigger mesh and has significantly reduced memory usage for considered mesh data.
{"title":"Enhanced Heat Method for Computation of Geodesic Distance on Triangular Meshes","authors":"Sudhanshu Rawat, M. Biswas","doi":"10.1109/UPCON56432.2022.9986375","DOIUrl":"https://doi.org/10.1109/UPCON56432.2022.9986375","url":null,"abstract":"We have proposed a method based on the heat method for computing geodesic distance on triangular meshes. The heat method is a very efficient and robust method for computing geodesics on many surfaces. The heat method develops a vector unit field having a gradient the same as that of the distance function and integrates this vector field over the surface by solving a Poisson equation which is required to solve two linear sparse equations. The original heat method uses the direct method to solve those linear equations. The proposed method uses a solver consisting of the algebraic multigrid preconditioned conjugate gradient for solving the linear equations to get the geodesic distance. We observed that using an iterative solver reduces the memory footprint and gives us the option to trade-off between performance and accuracy. The result shows that the proposed method needs less time to compute the geodesic distance for bigger mesh and has significantly reduced memory usage for considered mesh data.","PeriodicalId":185782,"journal":{"name":"2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133289127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-02DOI: 10.1109/UPCON56432.2022.10005845
Mohammad Zaid, A. Pampori, R. Dangi, Y. Singh Chauhan
In this letter, we propose an S-Band Power Amplifier based on a symmetric matching network using 10 W CREE GaN devices at 2.6 GHz. The design procedure focuses on choosing the source and load impedances close to each other, so that the matching networks at both the input and the output are symmetric. The advantage of this technique is that the output matching network remains unchanged once the input matching network is implemented. The power amplifier has a measured gain of 15.4 dB at 2.6 GHz, an output power of 38.1 dBm and a measured Power Added Efficiency (PAE) of 46.7 %. The design provides decent linearity with an Output 1-dB compression point (OP1dB) of 31.7 dBm and a Third Order Intercept (TOI) point of 40.8 dBm.
在这封信中，我们提出了一个基于对称匹配网络的s波段功率放大器，使用2.6 GHz的10 W CREE GaN器件。设计过程侧重于选择源阻抗和负载阻抗相互接近，使输入和输出处的匹配网络都是对称的。该技术的优点是，一旦实现了输入匹配网络，输出匹配网络保持不变。该功率放大器在2.6 GHz时的测量增益为15.4 dB，输出功率为38.1 dBm，测量功率附加效率(PAE)为46.7%。该设计提供了良好的线性度，输出1-dB压缩点(OP1dB)为31.7 dBm，三阶截距(TOI)点为40.8 dBm。
{"title":"S-Band GaN based Power Amplifier with Symmetric Matching Network","authors":"Mohammad Zaid, A. Pampori, R. Dangi, Y. Singh Chauhan","doi":"10.1109/UPCON56432.2022.10005845","DOIUrl":"https://doi.org/10.1109/UPCON56432.2022.10005845","url":null,"abstract":"In this letter, we propose an S-Band Power Amplifier based on a symmetric matching network using 10 W CREE GaN devices at 2.6 GHz. The design procedure focuses on choosing the source and load impedances close to each other, so that the matching networks at both the input and the output are symmetric. The advantage of this technique is that the output matching network remains unchanged once the input matching network is implemented. The power amplifier has a measured gain of 15.4 dB at 2.6 GHz, an output power of 38.1 dBm and a measured Power Added Efficiency (PAE) of 46.7 %. The design provides decent linearity with an Output 1-dB compression point (OP1dB) of 31.7 dBm and a Third Order Intercept (TOI) point of 40.8 dBm.","PeriodicalId":185782,"journal":{"name":"2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116790302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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