In this paper we propose a new Tabu Search-based design optimization strategy for mixed-criticality systems implementing hard and soft real-time applications on the same platform. Our proposed strategy determined an implementation such that all hard real-time applications are schedulable and the quality of service of the soft real-time tasks is maximized. We have evaluated our strategy using an aerospace case study.
{"title":"Optimization of Partitioned Architectures to Support Soft Real-Time Applications","authors":"D. Tamas-Selicean, P. Pop","doi":"10.1109/PRDC.2014.36","DOIUrl":"https://doi.org/10.1109/PRDC.2014.36","url":null,"abstract":"In this paper we propose a new Tabu Search-based design optimization strategy for mixed-criticality systems implementing hard and soft real-time applications on the same platform. Our proposed strategy determined an implementation such that all hard real-time applications are schedulable and the quality of service of the soft real-time tasks is maximized. We have evaluated our strategy using an aerospace case study.","PeriodicalId":187000,"journal":{"name":"2014 IEEE 20th Pacific Rim International Symposium on Dependable Computing","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122647407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Since analytical software reliability growth models (SRGMs) are difficult to incorporate complex factors, some researchers have tried to model fault detection process (FDP) and fault correction process (FCP) together through simulation approaches. In these works, the debuggers are assumed to be with the same skill level, which may be unrealistic. In this paper, a simulation approach is proposed to model FDP and FCP considering debuggers with different skill levels. The optimal combination of different debuggers and the optimal release time are discussed.
{"title":"Simulation of Software Fault Detection and Correction Processes Considering Different Skill Levels of Debuggers","authors":"R. Peng, F. R. Shahrzad","doi":"10.1109/PRDC.2014.27","DOIUrl":"https://doi.org/10.1109/PRDC.2014.27","url":null,"abstract":"Since analytical software reliability growth models (SRGMs) are difficult to incorporate complex factors, some researchers have tried to model fault detection process (FDP) and fault correction process (FCP) together through simulation approaches. In these works, the debuggers are assumed to be with the same skill level, which may be unrealistic. In this paper, a simulation approach is proposed to model FDP and FCP considering debuggers with different skill levels. The optimal combination of different debuggers and the optimal release time are discussed.","PeriodicalId":187000,"journal":{"name":"2014 IEEE 20th Pacific Rim International Symposium on Dependable Computing","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121905614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Software engineering researchers have extensively explored the reuse of components at source-code level. Contracts explicitly describe component behaviour, reducing development risk by exposing potential incompatibilities early in the development process. But to benefit fully from reuse, developers of safety-critical systems must also reuse safety evidence. Full reuse would require both extending the existing notion of component contracts to cover safety properties and using these contracts in both component selection and system certification. This is not as simple as it first appears. Much of the review, analysis, and test evidence developers provide during certification is system-specific. This makes it difficult to define safety contracts that facilitate both selecting components to reuse and certifying systems. In this paper, we explore the definition and use of safety contracts, identify challenges to component-based software reuse safety-critical systems, present examples to illustrate several key difficulties, and discuss potential solutions to these problems.
{"title":"The Nature and Content of Safety Contracts: Challenges and Suggestions for a Way Forward","authors":"P. Graydon, I. Bate","doi":"10.1109/PRDC.2014.24","DOIUrl":"https://doi.org/10.1109/PRDC.2014.24","url":null,"abstract":"Software engineering researchers have extensively explored the reuse of components at source-code level. Contracts explicitly describe component behaviour, reducing development risk by exposing potential incompatibilities early in the development process. But to benefit fully from reuse, developers of safety-critical systems must also reuse safety evidence. Full reuse would require both extending the existing notion of component contracts to cover safety properties and using these contracts in both component selection and system certification. This is not as simple as it first appears. Much of the review, analysis, and test evidence developers provide during certification is system-specific. This makes it difficult to define safety contracts that facilitate both selecting components to reuse and certifying systems. In this paper, we explore the definition and use of safety contracts, identify challenges to component-based software reuse safety-critical systems, present examples to illustrate several key difficulties, and discuss potential solutions to these problems.","PeriodicalId":187000,"journal":{"name":"2014 IEEE 20th Pacific Rim International Symposium on Dependable Computing","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121304214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Kono, Shunsuke Miyahara, H. Yamada, Takeshi Yoshimura
Enhancing source code quality of operating systems (OSes) is an essential and endless task in communities of commodity OSes. Unfortunately, improving the quality of the kernel code is not trivial because the kernel is large and complex. In particular, asynchronous events from peripheral devices such as interrupts make the improvement quite hard due to their low reproducibility. This paper presents Foxy Feed, a mechanism based on virtual machine monitors that helps to fix bugs caused by asynchronous device-level events. Foxy Feed forges device-level events and injects them to a debuggee kernel at the timing specified in advance, and allows us to control the timing at which asynchronous events occur for the debugging purpose. Using our prototype implementation of Foxy Feed, which is based on Xen 4.1.0, we demonstrate that Foxy Feed reproduces failures caused by device-triggered bugs in Linux and gives significant clues to the root causes.
{"title":"FoxyFeed: Forging Device-Level Asynchronous Events for Kernel Development","authors":"K. Kono, Shunsuke Miyahara, H. Yamada, Takeshi Yoshimura","doi":"10.1109/PRDC.2014.25","DOIUrl":"https://doi.org/10.1109/PRDC.2014.25","url":null,"abstract":"Enhancing source code quality of operating systems (OSes) is an essential and endless task in communities of commodity OSes. Unfortunately, improving the quality of the kernel code is not trivial because the kernel is large and complex. In particular, asynchronous events from peripheral devices such as interrupts make the improvement quite hard due to their low reproducibility. This paper presents Foxy Feed, a mechanism based on virtual machine monitors that helps to fix bugs caused by asynchronous device-level events. Foxy Feed forges device-level events and injects them to a debuggee kernel at the timing specified in advance, and allows us to control the timing at which asynchronous events occur for the debugging purpose. Using our prototype implementation of Foxy Feed, which is based on Xen 4.1.0, we demonstrate that Foxy Feed reproduces failures caused by device-triggered bugs in Linux and gives significant clues to the root causes.","PeriodicalId":187000,"journal":{"name":"2014 IEEE 20th Pacific Rim International Symposium on Dependable Computing","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124338218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yasuo Sato, M. Monden, Yousuke Miyake, S. Kajihara
Ring Oscillators are used for variety of purposes to enhance reliability on LSIs or FPGAs. This paper introduces an aging-tolerant design structure of ring oscillators that are used in FPGAs. The structure is able to reduce NBTI-induced degradation in a ring oscillator's frequency by setting PMOS transistors of look-up tables in an off-state when the oscillator is not working. The evaluation of a variety of ring oscillators using Altera Cyclone IV device (60nm technology) shows that the proposed structure is capable of controlling degradation level as well as reducing more than 37% performance degradation compared to the conventional oscillators.
{"title":"Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA","authors":"Yasuo Sato, M. Monden, Yousuke Miyake, S. Kajihara","doi":"10.1109/PRDC.2014.16","DOIUrl":"https://doi.org/10.1109/PRDC.2014.16","url":null,"abstract":"Ring Oscillators are used for variety of purposes to enhance reliability on LSIs or FPGAs. This paper introduces an aging-tolerant design structure of ring oscillators that are used in FPGAs. The structure is able to reduce NBTI-induced degradation in a ring oscillator's frequency by setting PMOS transistors of look-up tables in an off-state when the oscillator is not working. The evaluation of a variety of ring oscillators using Altera Cyclone IV device (60nm technology) shows that the proposed structure is capable of controlling degradation level as well as reducing more than 37% performance degradation compared to the conventional oscillators.","PeriodicalId":187000,"journal":{"name":"2014 IEEE 20th Pacific Rim International Symposium on Dependable Computing","volume":"295 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114352262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Iliadis, D. Sotnikov, Paula Ta-Shma, V. Venkatesan
Network bandwidth between sites is typically more scarce than bandwidth within a site in geo-replicated cloud storage systems, and can potentially be a bottleneck for recovery operations. We study the reliability of geo-replicated cloud storage systems taking into account different bandwidths within a site and between sites. We consider a new recovery scheme called staged rebuild and compare it with both a direct scheme and a scheme known as intelligent rebuild. To assess the reliability gains achieved by these schemes, we develop an analytical model that incorporates various relevant aspects of storage systems, such as bandwidths, latent sector errors, and failure distributions. The model applies in the context of Open Stack Swift, a widely deployed cloud storage system. Under certain practical system configurations, we establish that order of magnitude improvements in mean time to data loss (MTTDL) can be achieved using these schemes.
{"title":"Reliability of Geo-replicated Cloud Storage Systems","authors":"I. Iliadis, D. Sotnikov, Paula Ta-Shma, V. Venkatesan","doi":"10.1109/PRDC.2014.30","DOIUrl":"https://doi.org/10.1109/PRDC.2014.30","url":null,"abstract":"Network bandwidth between sites is typically more scarce than bandwidth within a site in geo-replicated cloud storage systems, and can potentially be a bottleneck for recovery operations. We study the reliability of geo-replicated cloud storage systems taking into account different bandwidths within a site and between sites. We consider a new recovery scheme called staged rebuild and compare it with both a direct scheme and a scheme known as intelligent rebuild. To assess the reliability gains achieved by these schemes, we develop an analytical model that incorporates various relevant aspects of storage systems, such as bandwidths, latent sector errors, and failure distributions. The model applies in the context of Open Stack Swift, a widely deployed cloud storage system. Under certain practical system configurations, we establish that order of magnitude improvements in mean time to data loss (MTTDL) can be achieved using these schemes.","PeriodicalId":187000,"journal":{"name":"2014 IEEE 20th Pacific Rim International Symposium on Dependable Computing","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121812775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dominant error sources in multi-level cell NAND Flash memories shift threshold voltage levels to either positive or negative values, thus errors are modeled by nonbinary unidirectional channels. However, bidirectional errors can also be caused when positive and negative errors have equivalent significance. Compared to unidirectional cases, error magnitude of bidirectional errors are considered to be small. In this correspondence, novel error correcting codes which correct limited magnitude asymmetric/unidirectional errors along with bidirectional errors of relatively small magnitude are presented. They can be used to reduce encoding and decoding complexity compared to conventional symmetric error correcting codes.
{"title":"Codes Correcting Asymmetric/Unidirectional Errors along with Bidirectional Errors of Small Magnitude","authors":"Shohei Kotaki, M. Kitakami","doi":"10.1109/PRDC.2014.28","DOIUrl":"https://doi.org/10.1109/PRDC.2014.28","url":null,"abstract":"Dominant error sources in multi-level cell NAND Flash memories shift threshold voltage levels to either positive or negative values, thus errors are modeled by nonbinary unidirectional channels. However, bidirectional errors can also be caused when positive and negative errors have equivalent significance. Compared to unidirectional cases, error magnitude of bidirectional errors are considered to be small. In this correspondence, novel error correcting codes which correct limited magnitude asymmetric/unidirectional errors along with bidirectional errors of relatively small magnitude are presented. They can be used to reduce encoding and decoding complexity compared to conventional symmetric error correcting codes.","PeriodicalId":187000,"journal":{"name":"2014 IEEE 20th Pacific Rim International Symposium on Dependable Computing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131129787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A distributed algorithm, run by distributed processes, satisfies mutual exclusion if at most one process is granted a privilege to access the critical section in each execution step (safety), and each process is privileged infinitely often in each execution (fairness). The design of mutual exclusion algorithms is, in particular, impacted to satisfy the fairness property. In this work, we focus on a class of synchronous systems, where processes rarely request a privilege, that the fairness property is satisfied anyway if the process selection is fast enough. We also consider that systems of this class have to satisfy self-stabilization, which ensures that a system eventually achieves its desired behavior, and does not leave it voluntarily, regardless of the system's initial behavior. We present a self-stabilizing synchronous Propagation of Information with Feedback (PIF) algorithm for trees. The algorithm exploits the synchronous environment to provide immediate feedback of requesting processes, which in turn guarantees fast selection of unique processes to be granted privileges.
{"title":"Exploiting Synchronicity for Immediate Feedback in Self-Stabilizing PIF Algorithms","authors":"Oday Jubran, Oliver E. Theel","doi":"10.1109/PRDC.2014.21","DOIUrl":"https://doi.org/10.1109/PRDC.2014.21","url":null,"abstract":"A distributed algorithm, run by distributed processes, satisfies mutual exclusion if at most one process is granted a privilege to access the critical section in each execution step (safety), and each process is privileged infinitely often in each execution (fairness). The design of mutual exclusion algorithms is, in particular, impacted to satisfy the fairness property. In this work, we focus on a class of synchronous systems, where processes rarely request a privilege, that the fairness property is satisfied anyway if the process selection is fast enough. We also consider that systems of this class have to satisfy self-stabilization, which ensures that a system eventually achieves its desired behavior, and does not leave it voluntarily, regardless of the system's initial behavior. We present a self-stabilizing synchronous Propagation of Information with Feedback (PIF) algorithm for trees. The algorithm exploits the synchronous environment to provide immediate feedback of requesting processes, which in turn guarantees fast selection of unique processes to be granted privileges.","PeriodicalId":187000,"journal":{"name":"2014 IEEE 20th Pacific Rim International Symposium on Dependable Computing","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121818280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper discusses parallel algorithms for transient analysis of continuous-time Markov chains (CTMCs). In dependable computing, it is used for evaluating the rare events such as failure based on CTMC models. The uniformizaton is a well-known algorithm for obtaining the transient solution of CTMC. However, the computation cost of uniformization is not low in the case of large-sized and stiff CTMCs. This paper considers parallelization of the uniformization algorithm. Particularly, we propose a coarse-grained parallel uniformization which is appropriate for multicore processors. This method enables us to analyze the large-sized and stiff CTMCs efficiently. In numerical examples, we examine the effectiveness of the proposed parallel algorithms with multicore processors.
{"title":"Coarse-Grained Parallel Uniformization for Continuous-Time Markov Chains","authors":"H. Okamura, Y. Kunimoto, T. Dohi","doi":"10.1109/PRDC.2014.22","DOIUrl":"https://doi.org/10.1109/PRDC.2014.22","url":null,"abstract":"This paper discusses parallel algorithms for transient analysis of continuous-time Markov chains (CTMCs). In dependable computing, it is used for evaluating the rare events such as failure based on CTMC models. The uniformizaton is a well-known algorithm for obtaining the transient solution of CTMC. However, the computation cost of uniformization is not low in the case of large-sized and stiff CTMCs. This paper considers parallelization of the uniformization algorithm. Particularly, we propose a coarse-grained parallel uniformization which is appropriate for multicore processors. This method enables us to analyze the large-sized and stiff CTMCs efficiently. In numerical examples, we examine the effectiveness of the proposed parallel algorithms with multicore processors.","PeriodicalId":187000,"journal":{"name":"2014 IEEE 20th Pacific Rim International Symposium on Dependable Computing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130485854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Intrusion detection system (IDS) offloading is useful for securely executing IDSes. It runs a target system in a virtual machine (VM) and enables IDSes to monitor the VM from the outside using VM introspection. Although VM introspection is well studied, its performance has not been reported in detail. The performance becomes important when users choose virtualization software, e.g., Xen and KVM. However, the performance comparison is difficult because there is no efficient implementation of VM introspection in KVM. In this paper, we first propose KVMonitor for efficient VM introspection in KVM. Using KVMonitor, we have ported Transcall for offloading legacy IDSes. For memory introspection, KVMonitor was 32 times faster than the existing LibVMI. Then we present performance comparison between Xen and KVM on VM introspection. The experimental results showed that checking the kernel memory with KVMonitor was 118 times faster than that in Xen. Even for legacy chkrootkit, the execution time with KVMonitor was 63% shorter than that in Xen.
{"title":"Efficient VM Introspection in KVM and Performance Comparison with Xen","authors":"Kenichi Kourai, Kousuke Nakamura","doi":"10.1109/PRDC.2014.33","DOIUrl":"https://doi.org/10.1109/PRDC.2014.33","url":null,"abstract":"Intrusion detection system (IDS) offloading is useful for securely executing IDSes. It runs a target system in a virtual machine (VM) and enables IDSes to monitor the VM from the outside using VM introspection. Although VM introspection is well studied, its performance has not been reported in detail. The performance becomes important when users choose virtualization software, e.g., Xen and KVM. However, the performance comparison is difficult because there is no efficient implementation of VM introspection in KVM. In this paper, we first propose KVMonitor for efficient VM introspection in KVM. Using KVMonitor, we have ported Transcall for offloading legacy IDSes. For memory introspection, KVMonitor was 32 times faster than the existing LibVMI. Then we present performance comparison between Xen and KVM on VM introspection. The experimental results showed that checking the kernel memory with KVMonitor was 118 times faster than that in Xen. Even for legacy chkrootkit, the execution time with KVMonitor was 63% shorter than that in Xen.","PeriodicalId":187000,"journal":{"name":"2014 IEEE 20th Pacific Rim International Symposium on Dependable Computing","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133961258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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