Digital sub-threshold logic circuits have recently been proposed for applications in the ultra-low power end of the design spectrum, where the performance is of secondary importance. To improve switching performance of the sub-threshold logic family with comparable energy/switching, we propose the use of sub-DTMOS (sub-threshold Dynamic Threshold MOS) transistors. The stability of sub-threshold DTMOS logic to temperature and process variations eliminates the need of additional stabilization scheme that may be required for regular sub-threshold MOS logic families to ensure proper operation in the sub-threshold region.
{"title":"Robust ultra-low power sub-threshold DTMOS logic","authors":"H. Soeleman, K. Roy, B. Paul","doi":"10.1145/344166.344187","DOIUrl":"https://doi.org/10.1145/344166.344187","url":null,"abstract":"Digital sub-threshold logic circuits have recently been proposed for applications in the ultra-low power end of the design spectrum, where the performance is of secondary importance. To improve switching performance of the sub-threshold logic family with comparable energy/switching, we propose the use of sub-DTMOS (sub-threshold Dynamic Threshold MOS) transistors. The stability of sub-threshold DTMOS logic to temperature and process variations eliminates the need of additional stabilization scheme that may be required for regular sub-threshold MOS logic families to ensure proper operation in the sub-threshold region.","PeriodicalId":188020,"journal":{"name":"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121155216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The design of the standard CMOS IC core of a commercial wireless burglar alarm system is presented as an example of a very low-power analog VLSI design for battery-operated systems. The main constraint is battery life, which must be at least five years (with standard camera-battery). The chip is composed of a digital (decision) part and an analog interface with sensors. The entire chip absorbs 10 /spl mu/A. Measures on each single component and test on working environment show full functionality and complied with specifications. Even though the example is application specific, the design solutions and each single element can also be utilized in many other battery-operated low-frequency devices (e.g. environmental parameter monitoring).
{"title":"A micro-power mixed signal IC for battery-operated burglar alarm systems","authors":"Silvio Bolliri, P. Porcu, L. Raffo","doi":"10.1145/344166.344516","DOIUrl":"https://doi.org/10.1145/344166.344516","url":null,"abstract":"The design of the standard CMOS IC core of a commercial wireless burglar alarm system is presented as an example of a very low-power analog VLSI design for battery-operated systems. The main constraint is battery life, which must be at least five years (with standard camera-battery). The chip is composed of a digital (decision) part and an analog interface with sensors. The entire chip absorbs 10 /spl mu/A. Measures on each single component and test on working environment show full functionality and complied with specifications. Even though the example is application specific, the design solutions and each single element can also be utilized in many other battery-operated low-frequency devices (e.g. environmental parameter monitoring).","PeriodicalId":188020,"journal":{"name":"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123379549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Two novel low power flip-flops are presented in the paper. The proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. The presented circuits overcome the clock duty-cycle limitation of previously reported gated flip-flops. Circuit simulations with the inclusion of parasitics show that sensible power dissipation reduction is possible if the input signal has reduced switching activity. A 16-bit counter is presented as a simple low power application.
{"title":"New clock-gating techniques for low-power flip-flops","authors":"A. Strollo, E. Napoli, D. Caro","doi":"10.1145/344166.344540","DOIUrl":"https://doi.org/10.1145/344166.344540","url":null,"abstract":"Two novel low power flip-flops are presented in the paper. The proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. The presented circuits overcome the clock duty-cycle limitation of previously reported gated flip-flops. Circuit simulations with the inclusion of parasitics show that sensible power dissipation reduction is possible if the input signal has reduced switching activity. A 16-bit counter is presented as a simple low power application.","PeriodicalId":188020,"journal":{"name":"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115591331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Various techniques are used to reduce area and power dissipation while speed remains as the main performance criterion for the target application. A parallel transposed direct form architecture operates on real-time input data samples and employs a fast, low-area multiplier based on selection of radix-8 pre-multiplied coefficients in conjunction with one-hot encoded bus leading to a very compact layout and reduced power dissipation. Area, speed and power comparisons with other low-power implementation options are also shown. The proposed filter has been fabricated using a 0.18 /spl mu/m L-effective CMOS technology and operates at 550 MSamples/s.
{"title":"Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels","authors":"K. Muhammad, R. Staszewski, P. Balsara","doi":"10.1145/344166.344623","DOIUrl":"https://doi.org/10.1145/344166.344623","url":null,"abstract":"In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Various techniques are used to reduce area and power dissipation while speed remains as the main performance criterion for the target application. A parallel transposed direct form architecture operates on real-time input data samples and employs a fast, low-area multiplier based on selection of radix-8 pre-multiplied coefficients in conjunction with one-hot encoded bus leading to a very compact layout and reduced power dissipation. Area, speed and power comparisons with other low-power implementation options are also shown. The proposed filter has been fabricated using a 0.18 /spl mu/m L-effective CMOS technology and operates at 550 MSamples/s.","PeriodicalId":188020,"journal":{"name":"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128701482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a framework for CMOS ring oscillator phase noise analysis for given power consumption specifications. This model considers both linear and nonlinear operations. It indicates that fast rail-to-rail switching has to be achieved for low phase noise and that the up-conversion of low-frequency noise from the current bias/control circuit can be significant. Our phase noise model is validated via simulation and measurement results. We also present a coupled-ring oscillator whose phase noise is -114 dBc/Hz at a 600 kHz offset from the 960 MHz carrier frequency.
{"title":"Analysis and design of low-phase-noise ring oscillators","authors":"L. Dai, R. Harjani","doi":"10.1145/344166.344639","DOIUrl":"https://doi.org/10.1145/344166.344639","url":null,"abstract":"This paper presents a framework for CMOS ring oscillator phase noise analysis for given power consumption specifications. This model considers both linear and nonlinear operations. It indicates that fast rail-to-rail switching has to be achieved for low phase noise and that the up-conversion of low-frequency noise from the current bias/control circuit can be significant. Our phase noise model is validated via simulation and measurement results. We also present a coupled-ring oscillator whose phase noise is -114 dBc/Hz at a 600 kHz offset from the 960 MHz carrier frequency.","PeriodicalId":188020,"journal":{"name":"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128726502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In recent years reducing power has become a critical design goal for high-performance microprocessors. This work attempts to bring the power issue to the earliest phase of high-performance microprocessor development. We propose a methodology for power-optimization at the micro-architectural level. First, major targets for power reduction are identified within superscalar microarchitecture, then an optimization of a superscalar micro-architecture is performed that generates a set of energy-efficient configurations forming a convex hull in the power-performance space. The energy-efficient families are then compared to find configurations that dissipate the lowest power given a performance target, or, conversely, deliver the highest performance given a power budget. Application of the developed methodology to a superscalar microarchitecture shows that at the architectural level there is a potential for reducing power up to 50%, given a performance requirement, and for up to 15% performance improvement, given a power budget.
{"title":"Optimization of high-performance superscalar architectures for energy efficiency","authors":"V. Zyuban, P. Kogge","doi":"10.1145/344166.344522","DOIUrl":"https://doi.org/10.1145/344166.344522","url":null,"abstract":"In recent years reducing power has become a critical design goal for high-performance microprocessors. This work attempts to bring the power issue to the earliest phase of high-performance microprocessor development. We propose a methodology for power-optimization at the micro-architectural level. First, major targets for power reduction are identified within superscalar microarchitecture, then an optimization of a superscalar micro-architecture is performed that generates a set of energy-efficient configurations forming a convex hull in the power-performance space. The energy-efficient families are then compared to find configurations that dissipate the lowest power given a performance target, or, conversely, deliver the highest performance given a power budget. Application of the developed methodology to a superscalar microarchitecture shows that at the architectural level there is a potential for reducing power up to 50%, given a performance requirement, and for up to 15% performance improvement, given a power budget.","PeriodicalId":188020,"journal":{"name":"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127628743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we present a completely on-chip voltage regulation technique which promises to adjust the degree of voltage regulation in a digital logic chip in the face of process induced delay variations so as to minimize energy dissipation while always guaranteeing the target operating frequency. For this purpose the delay of a critical path replica of the circuit being regulated is constantly compared with the target delay to provide the regulator with the information needed to select the optimum voltage levels. The proposed solution is even move attractive in that no external components are required. Based on this scheme, a completely on-chip voltage regulator has been fabricated in a commercial 0.5 /spl mu/m CMOS process and used to generate the inner rail voltages for a DSP multiplier-accumulator (MAC) implemented in mixed swing QuadRail. Measured results indicate that the voltages generated by the regulator offer a very high degree of load regulation thus verifying the fast response time of the on-chip output buffer.
{"title":"An adaptive on-chip voltage regulation technique for low-power applications","authors":"Nicola Dragone, A. Aggarwal, L. Carley","doi":"10.1145/344166.344185","DOIUrl":"https://doi.org/10.1145/344166.344185","url":null,"abstract":"In this paper we present a completely on-chip voltage regulation technique which promises to adjust the degree of voltage regulation in a digital logic chip in the face of process induced delay variations so as to minimize energy dissipation while always guaranteeing the target operating frequency. For this purpose the delay of a critical path replica of the circuit being regulated is constantly compared with the target delay to provide the regulator with the information needed to select the optimum voltage levels. The proposed solution is even move attractive in that no external components are required. Based on this scheme, a completely on-chip voltage regulator has been fabricated in a commercial 0.5 /spl mu/m CMOS process and used to generate the inner rail voltages for a DSP multiplier-accumulator (MAC) implemented in mixed swing QuadRail. Measured results indicate that the voltages generated by the regulator offer a very high degree of load regulation thus verifying the fast response time of the on-chip output buffer.","PeriodicalId":188020,"journal":{"name":"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133341276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Micromachined microsystems and micro electromechanical systems (MEMS) have made possible the development of highly accurate and portable sensors and instruments for a variety of applications in health care, industrial, consumer products, avionics, and defense. Design of low-power circuits for these applications, and use of micromachined sensors and actuators in combination with integrated circuits to implement even lower power microinstruments has now become possible and the focus of attention. This paper reviews the state of the art in the development of micromachined microsystems and MEMS, discusses low-power design approaches for microsystems, and reviews some recent development in power generation and energy harvesting from the environment.
{"title":"Low-power micromachined microsystems","authors":"K. Najafi","doi":"10.1145/344166.344176","DOIUrl":"https://doi.org/10.1145/344166.344176","url":null,"abstract":"Micromachined microsystems and micro electromechanical systems (MEMS) have made possible the development of highly accurate and portable sensors and instruments for a variety of applications in health care, industrial, consumer products, avionics, and defense. Design of low-power circuits for these applications, and use of micromachined sensors and actuators in combination with integrated circuits to implement even lower power microinstruments has now become possible and the focus of attention. This paper reviews the state of the art in the development of micromachined microsystems and MEMS, discusses low-power design approaches for microsystems, and reviews some recent development in power generation and energy harvesting from the environment.","PeriodicalId":188020,"journal":{"name":"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123917911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Quality of service (QoS) is one of the key features for new Internet-based multimedia and other applications. Meanwhile, energy remains as a big concern for systems that perform such applications. We address the issue of combining system design concerns and QoS requirements to design systems that can deliver QoS guarantees. In this paper, we discuss how to satisfy QoS requirements and minimize the system's energy consumption. Specifically, we consider the following problem: given a set of applications each specifying its required amount of computation and service time, how we allocate CPU time and determine the voltage profile on a variable voltage system, such that all the applications' requirements are satisfied and the system's total energy consumption is minimized. We optimally solve several basic cases and propose a dynamic programming procedure for the general case. Simulation shows that the new approach saves 38.75% energy over the system shut-down technique.
{"title":"Energy minimization with guaranteed quality of service","authors":"G. Qu, M. Potkonjak","doi":"10.1145/344166.344196","DOIUrl":"https://doi.org/10.1145/344166.344196","url":null,"abstract":"Quality of service (QoS) is one of the key features for new Internet-based multimedia and other applications. Meanwhile, energy remains as a big concern for systems that perform such applications. We address the issue of combining system design concerns and QoS requirements to design systems that can deliver QoS guarantees. In this paper, we discuss how to satisfy QoS requirements and minimize the system's energy consumption. Specifically, we consider the following problem: given a set of applications each specifying its required amount of computation and service time, how we allocate CPU time and determine the voltage profile on a variable voltage system, such that all the applications' requirements are satisfied and the system's total energy consumption is minimized. We optimally solve several basic cases and propose a dynamic programming procedure for the general case. Simulation shows that the new approach saves 38.75% energy over the system shut-down technique.","PeriodicalId":188020,"journal":{"name":"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128404759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We introduce the notion of energy scalable computation on general purpose processors. The principle idea is to maximize computational quality for a given energy constraint. The desirable energy-quality behavior of algorithms is discussed. Subsequently the energy-quality scalability of three distinct categories of commonly used signal processing algorithms (viz. filtering, frequency domain transforms and classification) are analyzed on the StrongARM SA-1100 processor and transformations are described which obtain significant improvements in the energy-quality scalability of the algorithm.
{"title":"Algorithmic transforms for efficient energy scalable computation","authors":"A. Sinha, Alice Wang, A. Chandrakasan","doi":"10.1145/344166.344188","DOIUrl":"https://doi.org/10.1145/344166.344188","url":null,"abstract":"We introduce the notion of energy scalable computation on general purpose processors. The principle idea is to maximize computational quality for a given energy constraint. The desirable energy-quality behavior of algorithms is discussed. Subsequently the energy-quality scalability of three distinct categories of commonly used signal processing algorithms (viz. filtering, frequency domain transforms and classification) are analyzed on the StrongARM SA-1100 processor and transformations are described which obtain significant improvements in the energy-quality scalability of the algorithm.","PeriodicalId":188020,"journal":{"name":"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128481008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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