Pub Date : 1991-06-26DOI: 10.1109/ARITH.1991.145526
J. Duprat, Yvan Herreros, Sylvanus Kla
A new redundant representation for complex numbers, called polygonal representation, is presented. This representation enables fast carry-free addition (in a way quite similar to the carry-free addition in signed-digits number systems), and is convenient for multiplication. In addition, the technique is extended to handle n-dimensional vectors.<>
{"title":"New redundant representations of complex numbers and vectors","authors":"J. Duprat, Yvan Herreros, Sylvanus Kla","doi":"10.1109/ARITH.1991.145526","DOIUrl":"https://doi.org/10.1109/ARITH.1991.145526","url":null,"abstract":"A new redundant representation for complex numbers, called polygonal representation, is presented. This representation enables fast carry-free addition (in a way quite similar to the carry-free addition in signed-digits number systems), and is convenient for multiplication. In addition, the technique is extended to handle n-dimensional vectors.<<ETX>>","PeriodicalId":190650,"journal":{"name":"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124932764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-26DOI: 10.1109/ARITH.1991.145527
F. Chaitin-Chatelin, V. Frayssé
In order to get insight into the perturbations generated by running algorithms on a computer, one may simulate them by random perturbations on the data. For linear systems, it is found that such a statistical estimation gives results which compare favorably with those given by the backward analysis of J.H. Wilkinson (1961) and R.D. Skeel (1979). The objective is to use such a technique mainly for nonlinear problems when no theoretical analysis is available.<>
{"title":"Analysis of arithmetic algorithms: a statistical study","authors":"F. Chaitin-Chatelin, V. Frayssé","doi":"10.1109/ARITH.1991.145527","DOIUrl":"https://doi.org/10.1109/ARITH.1991.145527","url":null,"abstract":"In order to get insight into the perturbations generated by running algorithms on a computer, one may simulate them by random perturbations on the data. For linear systems, it is found that such a statistical estimation gives results which compare favorably with those given by the backward analysis of J.H. Wilkinson (1961) and R.D. Skeel (1979). The objective is to use such a technique mainly for nonlinear problems when no theoretical analysis is available.<<ETX>>","PeriodicalId":190650,"journal":{"name":"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128617729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-26DOI: 10.1109/ARITH.1991.145558
Robert Alverson
By using a reciprocal approximation, integer division can be synthesized from a multiply followed by a shift. Without carefully selecting the reciprocal, however, the quotient obtained often suffers from off-by-one errors, requiring a correction step. The author describes the design decisions made when designing integer division for a new 64-b machine. The result is a fast and economical scheme for computing both unsigned and signed integer quotients which guarantees an exact answer without any correction. The reciprocal computation is fast enough, with one table lookup and five multiplies, so that this scheme is competitive with a dedicated divider, while requiring much less hardware specific to division. The real strength of the proposed method is division by a constant, which takes only a single multiply and shift, one operation on the machine considered. The analysis shows that the computed quotient is always exact: no adjustment or correction is necessary.<>
{"title":"Integer division using reciprocals","authors":"Robert Alverson","doi":"10.1109/ARITH.1991.145558","DOIUrl":"https://doi.org/10.1109/ARITH.1991.145558","url":null,"abstract":"By using a reciprocal approximation, integer division can be synthesized from a multiply followed by a shift. Without carefully selecting the reciprocal, however, the quotient obtained often suffers from off-by-one errors, requiring a correction step. The author describes the design decisions made when designing integer division for a new 64-b machine. The result is a fast and economical scheme for computing both unsigned and signed integer quotients which guarantees an exact answer without any correction. The reciprocal computation is fast enough, with one table lookup and five multiplies, so that this scheme is competitive with a dedicated divider, while requiring much less hardware specific to division. The real strength of the proposed method is division by a constant, which takes only a single multiply and shift, one operation on the machine considered. The analysis shows that the computed quotient is always exact: no adjustment or correction is necessary.<<ETX>>","PeriodicalId":190650,"journal":{"name":"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130611457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-26DOI: 10.1109/ARITH.1991.145534
Dapeng Zhang, G. Jullien, W. Miller, E. Swartzlander
The implementation of large input digital neurons using designs based on parallel counters is described. The implementation of the design uses a two-cell library, in which each cell is implemented using switching trees which are pipelined binary trees of n-channel transistors. Results obtained from initial switching trees realized with a 3- mu m CMOS process indicate that the design is capable of being pipelined at 40 MHz sample rates, with better performance expected for more advanced technologies. It appears feasible to develop a wafer-scale implementation with 2000 neurons (each with 1000 inputs) that would perform 3*10/sup 12/ additions/s.<>
描述了基于并行计数器设计的大输入数字神经元的实现。该设计的实现使用一个双单元库，其中每个单元都使用n通道晶体管的流水线二叉树开关树来实现。用3 μ m CMOS工艺实现的初始开关树的结果表明，该设计能够在40 MHz采样率下流水线化，并有望在更先进的技术中具有更好的性能。开发具有2000个神经元(每个神经元有1000个输入)的晶圆级实现似乎是可行的，该实现将执行3*10/sup / 12/ add /s。
{"title":"Arithmetic for digital neural networks","authors":"Dapeng Zhang, G. Jullien, W. Miller, E. Swartzlander","doi":"10.1109/ARITH.1991.145534","DOIUrl":"https://doi.org/10.1109/ARITH.1991.145534","url":null,"abstract":"The implementation of large input digital neurons using designs based on parallel counters is described. The implementation of the design uses a two-cell library, in which each cell is implemented using switching trees which are pipelined binary trees of n-channel transistors. Results obtained from initial switching trees realized with a 3- mu m CMOS process indicate that the design is capable of being pipelined at 40 MHz sample rates, with better performance expected for more advanced technologies. It appears feasible to develop a wafer-scale implementation with 2000 neurons (each with 1000 inputs) that would perform 3*10/sup 12/ additions/s.<<ETX>>","PeriodicalId":190650,"journal":{"name":"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126158290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ARITH.1991.145535
M. Muller, C. Rub, W. Rulling
The authors present a new idea for designing a chip which computes the exact sum of arbitrarily many floating-point numbers, i.e. it can accumulate the floating-point numbers without cancellation. Such a chip is needed to provide a fast implementation of Kulisch arithmetic. This is a new theory of floating-point arithmetic which makes it possible to compute least significant bit accurate solutions to even ill-conditioned numerical problems. The proposed approach avoids the disadvantages of previously suggested designs which are too large, too slow, or consume too much power. The crucial point is a technique for a fast carry resolution in a long accumulator. It can also be implemented in software.<>
{"title":"Exact accumulation of floating-point numbers","authors":"M. Muller, C. Rub, W. Rulling","doi":"10.1109/ARITH.1991.145535","DOIUrl":"https://doi.org/10.1109/ARITH.1991.145535","url":null,"abstract":"The authors present a new idea for designing a chip which computes the exact sum of arbitrarily many floating-point numbers, i.e. it can accumulate the floating-point numbers without cancellation. Such a chip is needed to provide a fast implementation of Kulisch arithmetic. This is a new theory of floating-point arithmetic which makes it possible to compute least significant bit accurate solutions to even ill-conditioned numerical problems. The proposed approach avoids the disadvantages of previously suggested designs which are too large, too slow, or consume too much power. The crucial point is a technique for a fast carry resolution in a long accumulator. It can also be implemented in software.<<ETX>>","PeriodicalId":190650,"journal":{"name":"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124385257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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