Pub Date : 1991-06-26DOI: 10.1109/ARITH.1991.145546
H. Yokoo
A class of new floating-point representations of real numbers, based on representations of the integers, is described. In the class, every representation uses a self-delimiting representation of the integers as a variable length field, and neither overflow nor underflow appears in practice. The adopted representations of the integers are defined systematically, so that representations of numbers greater than one have both exponent-significant and integer-fraction interpretations. Since representation errors are characterized by the length function of an underlying representation of the integers, systems superior in precision can be easily selected from the proposed class.<>
{"title":"Overflow/underflow-free floating-point number representations with self-delimiting variable-length exponent field","authors":"H. Yokoo","doi":"10.1109/ARITH.1991.145546","DOIUrl":"https://doi.org/10.1109/ARITH.1991.145546","url":null,"abstract":"A class of new floating-point representations of real numbers, based on representations of the integers, is described. In the class, every representation uses a self-delimiting representation of the integers as a variable length field, and neither overflow nor underflow appears in practice. The adopted representations of the integers are defined systematically, so that representations of numbers greater than one have both exponent-significant and integer-fraction interpretations. Since representation errors are characterized by the length function of an underlying representation of the integers, systems superior in precision can be easily selected from the proposed class.<<ETX>>","PeriodicalId":190650,"journal":{"name":"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129133548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-26DOI: 10.1109/ARITH.1991.145538
D. Gamberger
A novel division algorithm that is especially appropriate for residue number systems (RNSs) is presented. It makes use of the fact that the multiplicative inverse element of a divisor which is relatively prime to system moduli can be easily determined in the RNS. The number of its iterations depends only on the magnitude of the divisor and the moduli of the system. The problems in the algorithm realization are analyzed in detail, and a complete solution using the incompletely specified RNS is described.<>
{"title":"New approach to integer division in residue number systems","authors":"D. Gamberger","doi":"10.1109/ARITH.1991.145538","DOIUrl":"https://doi.org/10.1109/ARITH.1991.145538","url":null,"abstract":"A novel division algorithm that is especially appropriate for residue number systems (RNSs) is presented. It makes use of the fact that the multiplicative inverse element of a divisor which is relatively prime to system moduli can be easily determined in the RNS. The number of its iterations depends only on the magnitude of the divisor and the moduli of the system. The problems in the algorithm realization are analyzed in detail, and a complete solution using the incompletely specified RNS is described.<<ETX>>","PeriodicalId":190650,"journal":{"name":"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127961254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-26DOI: 10.1109/ARITH.1991.145537
Jen-Shiun Chiang, Mi Lu
A general algorithm for signed number division in residue number systems (RNSs) is presented. A parity checking technique is used to accomplish the sign and overflow detection in this algorithm. Compared with conventional methods of sign and overflow detection, the parity checking method is more efficient and practical. Sign magnitude arithmetic division is implemented using binary search. There is no restriction on the dividend and the divisor (except zero divisor), and no quotient estimation is necessary before the division is started. In hardware implementations, the storage of one table is required for parity checking, and all the other arithmetic operations are completed by calculations. Only simple operations are needed to accomplish this RNS division.<>
{"title":"A general division algorithm for residue number systems","authors":"Jen-Shiun Chiang, Mi Lu","doi":"10.1109/ARITH.1991.145537","DOIUrl":"https://doi.org/10.1109/ARITH.1991.145537","url":null,"abstract":"A general algorithm for signed number division in residue number systems (RNSs) is presented. A parity checking technique is used to accomplish the sign and overflow detection in this algorithm. Compared with conventional methods of sign and overflow detection, the parity checking method is more efficient and practical. Sign magnitude arithmetic division is implemented using binary search. There is no restriction on the dividend and the divisor (except zero divisor), and no quotient estimation is necessary before the division is started. In hardware implementations, the storage of one table is required for parity checking, and all the other arithmetic operations are completed by calculations. Only simple operations are needed to accomplish this RNS division.<<ETX>>","PeriodicalId":190650,"journal":{"name":"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127888446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-26DOI: 10.1109/ARITH.1991.145531
N. Takagi
A fast radix-4 modular multiplication hardware algorithm is proposed. It is efficient especially in applications, such as encryption/decryption in the RSA cryptosystem, where modular multiplications are carried out iteratively. Each subtraction for the division for residue calculation is embedded in the repeated multiply-addition. Numbers are represented in a redundant representation and addition/subtractions are performed without carry propagation. A serial-parallel modular multiplier based on the algorithm has a regular cellular array structure with a bit slice feature suitable for VLSI implementation.<>
{"title":"A radix-4 modular multiplication hardware algorithm efficient for iterative modular multiplications","authors":"N. Takagi","doi":"10.1109/ARITH.1991.145531","DOIUrl":"https://doi.org/10.1109/ARITH.1991.145531","url":null,"abstract":"A fast radix-4 modular multiplication hardware algorithm is proposed. It is efficient especially in applications, such as encryption/decryption in the RSA cryptosystem, where modular multiplications are carried out iteratively. Each subtraction for the division for residue calculation is embedded in the repeated multiply-addition. Numbers are represented in a redundant representation and addition/subtractions are performed without carry propagation. A serial-parallel modular multiplier based on the algorithm has a regular cellular array structure with a bit slice feature suitable for VLSI implementation.<<ETX>>","PeriodicalId":190650,"journal":{"name":"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic","volume":"231 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121131393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-26DOI: 10.1109/ARITH.1991.145560
P. Montuschi, L. Ciminiera
The authors present a novel algorithm for shared radix 2 division and square root whose main characteristic is the ability to avoid any addition when the digit 0 has been selected. The solution presented uses a redundant representation of the partial remainder, while keeping the advantages of classical solutions. It is shown how the next digit of the result can be selected even when the remainder is not updated; the tradeoff arising is also indicated. The average occurrences of 0 digit selections are also estimated in order to assess the benefits of the algorithm presented.<>
{"title":"Simple radix 2 division and square root with skipping of some addition steps","authors":"P. Montuschi, L. Ciminiera","doi":"10.1109/ARITH.1991.145560","DOIUrl":"https://doi.org/10.1109/ARITH.1991.145560","url":null,"abstract":"The authors present a novel algorithm for shared radix 2 division and square root whose main characteristic is the ability to avoid any addition when the digit 0 has been selected. The solution presented uses a redundant representation of the partial remainder, while keeping the advantages of classical solutions. It is shown how the next digit of the result can be selected even when the remainder is not updated; the tradeoff arising is also indicated. The average occurrences of 0 digit selections are also estimated in order to assess the benefits of the algorithm presented.<<ETX>>","PeriodicalId":190650,"journal":{"name":"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic","volume":"55 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127399079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-26DOI: 10.1109/ARITH.1991.145549
Douglas M. Priest
The author presents techniques for performing computations of very high accuracy using only straightforward floating-point arithmetic operations of limited precision. The validity of these techniques is proved under very general hypotheses satisfied by most implementations of floating-point arithmetic. To illustrate the applications of these techniques, an algorithm is presented which computes the intersection of a line and a line segment. The algorithm is guaranteed to correctly decide whether an intersection exists and, if so, to produce the coordinates of the intersection point accurate to full precision. The algorithm is usually quite efficient; only in a few cases does guaranteed accuracy necessitate an expensive computation.<>
{"title":"Algorithms for arbitrary precision floating point arithmetic","authors":"Douglas M. Priest","doi":"10.1109/ARITH.1991.145549","DOIUrl":"https://doi.org/10.1109/ARITH.1991.145549","url":null,"abstract":"The author presents techniques for performing computations of very high accuracy using only straightforward floating-point arithmetic operations of limited precision. The validity of these techniques is proved under very general hypotheses satisfied by most implementations of floating-point arithmetic. To illustrate the applications of these techniques, an algorithm is presented which computes the intersection of a line and a line segment. The algorithm is guaranteed to correctly decide whether an intersection exists and, if so, to produce the coordinates of the intersection point accurate to full precision. The algorithm is usually quite efficient; only in a few cases does guaranteed accuracy necessitate an expensive computation.<<ETX>>","PeriodicalId":190650,"journal":{"name":"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128044832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-26DOI: 10.1109/ARITH.1991.145540
S. Piestrak
The design of residue generators and multioperand modular adders is studied. Novel highly parallel schemes using carry-save adders with end-around carry are proposed for either type of circuit. They are derived on the basis of the periodicity of the series of powers of two taken modulo A (A is a module). The novel circuits are faster and use less hardware than existing similar circuits.<>
{"title":"Design of residue generators and multioperand modular adders using carry-save adders","authors":"S. Piestrak","doi":"10.1109/ARITH.1991.145540","DOIUrl":"https://doi.org/10.1109/ARITH.1991.145540","url":null,"abstract":"The design of residue generators and multioperand modular adders is studied. Novel highly parallel schemes using carry-save adders with end-around carry are proposed for either type of circuit. They are derived on the basis of the periodicity of the series of powers of two taken modulo A (A is a module). The novel circuits are faster and use less hardware than existing similar circuits.<<ETX>>","PeriodicalId":190650,"journal":{"name":"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129349513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-26DOI: 10.1109/ARITH.1991.145551
V. Kantabutra
A method for designing optimum-speed one-level carry-skip adders is described. This method always yields the fastest adders if the assumptions of A. Guyot et al. (1987) hold, that is if the ripple time (a circuit parameter) of a carry signal is a linear function of the number of bit positions that the carry signal propagates through, and if the skip time (another circuit parameter) of a carry signal is a linear function of the number of blocks of bit positions skipped by the signal, or if these two parameters are such mildly nonlinear functions that can be modeled by a linear function without any effect on any of the results obtained. The circuit design method is useful because in device technologies such as 2-AlU CMOS the nonlinearities are often insignificant. The present results are compared with those of Guyot et al. as well as with the results of V.G. Oklobdzija and E.R. Barnes (1985).<>
{"title":"Designing optimum carry-skip adders","authors":"V. Kantabutra","doi":"10.1109/ARITH.1991.145551","DOIUrl":"https://doi.org/10.1109/ARITH.1991.145551","url":null,"abstract":"A method for designing optimum-speed one-level carry-skip adders is described. This method always yields the fastest adders if the assumptions of A. Guyot et al. (1987) hold, that is if the ripple time (a circuit parameter) of a carry signal is a linear function of the number of bit positions that the carry signal propagates through, and if the skip time (another circuit parameter) of a carry signal is a linear function of the number of blocks of bit positions skipped by the signal, or if these two parameters are such mildly nonlinear functions that can be modeled by a linear function without any effect on any of the results obtained. The circuit design method is useful because in device technologies such as 2-AlU CMOS the nonlinearities are often insignificant. The present results are compared with those of Guyot et al. as well as with the results of V.G. Oklobdzija and E.R. Barnes (1985).<<ETX>>","PeriodicalId":190650,"journal":{"name":"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129660347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-26DOI: 10.1109/ARITH.1991.145552
P. K. Chan, M. Schlag, C. Thomborson, V. Oklobdzija
The worst-case carry propagation delays in carry-skip adders and block carry-lookahead adders depend on how the full adders are grouped structurally together into blocks as well as the number of levels. The authors report a multidimensional dynamic programming paradigm for configuring these two adders to attain minimum latency. Previous methods are applicable only to very limited delay models that do not guarantee a minimum latency configuration. Under the proposed delay model, critical path delay is calculated taking into account not only the intrinsic gate delays but also the fanin and fanout contributions.<>
{"title":"Delay optimization of carry-skip adders and block carry-lookahead adders","authors":"P. K. Chan, M. Schlag, C. Thomborson, V. Oklobdzija","doi":"10.1109/ARITH.1991.145552","DOIUrl":"https://doi.org/10.1109/ARITH.1991.145552","url":null,"abstract":"The worst-case carry propagation delays in carry-skip adders and block carry-lookahead adders depend on how the full adders are grouped structurally together into blocks as well as the number of levels. The authors report a multidimensional dynamic programming paradigm for configuring these two adders to attain minimum latency. Previous methods are applicable only to very limited delay models that do not guarantee a minimum latency configuration. Under the proposed delay model, critical path delay is calculated taking into account not only the intrinsic gate delays but also the fanin and fanout contributions.<<ETX>>","PeriodicalId":190650,"journal":{"name":"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128955682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-26DOI: 10.1109/ARITH.1991.145529
G. Bohlender, W. Walter, Peter Kornerup, D. Matula
Semantics are given for the four elementary arithmetic operations and the square root, to characterize what are termed exact floating point operations. The operands of the arithmetic operations and the argument of the square root are all floating point numbers in one format. In every case, the result is a pair of floating point numbers in the same format with no accuracy lost in the computation. These semantics make it possible to realize the following principle: it shall be a user option to discard any information in the result of a floating point arithmetic operation. The reliability and portability previously associated with only mathematical software implementations in integer arithmetic can thus be attained exploiting the generally higher efficiency of floating point hardware.<>
{"title":"Semantics for exact floating point operations","authors":"G. Bohlender, W. Walter, Peter Kornerup, D. Matula","doi":"10.1109/ARITH.1991.145529","DOIUrl":"https://doi.org/10.1109/ARITH.1991.145529","url":null,"abstract":"Semantics are given for the four elementary arithmetic operations and the square root, to characterize what are termed exact floating point operations. The operands of the arithmetic operations and the argument of the square root are all floating point numbers in one format. In every case, the result is a pair of floating point numbers in the same format with no accuracy lost in the computation. These semantics make it possible to realize the following principle: it shall be a user option to discard any information in the result of a floating point arithmetic operation. The reliability and portability previously associated with only mathematical software implementations in integer arithmetic can thus be attained exploiting the generally higher efficiency of floating point hardware.<<ETX>>","PeriodicalId":190650,"journal":{"name":"[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123494520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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