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2020 IEEE 2nd International Conference on Circuits and Systems (ICCS)最新文献

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Ringing Test for Second-Order Sallen-Key Low-Pass Filters 二阶萨伦键低通滤波器的振铃测试
Pub Date : 2020-12-10 DOI: 10.1109/ICCS51219.2020.9336525
MinhTri Tran, A. Kuwana, Haruo Kobayashi
This paper presents a ringing test for 2nd-order Sallen-Key low-pass filters. A comparison measurement is constructed, which takes into account the measurement of a self-loop function in a transfer function. Based on the phase margin at unity of the self-loop function, a general stability criterion for second-order linear systems is proposed in terms of operating regions. In case of under-damping region, the ringing occurs and makes the system unstable. The advantage of the proposed criterion lies in its simplicity than some of the existing results. The new stability criterion is applied to the network based negative feedback issues. Experimental results show that the proposed method is quite effective.
本文给出了二阶萨伦键低通滤波器的振铃测试方法。考虑传递函数中自环函数的测量,构造了一个比较测量。基于自环函数在单位处的相位裕度,提出了二阶线性系统在工作区域上的一般稳定性判据。在欠阻尼区,会产生振铃,使系统不稳定。所提出的准则的优点在于它比现有的一些结果简单。将新的稳定性判据应用于基于网络的负反馈问题。实验结果表明,该方法是非常有效的。
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引用次数: 1
Codesign of a Broadband Doherty Power Amplifier with Microstrip Bandpass Filters 带微带带通滤波器的宽带多尔蒂功率放大器的协同设计
Pub Date : 2020-12-10 DOI: 10.1109/ICCS51219.2020.9336594
Yiming Lyu, Zhiqin Zhao
A broadband Doherty power amplifier codesigned with filters and a series of continuous modes is presented. Three bandpass filters are used to design post matching network, output matching network for carrier and peaking stages. These filters can not only suppress the harmonics but also interferences outside the operating band of the power amplifier. Theory named a series of continuous modes is used to transform impedance looking from carrier stage into power combing point to the objective high efficiency design space while even-odd-mode analysis is used to analysis the response of the three BPFs. Finally, a broadband 6-dB output back-off DPA operating in 1.3-2.2 GHz is designed. Simulation results exhibit output backoff drain efficiency of 56.0%-78.6% and saturated drain efficiency of 42.1%-60.2%. Moreover, the saturated output power level is 43.3-44.9 dBm with a gain of 10.3-11.8 dB.
提出了一种与滤波器和一系列连续模式协同设计的宽带多尔蒂功率放大器。采用三个带通滤波器分别设计后级匹配网络、载波级输出匹配网络和峰值级输出匹配网络。这些滤波器不仅能抑制谐波,还能抑制功率放大器工作频带外的干扰。采用连续模态序列理论将阻抗从载波级到功率精梳点的观察转化为客观的高效设计空间,采用奇偶模态分析方法分析了三个bpf的响应。最后,设计了一个工作在1.3-2.2 GHz频段的宽带6db输出回退DPA。仿真结果表明,输出回泄效率为56.0% ~ 78.6%,饱和泄效率为42.1% ~ 60.2%。饱和输出功率为43.3 ~ 44.9 dBm,增益为10.3 ~ 11.8 dB。
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引用次数: 0
Design of a Wideband Compact CMOS Integrated Attenuator with Low Insertion Loss and High Accuracy 一种低插入损耗、高精度的宽带紧凑型CMOS集成衰减器设计
Pub Date : 2020-12-10 DOI: 10.1109/ICCS51219.2020.9336526
Yunzhao Sun, Chen-Chen Yang, Tong Li, N. Yan, Hongtao Xu
This paper presents an integrated attenuator (IATT) with 40nm bulk COMS process. The IATT that works from 15GHz to 20GHz can be used in phased array system and it only employs MOSFET rather than poly silicon resistors in the main signal path and can cover attenuation range up to 14 dB by step of 2 dB. Furthermore, the root-mean-square (RMS) attenuation error can be less than 0.15dB. Due to the integrated structure the IATT only occupies 0.167 mm2 including inductors (inds) and 0.0158 mm2 excluding inductors. Besides, the IATT also shows a relative low insertion loss less than 3dB. By adopting the shunt capacitor (cap) compensation technique the RMS phase error of the IATT can be less than 0.5°.
提出了一种采用40nm块体COMS工艺的集成衰减器(IATT)。工作在15GHz到20GHz的itt可以用于相控阵系统,它在主信号路径中只使用MOSFET而不是多晶硅电阻,并且可以覆盖高达14 dB的衰减范围。此外,均方根(RMS)衰减误差可小于0.15dB。由于采用了集成化的结构,包括电感在内,IATT的占地面积仅为0.167 mm2,不包括电感的占地面积仅为0.0158 mm2。此外,IATT还显示出相对较低的插入损耗,小于3dB。采用并联电容(帽)补偿技术,可使IATT的均方根相位误差小于0.5°。
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引用次数: 0
Research on Coordination Solution Strategy of Power System Transient Stability and Short Circuit Current Based on External Penalty Function Method 基于外部惩罚函数法的电力系统暂态稳定与短路电流协调求解策略研究
Pub Date : 2020-12-10 DOI: 10.1109/ICCS51219.2020.9336605
Shuai Yang, Zhongwei He, Wentao Huang, Jun He, Zhijun Yuan, Jinman Yu
As large-capacity units shift down to low-level power grids, the problems of transient stability and short-circuit current of power systems become increasingly prominent. The traditional control methods such as generator-tripping and load-shedding can only solve one of the problems, but cannot fundamentally solve the contradiction between transient stability and short-circuit current at the same time, resulting in poor power grid stability. A practical control strategy of connecting transient stability and short-circuit current problems of the system through system impedance are studied for the first time in this paper and a mathematical model is established with system impedance as the core. An external penalty function method is proposed to solve the contradiction between transient stability and short-circuit current by seeking the optimal impedance of the system. Taking GGE (A power grid in Hubei) regional power grid as an example for simulation verification through Power System Analysis Software Package (PSASP), the results show that the problems of transient stability and short-circuit current in the GGE regional power grid have been effectively solved and the power grid can operate stably. It is verified that the proposed coordinated control strategy of transient stability and short-circuit current can effectively improve the stability of power system.
随着大容量机组向低电平电网转移,电力系统暂态稳定和短路电流问题日益突出。传统的发电机脱扣、减载等控制方法只能解决其中的一个问题,而不能同时从根本上解决暂态稳定与短路电流之间的矛盾,导致电网稳定性差。本文首次研究了一种通过系统阻抗将系统暂态稳定和短路电流问题联系起来的实用控制策略,并建立了以系统阻抗为核心的数学模型。通过寻找系统的最优阻抗,提出了一种外部罚函数法来解决暂态稳定性与短路电流之间的矛盾。以GGE(湖北A电网)区域电网为例,通过电力系统分析软件包(PSASP)进行仿真验证,结果表明,GGE区域电网暂态稳定和短路电流问题得到了有效解决,电网能够稳定运行。验证了所提出的暂态稳定与短路电流协调控制策略能有效地提高电力系统的稳定性。
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引用次数: 0
Evaluation of On-Chip Accelerator Performance Based on RocketChip 基于RocketChip的片上加速器性能评价
Pub Date : 2020-12-10 DOI: 10.1109/ICCS51219.2020.9336609
Jinghe Wei, Zongguang Yu, De Liu
In the fields of artificial intelligence and signal processing where computing tasks are dense or algorithms are complex, researchers usually design heterogeneous SoC of CPU + accelerator to improve the efficiency of system. In heterogeneous SoC, accelerators often act as coprocessors or channel accelerators. In this paper, in order to study the coupling relationship between accelerators and CPU, we respectively design CORDIC algorithm accelerators of coprocessor, CORIDC channel accelerator, vector dot product accelerators of coprocessor and channel accelerator based on RISC-V open source project - RocketChip. The acceleration effect of each accelerator is simulated by Modelsim. It is verified that the acceleration ratio of CORDIC algorithm coprocessor to CPU is about 151 times, and the accelerator ratio of CORDIC channel accelerator is about 103 times. The longer the vector length is, the more significant the acceleration effect of the vector dot product accelerator is, and the acceleration effect of the vector dot product channel accelerator is significantly better than that of the vector dot product coprocessor. We find that the performance of the coprocessor is limited by the speed of data access. Moreover, when the coprocessor is not tightly coupled to the CPU, additional time overhead is introduced.
在计算任务密集或算法复杂的人工智能和信号处理领域,研究人员通常会设计CPU +加速器的异构SoC来提高系统效率。在异构SoC中,加速器通常充当协处理器或通道加速器。本文为了研究加速器与CPU之间的耦合关系,基于RISC-V开源项目RocketChip,分别设计了协处理器的CORDIC算法加速器、CORIDC通道加速器、协处理器的矢量点积加速器和通道加速器。利用Modelsim软件对各加速器的加速效果进行仿真。验证了CORDIC算法协处理器对CPU的加速比约为151倍,CORDIC通道加速器的加速比约为103倍。矢量长度越长,矢量点积加速器的加速效果越显著,且矢量点积通道加速器的加速效果明显优于矢量点积协处理器。我们发现协处理器的性能受到数据访问速度的限制。此外,当协处理器没有与CPU紧密耦合时,会引入额外的时间开销。
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引用次数: 1
A 120GHz Frequency Tripler with Improved Output Power in 40nm CMOS 一种40nm CMOS输出功率提高的120GHz三倍频器
Pub Date : 2020-12-10 DOI: 10.1109/ICCS51219.2020.9336593
Han Cui, Leijun Xu
This paper introduces a frequency tripler with improved output power in 40nm CMOS process. Low insertion loss and high balanced Baluns are designed for the input and output impedance matching. Meanwhile, LC series resonance is used to suppress the fundamental wave and improve the power of third harmonic wave. When the input power is 10dBm, the peak output power is 3.7dBm, the frequency conversion loss is 6.3dBm and the fundamental suppression ratio is 41dBc. The total DC power consumption is 9.6mW. The 3-dB bandwidth is 12GHz (115.5GHz~127.5GHz).
本文介绍了一种40nm CMOS工艺中输出功率提高的三倍频器。低插入损耗和高平衡的平衡器设计用于输入和输出阻抗匹配。同时,采用LC串联谐振抑制基波,提高三次谐波功率。当输入功率为10dBm时,峰值输出功率为3.7dBm,变频损耗为6.3dBm,基波抑制比为41dBc。直流总功耗9.6mW。3db带宽为12GHz (115.5GHz~127.5GHz)。
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引用次数: 0
Research of Control Strategy of Power System Stabilizer Based on Reinforcement Learning 基于强化学习的电力系统稳定器控制策略研究
Pub Date : 2020-12-10 DOI: 10.1109/ICCS51219.2020.9336612
Xingyu Zhu, T. Jin
Power system stabilizer (PSS) is used to generate excitation system auxiliary control signals which can suppress low frequency oscillation in power system. It has the ability of self-learning and parameter online tuning, which is a development trend of smart grid PSS controller in the future. This paper presents a design method of power system stabilizer based on reinforcement learning. Q-learning algorithm is one of reinforcement learning, and is used to PSS as the additional control. The simulation results show that the PSS based on Q-learning can effectively improve the ability of suppressing low frequency oscillation in power system, and the robustness of the system is significantly enhanced.
电力系统稳定器(PSS)用于产生励磁系统辅助控制信号,以抑制电力系统的低频振荡。它具有自学习能力和参数在线整定能力,是未来智能电网PSS控制器的发展趋势。提出了一种基于强化学习的电力系统稳定器设计方法。q -学习算法是强化学习的一种,用于PSS作为附加控制。仿真结果表明,基于q -学习的PSS能有效提高电力系统抑制低频振荡的能力,显著增强了系统的鲁棒性。
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引用次数: 3
Do We Really Need Complicated Solar Energy Harvesting Circuits for Low Cost Sensor Nodes? 低成本传感器节点真的需要复杂的太阳能收集电路吗?
Pub Date : 2020-12-10 DOI: 10.1109/ICCS51219.2020.9336611
Wei Liu, Wenzhuo Yin, Jian Xie, Rong Luo, Shunren Hu
Existing solar energy harvesting structures with maximum power point tracking capability are typically a bit complicated and expensive for low cost sensor nodes, which makes them unsuitable for large-scale deployments of wireless sensor networks. In this paper, a voltage matching method for suboptimal solar energy harvesting is proposed. By matching the working voltage ranges of rechargeable batteries with the maximum power point voltages of solar panels, the output voltages of solar panels could be clamped around the maximum power point only using a simple and cheap diode. In this way, suboptimal but efficient enough solar energy harvesting could be achieved. Experimental results show that compared with existing structures, energy harvesting efficiency of the proposed method only reduces by 2.3%~18.8%.
现有的具有最大功率点跟踪能力的太阳能收集结构对于低成本传感器节点来说通常有点复杂和昂贵,这使得它们不适合大规模部署无线传感器网络。本文提出了一种用于次优太阳能收集的电压匹配方法。通过将可充电电池的工作电压范围与太阳能电池板的最大功率点电压相匹配,只需使用一个简单廉价的二极管,就可以将太阳能电池板的输出电压固定在最大功率点附近。通过这种方式,可以实现次优但足够有效的太阳能收集。实验结果表明,与现有结构相比,该方法的能量收集效率仅降低2.3%~18.8%。
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引用次数: 1
Magnetic Field Shielding Optimization Based on Wireless Charging 基于无线充电的磁场屏蔽优化
Pub Date : 2020-12-10 DOI: 10.1109/ICCS51219.2020.9336524
Xuguang Liu, K. Wu, Rui Wang, Zhengwei Pan, Erxian Yao
For the design of wireless charging magnetic coupling coil, the principle is explained and the loss calculation analysis is carried out, and the loss calculation method of the magnetic coupling coil, magnetic core and shielding plate is analyzed. This paper uses the finite element method to model and design the target parameters of the magnetic coupling mechanism, compare and calculate the mass proportion of each component of the magnetic coupling mechanism, and optimize the magnetic core mass proportion. The magnetic permeability and loss curve of nanocrystalline materials and ferrite materials are compared and analyzed in detail. This paper proposes to use high permeability and low loss nanocrystalline materials to optimize the thickness of the magnetic core. Through the optimization scheme, it can be seen that the quality of the magnetic core is reduced by about 51%, and the transmission efficiency of the magnetic coupling coil remains basically unchanged. Co-simulation has been used to verify the influence of the optimization scheme on the transmission efficiency. The results show that the optimization of the magnetic core does not have a significant impact on the system efficiency, to achieve the intended purpose of the design.
对于无线充电磁耦合线圈的设计,阐述了原理并进行了损耗计算分析,分析了磁耦合线圈、磁芯和屏蔽板的损耗计算方法。本文采用有限元法对磁耦合机构的目标参数进行建模和设计,对磁耦合机构各部件的质量比例进行比较计算,并对磁芯质量比例进行优化。对纳米晶材料和铁氧体材料的磁导率和损耗曲线进行了详细的比较分析。本文提出采用高磁导率、低损耗的纳米晶材料来优化磁芯厚度。通过优化方案可以看出,磁芯质量降低了51%左右,磁耦合线圈的传动效率基本保持不变。通过联合仿真验证了优化方案对传动效率的影响。结果表明,磁芯的优化对系统效率没有明显影响,达到了设计的预期目的。
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引用次数: 1
[Copyright notice] (版权)
Pub Date : 2020-12-10 DOI: 10.1109/iccs51219.2020.9336592
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引用次数: 0
期刊
2020 IEEE 2nd International Conference on Circuits and Systems (ICCS)
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