Pub Date : 2014-06-09DOI: 10.1109/ICEP.2014.6826681
Jian-Chun Liu, H. Yu, Gong Zhang, Zhenghong Wang, Jusheng Ma
The Anand constitutive model has emerged as a popular method to describe the inelastic deformation behavior of Sn-Pb solders and, more recently, to describe the behavior of lead-free solders in electronic assemblies, mainly due to its effective description of constitutive behavior and high compatibility with finite element modes. Heretofore, although plenty of experimental and theoretical works have been conducted on building constitutive models for lead-free solders, e.g. Sn-Ag, Sn-Ag-Cu, Sn-Cu based solders, insufficient works have been conducted on modeling Sn-Zn based lead-free solder alloys. In this paper, a series of compression tests were conducted for a novel lead-free solder Sn-9Zn-2.5Bi-0.5In-0.05P and Sn-8Zn-3Bi solder at three constant strain rates (10-3/s, 10-2/s, 10-1/s) and different temperatures (20°C, 60°C, 100°C). Anand constitutive model was applied to describe the inelastic behavior as well as saturation stress of both solder alloys. Comparison of the experimental results and Anand model predictions were evaluated with the material parameters extracted from compression tests and non-linear least squares fitting of the constitutive relation. The results reveal that, for both two solder alloys, the Anand model predictions are in good agreement with experimental data of stress-strain responses at various strain rates and temperatures applied in the present work. In addition, the stress-strain responses of both solder alloys are also discussed on the basis of experimental data.
{"title":"Constitutive behavior and Anand model of novel lead-free solder Sn-Zn-Bi-In-P","authors":"Jian-Chun Liu, H. Yu, Gong Zhang, Zhenghong Wang, Jusheng Ma","doi":"10.1109/ICEP.2014.6826681","DOIUrl":"https://doi.org/10.1109/ICEP.2014.6826681","url":null,"abstract":"The Anand constitutive model has emerged as a popular method to describe the inelastic deformation behavior of Sn-Pb solders and, more recently, to describe the behavior of lead-free solders in electronic assemblies, mainly due to its effective description of constitutive behavior and high compatibility with finite element modes. Heretofore, although plenty of experimental and theoretical works have been conducted on building constitutive models for lead-free solders, e.g. Sn-Ag, Sn-Ag-Cu, Sn-Cu based solders, insufficient works have been conducted on modeling Sn-Zn based lead-free solder alloys. In this paper, a series of compression tests were conducted for a novel lead-free solder Sn-9Zn-2.5Bi-0.5In-0.05P and Sn-8Zn-3Bi solder at three constant strain rates (10-3/s, 10-2/s, 10-1/s) and different temperatures (20°C, 60°C, 100°C). Anand constitutive model was applied to describe the inelastic behavior as well as saturation stress of both solder alloys. Comparison of the experimental results and Anand model predictions were evaluated with the material parameters extracted from compression tests and non-linear least squares fitting of the constitutive relation. The results reveal that, for both two solder alloys, the Anand model predictions are in good agreement with experimental data of stress-strain responses at various strain rates and temperatures applied in the present work. In addition, the stress-strain responses of both solder alloys are also discussed on the basis of experimental data.","PeriodicalId":195433,"journal":{"name":"2014 International Conference on Electronics Packaging (ICEP)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123431925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-09DOI: 10.1109/ICEP.2014.6826725
H. Kudo, T. Yonekawa, S. Yoshimi, Y. Oguri, A. Tsukune, Y. Kim, H. Kitada, K. Fjimoto, I. Kinefuchi, Y. Matsumoto, T. Ohba
A multi-channel electro-osmotic flow (EOF) implemented to the closed-channel cooling system (C3S) has been developed for thermal management of stacked chips (3D-ICs). The EOF pump, which was fabricated using MEMS technology, provided driving capabilities of fluid flow through the micro channel at the Pmax of 1 × 104 Pa and Qmax of 38 μl/min. Cooling capability as high as 140 W/cm2 was demonstrated for the first time.
{"title":"High-performance cooling system with multi-channel electro-osmotic flow pumps for high-power 3D-ICs","authors":"H. Kudo, T. Yonekawa, S. Yoshimi, Y. Oguri, A. Tsukune, Y. Kim, H. Kitada, K. Fjimoto, I. Kinefuchi, Y. Matsumoto, T. Ohba","doi":"10.1109/ICEP.2014.6826725","DOIUrl":"https://doi.org/10.1109/ICEP.2014.6826725","url":null,"abstract":"A multi-channel electro-osmotic flow (EOF) implemented to the closed-channel cooling system (C<sup>3</sup>S) has been developed for thermal management of stacked chips (3D-ICs). The EOF pump, which was fabricated using MEMS technology, provided driving capabilities of fluid flow through the micro channel at the P<sub>max</sub> of 1 × 10<sup>4</sup> Pa and Q<sub>max</sub> of 38 μl/min. Cooling capability as high as 140 W/cm<sup>2</sup> was demonstrated for the first time.","PeriodicalId":195433,"journal":{"name":"2014 International Conference on Electronics Packaging (ICEP)","volume":"9 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121587920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-27DOI: 10.1109/ECTC.2014.6897542
T. Sakurai, Hikaru Mizuno, K. Okamoto, K. Inomata
This paper reports on our development of a low temperature curable photo-sensitive insulator. The design concept of our photo-sensitive insulator is based on a phenolic resin as the main component to perform good lithography and a polymeric cross-linker containing an epoxy functional unit. This polymeric epoxy cross-linker can decrease wafer stress by controlling the distance between cross-linked points with phenolic resin. Moreover, our photo-sensitive insulator contains naphthoquinone diazide (DNQ) compounds commonly used in positive tone resists. Through these concepts, our low temperature curable (around 200 °C) photo-sensitive insulator shows low residual stress (<;20MPa), low elastic modulus (<;1.8GPa), good chemical resistance and good lithography performance.
{"title":"Novel low temperature curable photo-sensitive insulator","authors":"T. Sakurai, Hikaru Mizuno, K. Okamoto, K. Inomata","doi":"10.1109/ECTC.2014.6897542","DOIUrl":"https://doi.org/10.1109/ECTC.2014.6897542","url":null,"abstract":"This paper reports on our development of a low temperature curable photo-sensitive insulator. The design concept of our photo-sensitive insulator is based on a phenolic resin as the main component to perform good lithography and a polymeric cross-linker containing an epoxy functional unit. This polymeric epoxy cross-linker can decrease wafer stress by controlling the distance between cross-linked points with phenolic resin. Moreover, our photo-sensitive insulator contains naphthoquinone diazide (DNQ) compounds commonly used in positive tone resists. Through these concepts, our low temperature curable (around 200 °C) photo-sensitive insulator shows low residual stress (<;20MPa), low elastic modulus (<;1.8GPa), good chemical resistance and good lithography performance.","PeriodicalId":195433,"journal":{"name":"2014 International Conference on Electronics Packaging (ICEP)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133402601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-23DOI: 10.1109/ICEP.2014.6826706
C. Kaestle, J. Franke
Today's state-of-the-art top level interconnect technology in power modules is an aluminum wire wedge/wedge bond process. Being the bottleneck for realizing even higher switching frequencies and thus higher junction temperatures made possible by upcoming wide bandgap semiconductors, innovative packaging technologies such as copper wire wedge/wedge bonding are a key issue in pushing the technological frontier of power electronics even further. With its higher electrical and thermal conductivity as well as its lower coefficient of thermal expansion copper wire bonding bears the chance of a significant improvement in one of the most sensitive lifetime limiting areas of power modules. In contrast copper's higher young's modulus as well as a higher strain hardening require increased bond parameters resulting in new challenges for the bonding process. A smaller and more sensitive process window is expected to be the other side of the coin. This study aims to display the advantages and challenges of the aluminum and copper wire bonding process for power modules with special focus on a comparative analysis of their process windows. To obtain statistically significant conclusions all tests are performed in randomized rotatable central composite response surface design of experiment studies. A comparison of attainable shear forces as well as observed failure modes will be the bases to define criteria for acceptance that are applicable for the used wire bond material. This deep understanding of all process and process influencing parameters will be needed in order to set up and evaluate a reliable and optimized production process for power modules.
{"title":"Comparative analysis of the process window of aluminum and copper wire bonding for power electronics applications","authors":"C. Kaestle, J. Franke","doi":"10.1109/ICEP.2014.6826706","DOIUrl":"https://doi.org/10.1109/ICEP.2014.6826706","url":null,"abstract":"Today's state-of-the-art top level interconnect technology in power modules is an aluminum wire wedge/wedge bond process. Being the bottleneck for realizing even higher switching frequencies and thus higher junction temperatures made possible by upcoming wide bandgap semiconductors, innovative packaging technologies such as copper wire wedge/wedge bonding are a key issue in pushing the technological frontier of power electronics even further. With its higher electrical and thermal conductivity as well as its lower coefficient of thermal expansion copper wire bonding bears the chance of a significant improvement in one of the most sensitive lifetime limiting areas of power modules. In contrast copper's higher young's modulus as well as a higher strain hardening require increased bond parameters resulting in new challenges for the bonding process. A smaller and more sensitive process window is expected to be the other side of the coin. This study aims to display the advantages and challenges of the aluminum and copper wire bonding process for power modules with special focus on a comparative analysis of their process windows. To obtain statistically significant conclusions all tests are performed in randomized rotatable central composite response surface design of experiment studies. A comparison of attainable shear forces as well as observed failure modes will be the bases to define criteria for acceptance that are applicable for the used wire bond material. This deep understanding of all process and process influencing parameters will be needed in order to set up and evaluate a reliable and optimized production process for power modules.","PeriodicalId":195433,"journal":{"name":"2014 International Conference on Electronics Packaging (ICEP)","volume":"312 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124288780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-23DOI: 10.1109/ICEP.2014.6826747
K. Nishi, T. Hatakeyama, S. Nakagawa, M. Ishizuka
This paper explores and investigates tablet device with slate style chassis by utilizing one-dimensional thermal network expression. Thermal network is constructed from results by heat conduction simulation to well understand root causes of hot spot temperature difference between several cases. It is found that thermal spreading resistances in thermal network vary by the difference of model construction even in the case that they are not directly next to the component whose configuration is changed.
{"title":"One-dimensional thermal network expression of tablet device with slate style chassis","authors":"K. Nishi, T. Hatakeyama, S. Nakagawa, M. Ishizuka","doi":"10.1109/ICEP.2014.6826747","DOIUrl":"https://doi.org/10.1109/ICEP.2014.6826747","url":null,"abstract":"This paper explores and investigates tablet device with slate style chassis by utilizing one-dimensional thermal network expression. Thermal network is constructed from results by heat conduction simulation to well understand root causes of hot spot temperature difference between several cases. It is found that thermal spreading resistances in thermal network vary by the difference of model construction even in the case that they are not directly next to the component whose configuration is changed.","PeriodicalId":195433,"journal":{"name":"2014 International Conference on Electronics Packaging (ICEP)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116717205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-23DOI: 10.1109/ICEP.2014.6826679
O. Mokhtari, Min-Su Kim, H. Nishikawa, F. Kawashiro, S. Itou, Takehiko Maeda, T. Hirose, T. Eto
This research focuses on the formation and growth behavior of Cu/Al intermetallic compounds (IMCs). In order to investigate IMC growth after 30, 60 and 120 min of aging at 270, 300 and 330 °C, cross-section of Al, Cu and Cu/Al IMCs were examined by scanning electron microscopy (SEM). The results showed that the consumption of the Al layer is more rapid than that of Cu layer, and that after 120 min at 330 °C the Al layer is entirely consumed. The formation of three distinct Cu/Al IMC layers was observed. Scanning transmission electron microscopy (STEM)/energy-dispersive X-ray spectroscopy (EDS) was used to identify the three IMC layers formed at the interface. These were CuAl, Cu3Al2 and Cu9Al4. Also, the activation energies of Cu/Al IMC growth were obtained from an Arrhenius plot.
{"title":"Effect of isothermal aging on the growth behavior of Cu/Al intermetallic compounds","authors":"O. Mokhtari, Min-Su Kim, H. Nishikawa, F. Kawashiro, S. Itou, Takehiko Maeda, T. Hirose, T. Eto","doi":"10.1109/ICEP.2014.6826679","DOIUrl":"https://doi.org/10.1109/ICEP.2014.6826679","url":null,"abstract":"This research focuses on the formation and growth behavior of Cu/Al intermetallic compounds (IMCs). In order to investigate IMC growth after 30, 60 and 120 min of aging at 270, 300 and 330 °C, cross-section of Al, Cu and Cu/Al IMCs were examined by scanning electron microscopy (SEM). The results showed that the consumption of the Al layer is more rapid than that of Cu layer, and that after 120 min at 330 °C the Al layer is entirely consumed. The formation of three distinct Cu/Al IMC layers was observed. Scanning transmission electron microscopy (STEM)/energy-dispersive X-ray spectroscopy (EDS) was used to identify the three IMC layers formed at the interface. These were CuAl, Cu3Al2 and Cu9Al4. Also, the activation energies of Cu/Al IMC growth were obtained from an Arrhenius plot.","PeriodicalId":195433,"journal":{"name":"2014 International Conference on Electronics Packaging (ICEP)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125954338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-23DOI: 10.1109/ICEP.2014.6826659
Tsuyoshi Tsunoda, Ryouhei Kasai, Shozo Yuki, N. Ota, Keisuke Sawada, Y. Yamamoto, Y. Fukuoka, S. Sagara
Advanced vertical interconnect technology that combines traditional HDI (high density interconnect) structures feature micro-vias and conductive paste-vias was developed to fabricate multilayer printed circuit board, such as ultra-multilayer printed circuit board like probe card or IC testing board, having excellent electrical performance, mechanical reliability and mass productivity at reasonable cost. This advanced multilayer printed circuit board constituted of high elastic modulus thermosetting dielectric composition with interstitial via holes (IVH) and/or Cu micro-vias (HDI), besides sintered conductive paste-vias buried in low elastic modulus thermosetting dielectric composition. The latter composition will properly act as mechanical buffering layer of vertical interconnection between upper and lower multilayer boards. This paper discuss about manufacturing process factor, that is pre-curing temperature, affecting the optimum electrical performance at the interface of HDI Cu lands and conductive paste with interposing low elastic modulus dielectric material in the first place. In the second place, analysis of observations for the micro structure and sintering condition at the interface of conductive paste and HDI Cu land by using SEM and energy dispersive X-ray spectrometry (EDX). In addition, mechanical reliabilities, estimated by using structural analysis method and signal transmission properties by way of this buried conductive paste using frequency and time-domain simulation analyses were discussed.. From these results, this advanced vertical interconnect technology with sintered conductive paste and low elastic dielectric has sufficient mechanical reliability and electrical property for passing high-speed signal up to 15 Gbps.
{"title":"Advanced vertical interconnect technology with high density interconnect and conductive paste","authors":"Tsuyoshi Tsunoda, Ryouhei Kasai, Shozo Yuki, N. Ota, Keisuke Sawada, Y. Yamamoto, Y. Fukuoka, S. Sagara","doi":"10.1109/ICEP.2014.6826659","DOIUrl":"https://doi.org/10.1109/ICEP.2014.6826659","url":null,"abstract":"Advanced vertical interconnect technology that combines traditional HDI (high density interconnect) structures feature micro-vias and conductive paste-vias was developed to fabricate multilayer printed circuit board, such as ultra-multilayer printed circuit board like probe card or IC testing board, having excellent electrical performance, mechanical reliability and mass productivity at reasonable cost. This advanced multilayer printed circuit board constituted of high elastic modulus thermosetting dielectric composition with interstitial via holes (IVH) and/or Cu micro-vias (HDI), besides sintered conductive paste-vias buried in low elastic modulus thermosetting dielectric composition. The latter composition will properly act as mechanical buffering layer of vertical interconnection between upper and lower multilayer boards. This paper discuss about manufacturing process factor, that is pre-curing temperature, affecting the optimum electrical performance at the interface of HDI Cu lands and conductive paste with interposing low elastic modulus dielectric material in the first place. In the second place, analysis of observations for the micro structure and sintering condition at the interface of conductive paste and HDI Cu land by using SEM and energy dispersive X-ray spectrometry (EDX). In addition, mechanical reliabilities, estimated by using structural analysis method and signal transmission properties by way of this buried conductive paste using frequency and time-domain simulation analyses were discussed.. From these results, this advanced vertical interconnect technology with sintered conductive paste and low elastic dielectric has sufficient mechanical reliability and electrical property for passing high-speed signal up to 15 Gbps.","PeriodicalId":195433,"journal":{"name":"2014 International Conference on Electronics Packaging (ICEP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115576251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-23DOI: 10.1109/ICEP.2014.6826712
So Ikeda, E. Higurashi, T. Suga, T. Oguchi
Miniaturized polarization sensors integrated with aluminum (Al) nanowire-grid polarizers have been developed for compact optical rotary encoders. The sensor consists of Al wire grid polarizers sandwiched between two glass substrates, an InGaAs photodiode (PD) chip and a Si substrate with a cavity and through silicon vias (TSVs). Two polarizers that can detect two orthogonally polarized components were integrated in a single device. The glass substrates with wire-grid polarizers were vertically stacked on the Si substrate for chip size packaging. Integration of PD chips and sealing were performed using Au-Au surface activated bonding using atmospheric-pressure plasma with mixed gas of Ar and H2 at a relatively low bonding temperature of 150 °C. The feasibility of rotational angle measurement of linear polarizer was demonstrated by differential detection of two orthogonally polarized components.
{"title":"Miniaturized polarization sensors integrated with wire-grid polarizers","authors":"So Ikeda, E. Higurashi, T. Suga, T. Oguchi","doi":"10.1109/ICEP.2014.6826712","DOIUrl":"https://doi.org/10.1109/ICEP.2014.6826712","url":null,"abstract":"Miniaturized polarization sensors integrated with aluminum (Al) nanowire-grid polarizers have been developed for compact optical rotary encoders. The sensor consists of Al wire grid polarizers sandwiched between two glass substrates, an InGaAs photodiode (PD) chip and a Si substrate with a cavity and through silicon vias (TSVs). Two polarizers that can detect two orthogonally polarized components were integrated in a single device. The glass substrates with wire-grid polarizers were vertically stacked on the Si substrate for chip size packaging. Integration of PD chips and sealing were performed using Au-Au surface activated bonding using atmospheric-pressure plasma with mixed gas of Ar and H2 at a relatively low bonding temperature of 150 °C. The feasibility of rotational angle measurement of linear polarizer was demonstrated by differential detection of two orthogonally polarized components.","PeriodicalId":195433,"journal":{"name":"2014 International Conference on Electronics Packaging (ICEP)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114248074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
3-Dimensional JISSO technology is important to realize smaller and more advanced electronic device. The conventional POP (Package on Package) is one of the useful technologies for it; however, it has some problems. For example, using TSV (through silicon via) or solder ball makes some limitations to minimize the package size. To solve these problems, we developed new 3-Dimensional package structure using micropin. In our new structure, several micro pins and electronic components are assembled on the large substrate, and molded together with encapsulation resin, and then cut to individual pieces. In this paper, we introduce this newly developed technology.
{"title":"Novel 3-Dimensional package structure with micro-pins and electronic components","authors":"Nau Negishi, Mikio Nakamura, Takanori Sekido, Tsutomu Nakamura, Yu Kondo","doi":"10.1109/ICEP.2014.6826667","DOIUrl":"https://doi.org/10.1109/ICEP.2014.6826667","url":null,"abstract":"3-Dimensional JISSO technology is important to realize smaller and more advanced electronic device. The conventional POP (Package on Package) is one of the useful technologies for it; however, it has some problems. For example, using TSV (through silicon via) or solder ball makes some limitations to minimize the package size. To solve these problems, we developed new 3-Dimensional package structure using micropin. In our new structure, several micro pins and electronic components are assembled on the large substrate, and molded together with encapsulation resin, and then cut to individual pieces. In this paper, we introduce this newly developed technology.","PeriodicalId":195433,"journal":{"name":"2014 International Conference on Electronics Packaging (ICEP)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114296127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-23DOI: 10.1109/ICEP.2014.6826765
Hiroki Ishihara, K. Oda, Teijiro Ori, K. Goi, K. Ogawa, T. Liow, X. Tu, G. Lo, D. Kwong
10-Gb/s silicon-based Mach-Zehnder modulator is packaged and characterized. The I/O sections of the modulator chip are located at longer-facet sides using bends waveguides for enhancing modulation bandwidth by using short straight configuration of traveling-wave electrodes. Low-insertion loss and high-return-loss optical coupling structure between input/output lenses and the modulator chip is achieved with optical coupling, where both of chip facets and inverted-taper mode-field-convertors are angled with respect to incident light beam. 3-dB electro-optic bandwidth is as high as 12.0-GHz and optical insertion loss is 9-dB or lower. High-contrast eye diagram with an extinction ratio of 13.8-dB is obtained.
{"title":"High-ON/OFF-contrast 10-Gb/s silicon Mach-zehnder modulator in high-speed low-loss package","authors":"Hiroki Ishihara, K. Oda, Teijiro Ori, K. Goi, K. Ogawa, T. Liow, X. Tu, G. Lo, D. Kwong","doi":"10.1109/ICEP.2014.6826765","DOIUrl":"https://doi.org/10.1109/ICEP.2014.6826765","url":null,"abstract":"10-Gb/s silicon-based Mach-Zehnder modulator is packaged and characterized. The I/O sections of the modulator chip are located at longer-facet sides using bends waveguides for enhancing modulation bandwidth by using short straight configuration of traveling-wave electrodes. Low-insertion loss and high-return-loss optical coupling structure between input/output lenses and the modulator chip is achieved with optical coupling, where both of chip facets and inverted-taper mode-field-convertors are angled with respect to incident light beam. 3-dB electro-optic bandwidth is as high as 12.0-GHz and optical insertion loss is 9-dB or lower. High-contrast eye diagram with an extinction ratio of 13.8-dB is obtained.","PeriodicalId":195433,"journal":{"name":"2014 International Conference on Electronics Packaging (ICEP)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116880888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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