Pub Date : 2019-04-24DOI: 10.1109/DDECS.2019.8724662
S. Odintsov, Ludovica Bozzoli, C. D. Sio, L. Sterpone, A. Jutman
Nowadays, increasing demand for High-Performance Systems produces significant growth in usage of Field Programmable Gate Arrays (FPGAs) for different applications thanks to their flexibility and high level of parallelism. Such systems rely on complex multi-layer Printed Circuit Board Assemblies (PCBA)with a few dozens of hidden layers, stacked microvias and high-density interconnects. Along with creating new test challenges, the increasing PCBA complexity elevates the criticality of defects in various subsystems. One of such sub-systems is a Power-Delivery-Network (PDN) with operating margin progressively reduced due to increasingly strict requirements of High-Performance applications. As a consequence, Marginal Defects and process variations in a PDN may create latent problems that will manifest in a particular condition thus compromising the overall system performance and causing malfunctions. In this paper we propose a new FPGA-based non-intrusive method to detect Marginal Defects in a PCBA PDN. The method is based on a monitoring circuit that measures signal delays caused by PDN variations and thus detects relevant anomalies. Additional ad-hoc PDN stress circuits have been developed to validate the measurement technique. Experimental results demonstrating the consistency of the proposed approach are obtained by comparing stress and non-stress scenarios.
{"title":"A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network","authors":"S. Odintsov, Ludovica Bozzoli, C. D. Sio, L. Sterpone, A. Jutman","doi":"10.1109/DDECS.2019.8724662","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724662","url":null,"abstract":"Nowadays, increasing demand for High-Performance Systems produces significant growth in usage of Field Programmable Gate Arrays (FPGAs) for different applications thanks to their flexibility and high level of parallelism. Such systems rely on complex multi-layer Printed Circuit Board Assemblies (PCBA)with a few dozens of hidden layers, stacked microvias and high-density interconnects. Along with creating new test challenges, the increasing PCBA complexity elevates the criticality of defects in various subsystems. One of such sub-systems is a Power-Delivery-Network (PDN) with operating margin progressively reduced due to increasingly strict requirements of High-Performance applications. As a consequence, Marginal Defects and process variations in a PDN may create latent problems that will manifest in a particular condition thus compromising the overall system performance and causing malfunctions. In this paper we propose a new FPGA-based non-intrusive method to detect Marginal Defects in a PCBA PDN. The method is based on a monitoring circuit that measures signal delays caused by PDN variations and thus detects relevant anomalies. Additional ad-hoc PDN stress circuits have been developed to validate the measurement technique. Experimental results demonstrating the consistency of the proposed approach are obtained by comparing stress and non-stress scenarios.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125408465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-16DOI: 10.1109/DDECS.2019.8724647
A. Floridia, Gianmarco Mongano, D. Piumatti, E. Sánchez
Safety-critical applications require to reach high fault coverage figures for on-line testing in order to be compliant with currently used functional safety standards. Nowadays, for meeting these constraints different solutions are adopted by semiconductor manufactures. Such approaches may vary from pure hardware-based mechanisms to software-based ones. Each of these possible solutions presents several advantages and drawbacks, typically: software approaches are less intrusive and have the advantage of reduced test application time compared to hardware ones. Conversely, hardware approaches yield high defect coverage but they are normally invasive and have longer test application time. The aim of this paper is to present a novel Design for Test infrastructure, accessible via software, for enabling a high fault coverage on-line test of arithmetic units within embedded processor cores. The end-goal is to overcome limitations of both hardware- and software-based test approaches, while striving for a low invasive on-line test. Such architecture was implemented on an open source processor, the OpenRISC 1200 and its effectiveness evaluated by means of exhaustive fault injection campaigns.
{"title":"Hybrid on-line self-test architecture for computational units on embedded processor cores","authors":"A. Floridia, Gianmarco Mongano, D. Piumatti, E. Sánchez","doi":"10.1109/DDECS.2019.8724647","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724647","url":null,"abstract":"Safety-critical applications require to reach high fault coverage figures for on-line testing in order to be compliant with currently used functional safety standards. Nowadays, for meeting these constraints different solutions are adopted by semiconductor manufactures. Such approaches may vary from pure hardware-based mechanisms to software-based ones. Each of these possible solutions presents several advantages and drawbacks, typically: software approaches are less intrusive and have the advantage of reduced test application time compared to hardware ones. Conversely, hardware approaches yield high defect coverage but they are normally invasive and have longer test application time. The aim of this paper is to present a novel Design for Test infrastructure, accessible via software, for enabling a high fault coverage on-line test of arithmetic units within embedded processor cores. The end-goal is to overcome limitations of both hardware- and software-based test approaches, while striving for a low invasive on-line test. Such architecture was implemented on an open source processor, the OpenRISC 1200 and its effectiveness evaluated by means of exhaustive fault injection campaigns.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123357230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.1109/DDECS.2019.8724663
Jan Belohoubek, P. Fiser, Jan Schmidt
The security of many digital devices strongly depends on a secret value stored in them. To mitigate security threats, high protection of such a value must be provided. Many attacks against (cryptographic) hardware as well as attack countermeasures were presented recently. As new attacks are invented continuously, it is important to analyze even potential threats to mitigate device vulnerability during its lifetime. In this paper, we report a novel voter-related vulnerability, which can be potentially misused to compromise the secret value stored in an embedded device.
{"title":"Using Voters May Lead to Secret Leakage","authors":"Jan Belohoubek, P. Fiser, Jan Schmidt","doi":"10.1109/DDECS.2019.8724663","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724663","url":null,"abstract":"The security of many digital devices strongly depends on a secret value stored in them. To mitigate security threats, high protection of such a value must be provided. Many attacks against (cryptographic) hardware as well as attack countermeasures were presented recently. As new attacks are invented continuously, it is important to analyze even potential threats to mitigate device vulnerability during its lifetime. In this paper, we report a novel voter-related vulnerability, which can be potentially misused to compromise the secret value stored in an embedded device.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115518856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.1109/DDECS.2019.8724654
E. Valea, M. D. Silva, M. Flottes, G. D. Natale, B. Rouzeyre
Standard test infrastructures, such as IEEE Std. 1149.1 (JTAG), IEEE Std. 1500 and IEEE Std. 1687 (IJTAG), are widely used in nowadays Integrated Circuits (ICs). However, they pose an important security challenge to the designers because of the high controllability and observability they offer through the Test Access Port (TAP). For instance, malicious users can exploit test infrastructures in order to access the internal scan chains of crypto-cores and perform scan attacks. Moreover, these infrastructures connect all the devices of the system to the same network. For this reason, the data sent to a target device are potentially visible to all the others. Consequently, this poses a threat to the confidentiality of data content. The encryption of test data is a countermeasure that has been conceived in order to overcome these threats. In this paper, we propose a new secure version of the JTAG infrastructure, relying on stream-based encryption.
{"title":"Encryption-Based Secure JTAG","authors":"E. Valea, M. D. Silva, M. Flottes, G. D. Natale, B. Rouzeyre","doi":"10.1109/DDECS.2019.8724654","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724654","url":null,"abstract":"Standard test infrastructures, such as IEEE Std. 1149.1 (JTAG), IEEE Std. 1500 and IEEE Std. 1687 (IJTAG), are widely used in nowadays Integrated Circuits (ICs). However, they pose an important security challenge to the designers because of the high controllability and observability they offer through the Test Access Port (TAP). For instance, malicious users can exploit test infrastructures in order to access the internal scan chains of crypto-cores and perform scan attacks. Moreover, these infrastructures connect all the devices of the system to the same network. For this reason, the data sent to a target device are potentially visible to all the others. Consequently, this poses a threat to the confidentiality of data content. The encryption of test data is a countermeasure that has been conceived in order to overcome these threats. In this paper, we propose a new secure version of the JTAG infrastructure, relying on stream-based encryption.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122123507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.1109/ddecs.2019.8724655
{"title":"DDECS 2019 Foreword","authors":"","doi":"10.1109/ddecs.2019.8724655","DOIUrl":"https://doi.org/10.1109/ddecs.2019.8724655","url":null,"abstract":"","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128208101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.1109/DDECS.2019.8724653
Attila Fejér, Z. Nagy, J. Benois-Pineau, P. Szolgay, A. Rugy, J. Domenger
The article describes the first steps to achieve control over a robotic or prosthetic arm based on analysis of visual environment acquired in real-time by video cameras on glasses and on the prosthesis. One of the main goals of the research is to develop a wearable, portable, lightweight, and low power consumption device for visual scene analysis. This paper will discuss the critical steps of its implementation on an FPGA board. We implemented some time-consuming parts of the SFT algorithm needed for the analysis in C/C++ language on TUL PYNQ-Z2 FPGA board. This implementation allows for a low power consumption of the programmable logic part of the system. The obtained value is 0. 274W. Processing capacity is 96.45 images per second on a small wearable size device which allow for the real-time implementation of the whole analysis in the future.
{"title":"FPGA-based SIFT implementation for wearable computing","authors":"Attila Fejér, Z. Nagy, J. Benois-Pineau, P. Szolgay, A. Rugy, J. Domenger","doi":"10.1109/DDECS.2019.8724653","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724653","url":null,"abstract":"The article describes the first steps to achieve control over a robotic or prosthetic arm based on analysis of visual environment acquired in real-time by video cameras on glasses and on the prosthesis. One of the main goals of the research is to develop a wearable, portable, lightweight, and low power consumption device for visual scene analysis. This paper will discuss the critical steps of its implementation on an FPGA board. We implemented some time-consuming parts of the SFT algorithm needed for the analysis in C/C++ language on TUL PYNQ-Z2 FPGA board. This implementation allows for a low power consumption of the programmable logic part of the system. The obtained value is 0. 274W. Processing capacity is 96.45 images per second on a small wearable size device which allow for the real-time implementation of the whole analysis in the future.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127736034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.1109/DDECS.2019.8724648
V. Muresan, M. Abrudean
In this paper, a solution to control the servicing machines of a rotary hearth furnace is presented. The proposed control strategy is based on the usage of a modified cascade control structure. The proposed control solution is augmented with a fault detection system capable to detect the faults which frequently occur in the operation of the D.C. motors used to drive the servicing machines. It is proved through simulation that, in a certain range of faults magnitude, their effect is rejected by the controllers, aspect which makes the proposed control system a fault tolerant one. Also, due to the usage of neural reference model, the faults magnitude can be quantified and when the safety limits are reached, some decisions for reducing the servicing machines operation are automatically generated.
{"title":"Fault Tolerant Control System of the Rotary Hearth Furnace Servicing Machines","authors":"V. Muresan, M. Abrudean","doi":"10.1109/DDECS.2019.8724648","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724648","url":null,"abstract":"In this paper, a solution to control the servicing machines of a rotary hearth furnace is presented. The proposed control strategy is based on the usage of a modified cascade control structure. The proposed control solution is augmented with a fault detection system capable to detect the faults which frequently occur in the operation of the D.C. motors used to drive the servicing machines. It is proved through simulation that, in a certain range of faults magnitude, their effect is rejected by the controllers, aspect which makes the proposed control system a fault tolerant one. Also, due to the usage of neural reference model, the faults magnitude can be quantified and when the safety limits are reached, some decisions for reducing the servicing machines operation are automatically generated.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128643589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.1109/ddecs.2019.8724640
{"title":"DDECS 2019 Sponsors","authors":"","doi":"10.1109/ddecs.2019.8724640","DOIUrl":"https://doi.org/10.1109/ddecs.2019.8724640","url":null,"abstract":"","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129370064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.1109/DDECS.2019.8724650
L. Nagy, D. Arbet, M. Kovác, M. Potocný, V. Stopjaková
The paper addresses a novel topology of ultra low-voltage comparator with rail-to-rail input voltage range and selectable level of hysteresis designed in a standard twin-well 130 nm CMOS technology. The nominal power supply voltage of 0.4 V was used, and the working temperature range was set to the industrial standard from -20 ° to 85 °. The proposed comparator design is intended to work in an energy harvesting system. Hence, low power consumption is the key requirement. The comparator employs bulk-driven transistors in the input stage and operates in so-called current mode. The designed comparator circuit draws less than $5 mu mathrm {A}$ in typical conditions but its function and robustness have been verified across all possible process and temperature corners. The design was submitted to foundry for manufacturing and the measured data can be expected soon.
本文提出了一种新颖的超低电压比较器拓扑结构，采用标准双孔130纳米CMOS技术设计了轨对轨输入电压范围和滞回可选电平。电源标称电压为0.4 V，工作温度范围设定为工业标准-20°~ 85°。所提出的比较器设计旨在在能量收集系统中工作。因此，低功耗是关键要求。比较器在输入级采用体积驱动晶体管，并在所谓的电流模式下工作。所设计的比较器电路在典型条件下功耗小于$5 mu mathrm {A}$，但其功能和鲁棒性已在所有可能的工艺和温度角上得到验证。该设计已提交给铸造厂进行制造，很快就可以得到测量数据。
{"title":"Ultra Low-Voltage Rail-to-Rail Comparator Design in 130 nm CMOS Technology","authors":"L. Nagy, D. Arbet, M. Kovác, M. Potocný, V. Stopjaková","doi":"10.1109/DDECS.2019.8724650","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724650","url":null,"abstract":"The paper addresses a novel topology of ultra low-voltage comparator with rail-to-rail input voltage range and selectable level of hysteresis designed in a standard twin-well 130 nm CMOS technology. The nominal power supply voltage of 0.4 V was used, and the working temperature range was set to the industrial standard from -20 ° to 85 °. The proposed comparator design is intended to work in an energy harvesting system. Hence, low power consumption is the key requirement. The comparator employs bulk-driven transistors in the input stage and operates in so-called current mode. The designed comparator circuit draws less than $5 mu mathrm {A}$ in typical conditions but its function and robustness have been verified across all possible process and temperature corners. The design was submitted to foundry for manufacturing and the measured data can be expected soon.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127649064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.1109/DDECS.2019.8724639
M. Tanweer, K. Halonen
Weareable biomedical devices make it possible to monitor physiological parameters of human beings where physical fitness is critical for their work. However, the motion artifacts corrupt the ambulatory measurements of electrophysiological parameters and it is necessary to detect and eliminate these motion artifacts. The long term measurement and analysis of health parameters require enormous data processing and storage resources on board. It is also challenging to perform sensor fusion of multiple devices and to manage multiple communication channels. This paper describes the development of a wearable hardware platform to measure electrocardiogram (ECG) and electromyogram (EMG) with an additional IMU sensor to detect the motion artifacts. Bringing all the sensors on single platform resolves the sensor fusion problems. The measurements are digitized and sent wirelessly through a bluetooth interface to a remote unit in real-time. Which is capable for the implementation of extensive processing and analysis algorithms to detect the motion artifacts and extract The features of ECG and EMG waveform structures.
{"title":"Development of wearable hardware platform to measure the ECG and EMG with IMU to detect motion artifacts","authors":"M. Tanweer, K. Halonen","doi":"10.1109/DDECS.2019.8724639","DOIUrl":"https://doi.org/10.1109/DDECS.2019.8724639","url":null,"abstract":"Weareable biomedical devices make it possible to monitor physiological parameters of human beings where physical fitness is critical for their work. However, the motion artifacts corrupt the ambulatory measurements of electrophysiological parameters and it is necessary to detect and eliminate these motion artifacts. The long term measurement and analysis of health parameters require enormous data processing and storage resources on board. It is also challenging to perform sensor fusion of multiple devices and to manage multiple communication channels. This paper describes the development of a wearable hardware platform to measure electrocardiogram (ECG) and electromyogram (EMG) with an additional IMU sensor to detect the motion artifacts. Bringing all the sensors on single platform resolves the sensor fusion problems. The measurements are digitized and sent wirelessly through a bluetooth interface to a remote unit in real-time. Which is capable for the implementation of extensive processing and analysis algorithms to detect the motion artifacts and extract The features of ECG and EMG waveform structures.","PeriodicalId":197053,"journal":{"name":"2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117111934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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