Pub Date : 2015-06-18DOI: 10.1109/ECS.2015.7124794
A. Manikandan, J. Ajayan, C. Kavin, S. Karthick, D. Nirmal
Dynamic comparators are widely being used in high speed Analog to Digital Converters (ADC) such as flash ADC's because of its low voltage, low power, high speed and area efficiency. In this paper, an analysis on the delay and power performance of strained silicon CMOS technology based dynamic comparators will be presented. To compare the performance of dynamic comparators, test circuits were simulated using 45nm high performance and low power technologies with a supply voltage of 0.8V using spice tools. Using circuit simulations, the overall improved characteristics of double tail dynamic comparator are demonstrated in comparison to those of the traditional as well as several state of the art dynamic comparators. The simulation results shows that in the dynamic double tail comparator both the power consumption and the time delay are reduced significantly.
{"title":"A comparative study of high performance dynamic comparators using strained silicon technology","authors":"A. Manikandan, J. Ajayan, C. Kavin, S. Karthick, D. Nirmal","doi":"10.1109/ECS.2015.7124794","DOIUrl":"https://doi.org/10.1109/ECS.2015.7124794","url":null,"abstract":"Dynamic comparators are widely being used in high speed Analog to Digital Converters (ADC) such as flash ADC's because of its low voltage, low power, high speed and area efficiency. In this paper, an analysis on the delay and power performance of strained silicon CMOS technology based dynamic comparators will be presented. To compare the performance of dynamic comparators, test circuits were simulated using 45nm high performance and low power technologies with a supply voltage of 0.8V using spice tools. Using circuit simulations, the overall improved characteristics of double tail dynamic comparator are demonstrated in comparison to those of the traditional as well as several state of the art dynamic comparators. The simulation results shows that in the dynamic double tail comparator both the power consumption and the time delay are reduced significantly.","PeriodicalId":202856,"journal":{"name":"2015 2nd International Conference on Electronics and Communication Systems (ICECS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125279236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-18DOI: 10.1109/ECS.2015.7124848
A. Manikandan, J. Ajayan, C. K. Arasan, S. Karthick, K. Vivek
The rapid growth in CMOS technology with the shrinking device size towards 22 nm has allowed for placement of billions of transistors on a single microprocessor chip. To achieve very high system performance, domino logic styles are widely employed in high performance VLSI chips together with aggressive technology scaling. Comparators are widely used in central processing units (CPUs) and microcontrollers (MCUs). In this paper, a 64 bit comparator circuit is proposed which has a lower leakage and higher noise immunity without dramatic speed degradation compared to high speed domino logic, leakage current replica keeper domino logic and diode footed domino logic. This circuit is based on comparison of mirrored current of the pull up network (PUN) with its worst case leakage current. Current comparison based domino technique reduces the parasitic capacitance on the dynamic node using a small keeper transistor, which reduces the contention current, power consumption and also the delay of the circuit. Simulation results of 64 bit comparator designed using a 22nm high performance predictive technology model demonstrate 51% power reduction compared to a standard domino circuits for 64 bit comparator.
{"title":"High speed low power 64-bit comparator designed using current comparison based domino logic","authors":"A. Manikandan, J. Ajayan, C. K. Arasan, S. Karthick, K. Vivek","doi":"10.1109/ECS.2015.7124848","DOIUrl":"https://doi.org/10.1109/ECS.2015.7124848","url":null,"abstract":"The rapid growth in CMOS technology with the shrinking device size towards 22 nm has allowed for placement of billions of transistors on a single microprocessor chip. To achieve very high system performance, domino logic styles are widely employed in high performance VLSI chips together with aggressive technology scaling. Comparators are widely used in central processing units (CPUs) and microcontrollers (MCUs). In this paper, a 64 bit comparator circuit is proposed which has a lower leakage and higher noise immunity without dramatic speed degradation compared to high speed domino logic, leakage current replica keeper domino logic and diode footed domino logic. This circuit is based on comparison of mirrored current of the pull up network (PUN) with its worst case leakage current. Current comparison based domino technique reduces the parasitic capacitance on the dynamic node using a small keeper transistor, which reduces the contention current, power consumption and also the delay of the circuit. Simulation results of 64 bit comparator designed using a 22nm high performance predictive technology model demonstrate 51% power reduction compared to a standard domino circuits for 64 bit comparator.","PeriodicalId":202856,"journal":{"name":"2015 2nd International Conference on Electronics and Communication Systems (ICECS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132333044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-18DOI: 10.1109/ECS.2015.7125019
A. N. Subramonium, Prakhyath Shetty, M. Kumar
In this paper the more precise mathematical modeling of Permanent Magnet Brushless DC Motor (PMBLDC) has been presented. This is required for accurate real time applications of PMBDLC drive. The electronic and communication system of this motor drive is a power processing unit (PPU). The technological growth of the 21st century in microelectronics and control has resulted in powerful linear integrated circuits, microcontrollers and digital signal processors. In addition, the development in semiconductor technology also made it possible to significantly handle the voltage and current capabilities and the switching speeds of semiconductor devices which are the integral part of the Power Processing Unit (PPU). The Digital Signal Processors (DSPs) are used for real-time control. This requires efficient performance of the control for which steady state and transient model of the PMBLDC motor are necessary. The developed model is simulated using Matlab/ Simulink to confer the operating behavior of the drive prior to the implementation.
{"title":"Closed loop control system modeling of Permanent Magnet Brushless DC Motor","authors":"A. N. Subramonium, Prakhyath Shetty, M. Kumar","doi":"10.1109/ECS.2015.7125019","DOIUrl":"https://doi.org/10.1109/ECS.2015.7125019","url":null,"abstract":"In this paper the more precise mathematical modeling of Permanent Magnet Brushless DC Motor (PMBLDC) has been presented. This is required for accurate real time applications of PMBDLC drive. The electronic and communication system of this motor drive is a power processing unit (PPU). The technological growth of the 21st century in microelectronics and control has resulted in powerful linear integrated circuits, microcontrollers and digital signal processors. In addition, the development in semiconductor technology also made it possible to significantly handle the voltage and current capabilities and the switching speeds of semiconductor devices which are the integral part of the Power Processing Unit (PPU). The Digital Signal Processors (DSPs) are used for real-time control. This requires efficient performance of the control for which steady state and transient model of the PMBLDC motor are necessary. The developed model is simulated using Matlab/ Simulink to confer the operating behavior of the drive prior to the implementation.","PeriodicalId":202856,"journal":{"name":"2015 2nd International Conference on Electronics and Communication Systems (ICECS)","volume":"78 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121013771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-18DOI: 10.1109/ECS.2015.7125045
K. Malarvizhi, Madhusudan Kumar
SRM motors due to simple mechanical design have significant role in high speed operations and hence require faster control of rotor speed and minimized torque ripple. Proposed work uses Particle Swarm Optimization (PSO) for the tuning of the Emotional Learning controller (BELBIC). PSO is used for tuning the training coefficients of the BELBIC and maximizing the reward of the system to provide minimized speed settling time. The simulation is performed on an 8/6 SRM in MATLAB r2012a version. The operation of 8/6 SRM motor is compared by using a simple PID controller, a BELBIC Controller and a PSO tuned BELBIC controller. PSO tuned BELBIC controller shows higher operational efficiency compared to the other two methods.
{"title":"Particle Swarm Optimization tuned BELBIC controller for 8/6 SRM operation","authors":"K. Malarvizhi, Madhusudan Kumar","doi":"10.1109/ECS.2015.7125045","DOIUrl":"https://doi.org/10.1109/ECS.2015.7125045","url":null,"abstract":"SRM motors due to simple mechanical design have significant role in high speed operations and hence require faster control of rotor speed and minimized torque ripple. Proposed work uses Particle Swarm Optimization (PSO) for the tuning of the Emotional Learning controller (BELBIC). PSO is used for tuning the training coefficients of the BELBIC and maximizing the reward of the system to provide minimized speed settling time. The simulation is performed on an 8/6 SRM in MATLAB r2012a version. The operation of 8/6 SRM motor is compared by using a simple PID controller, a BELBIC Controller and a PSO tuned BELBIC controller. PSO tuned BELBIC controller shows higher operational efficiency compared to the other two methods.","PeriodicalId":202856,"journal":{"name":"2015 2nd International Conference on Electronics and Communication Systems (ICECS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114974958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-18DOI: 10.1109/ECS.2015.7124940
R. Ravanya, S. Ramya
A biometric system makes a pattern recognition decision in accordance with the biometric features extracted from a human being. This paper presents a text-independent speaker Verification system using support vector machines (SVMs) is to identify the speaker by listening to the voice of the speaker. Thus speaker verification is to determine whether a test utterance is spoken by a target speaker and also causes large power dissipation. In this paper, Spurious Power Suppression Technique (SPST) is utilized to overcome these issues, which uses a detection logic circuit to detect the effective data range of arithmetic units, e.g., adders or multipliers. This SPST is used to reduce the power dissipation when compared to previous method.
{"title":"Low power SVM module using spurious power suppression technique","authors":"R. Ravanya, S. Ramya","doi":"10.1109/ECS.2015.7124940","DOIUrl":"https://doi.org/10.1109/ECS.2015.7124940","url":null,"abstract":"A biometric system makes a pattern recognition decision in accordance with the biometric features extracted from a human being. This paper presents a text-independent speaker Verification system using support vector machines (SVMs) is to identify the speaker by listening to the voice of the speaker. Thus speaker verification is to determine whether a test utterance is spoken by a target speaker and also causes large power dissipation. In this paper, Spurious Power Suppression Technique (SPST) is utilized to overcome these issues, which uses a detection logic circuit to detect the effective data range of arithmetic units, e.g., adders or multipliers. This SPST is used to reduce the power dissipation when compared to previous method.","PeriodicalId":202856,"journal":{"name":"2015 2nd International Conference on Electronics and Communication Systems (ICECS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116417242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-18DOI: 10.1109/ECS.2015.7124972
P. Karthigeyan, M. S. Raja, M. Sheeba, R. Gnanaselvam, N. Raj
Most of the pollution issues created in power system is due to the power quality problems like faults, harmonics etc. In this paper a grid connected fixed speed wind turbine induction generator subjected to asymmetric fault gets attenuated by unified power flow controller (UPFC) as it compensates the positive and negative sequence voltages thereby reducing the torque oscillations and improving the life time of the drain. It is the combination of static compensator (STATCOM) and static synchronous series compensator (SSSC). The control theory is based on vector control- dq(direct quadrature axis) reference frame fed PI, hysteresis control and fuzzy logic control using DSOGI-PLL(Dual second order generalized integrator- Phase locked loop). The proposed system is implemented using MATLAB / SIMULINK platform with and without Unified power flow controller. The effect of UPFC for fixed speed windturbine under faults is analysed using the above three controllers and its performance is evaluated.
{"title":"Optimization of power quality problem for a windturbine fixed speed induction generatorunder asymmetric faultsusing UPFC fed vector control-PI, hysteresis and fuzzy logic","authors":"P. Karthigeyan, M. S. Raja, M. Sheeba, R. Gnanaselvam, N. Raj","doi":"10.1109/ECS.2015.7124972","DOIUrl":"https://doi.org/10.1109/ECS.2015.7124972","url":null,"abstract":"Most of the pollution issues created in power system is due to the power quality problems like faults, harmonics etc. In this paper a grid connected fixed speed wind turbine induction generator subjected to asymmetric fault gets attenuated by unified power flow controller (UPFC) as it compensates the positive and negative sequence voltages thereby reducing the torque oscillations and improving the life time of the drain. It is the combination of static compensator (STATCOM) and static synchronous series compensator (SSSC). The control theory is based on vector control- dq(direct quadrature axis) reference frame fed PI, hysteresis control and fuzzy logic control using DSOGI-PLL(Dual second order generalized integrator- Phase locked loop). The proposed system is implemented using MATLAB / SIMULINK platform with and without Unified power flow controller. The effect of UPFC for fixed speed windturbine under faults is analysed using the above three controllers and its performance is evaluated.","PeriodicalId":202856,"journal":{"name":"2015 2nd International Conference on Electronics and Communication Systems (ICECS)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115432385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-18DOI: 10.1109/ECS.2015.7124983
Ranjeet Kumar, Anil Kumar
An Electrocardiogram (ECG) signal compression becomes more area of interest due to increases demand of tel-e-healthcare system. In this manuscript, dual tree discrete wavelet decomposition (DT-DWT) based ECG signal compression is exploited using zero run-length coding techniques. The main advancement of proposed technique, its sensitivity of generating sparse data set that helps to enhance compression performance of system. Performance of method evaluated through compression ratio and percentage root-mean square difference and quality evaluated using the cross correlation between the original and reconstructed MIT-BIH records. As discuses in results, proposed method is good as compare to earlier developed techniques in term of compression.
{"title":"Dual tree DWT analysis based electrocardiogram signal compression using zero coding technique","authors":"Ranjeet Kumar, Anil Kumar","doi":"10.1109/ECS.2015.7124983","DOIUrl":"https://doi.org/10.1109/ECS.2015.7124983","url":null,"abstract":"An Electrocardiogram (ECG) signal compression becomes more area of interest due to increases demand of tel-e-healthcare system. In this manuscript, dual tree discrete wavelet decomposition (DT-DWT) based ECG signal compression is exploited using zero run-length coding techniques. The main advancement of proposed technique, its sensitivity of generating sparse data set that helps to enhance compression performance of system. Performance of method evaluated through compression ratio and percentage root-mean square difference and quality evaluated using the cross correlation between the original and reconstructed MIT-BIH records. As discuses in results, proposed method is good as compare to earlier developed techniques in term of compression.","PeriodicalId":202856,"journal":{"name":"2015 2nd International Conference on Electronics and Communication Systems (ICECS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116045727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-18DOI: 10.1109/ECS.2015.7124846
G. Ram, P. Chakravorty, D. Mandal, R. Kar, S. Ghoshal
In this paper, a new evolutionary optimization algorithm named gravitational search algorithm with wavelet mutation (GSAWM) is adopted for optimal design of hyper beam pattern of linear antenna arrays. Hyper beam is derived from sum and difference beam patterns associated with hyper beam exponent parameter for the array. In GSAWM, particles are considered as objects and their performances are measured by their masses. All these objects attract each other by gravity forces, and these forces produce global movements of all objects towards the objects with heavier masses. GSAWM guarantees the exploitation step of the algorithm and it is apparently free from premature convergence. Extensive simulation results justify superior optimization capability of GSAWM over the aforementioned optimization techniques. By optimization of current excitation weights and uniform inter-element spacing, GSAWM achieves optimized hyper beam with much greater reduction in side lobe level (SLL), improved directivity and much more improved first null beam width (FNBW), keeping the same value of hyper beam exponent. The whole simulation experiment has been performed for 10-, 14-, and 20-element linear antenna arrays.
{"title":"GSAWM for beamforming and directivity of linear antenna arrays","authors":"G. Ram, P. Chakravorty, D. Mandal, R. Kar, S. Ghoshal","doi":"10.1109/ECS.2015.7124846","DOIUrl":"https://doi.org/10.1109/ECS.2015.7124846","url":null,"abstract":"In this paper, a new evolutionary optimization algorithm named gravitational search algorithm with wavelet mutation (GSAWM) is adopted for optimal design of hyper beam pattern of linear antenna arrays. Hyper beam is derived from sum and difference beam patterns associated with hyper beam exponent parameter for the array. In GSAWM, particles are considered as objects and their performances are measured by their masses. All these objects attract each other by gravity forces, and these forces produce global movements of all objects towards the objects with heavier masses. GSAWM guarantees the exploitation step of the algorithm and it is apparently free from premature convergence. Extensive simulation results justify superior optimization capability of GSAWM over the aforementioned optimization techniques. By optimization of current excitation weights and uniform inter-element spacing, GSAWM achieves optimized hyper beam with much greater reduction in side lobe level (SLL), improved directivity and much more improved first null beam width (FNBW), keeping the same value of hyper beam exponent. The whole simulation experiment has been performed for 10-, 14-, and 20-element linear antenna arrays.","PeriodicalId":202856,"journal":{"name":"2015 2nd International Conference on Electronics and Communication Systems (ICECS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125301631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-18DOI: 10.1109/ECS.2015.7124917
A. Abinaya, S. Sivaranjani
Power reduction plays a vital role in VLSI design. Multi-bit flip-flop is an efficient method for clock power reduction. This method is to eliminate the redundant inverters by merging some flip-flops into multi-bit flip-flops. This multi-bit flip-flops can share the drive strength, dynamic power, area of the inverter chain and can even save the clock network power and facilitate the skew control. Firstly flip-flops that can be merged are identified based on synchronous clock signal and then a combination table is built to define the possible combination of flip-flops and finally a hierarchical way is used to merge flip-flops.
{"title":"Efficient flip-flop merging technique for clock power reduction","authors":"A. Abinaya, S. Sivaranjani","doi":"10.1109/ECS.2015.7124917","DOIUrl":"https://doi.org/10.1109/ECS.2015.7124917","url":null,"abstract":"Power reduction plays a vital role in VLSI design. Multi-bit flip-flop is an efficient method for clock power reduction. This method is to eliminate the redundant inverters by merging some flip-flops into multi-bit flip-flops. This multi-bit flip-flops can share the drive strength, dynamic power, area of the inverter chain and can even save the clock network power and facilitate the skew control. Firstly flip-flops that can be merged are identified based on synchronous clock signal and then a combination table is built to define the possible combination of flip-flops and finally a hierarchical way is used to merge flip-flops.","PeriodicalId":202856,"journal":{"name":"2015 2nd International Conference on Electronics and Communication Systems (ICECS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125008835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-18DOI: 10.1109/ECS.2015.7124991
M. Geethananda, Z. C. Alex, K. Shambavi
A planar multi-ring monopole antenna for ultra wide band applications is presented in this paper. The proposed antenna is designed using concentric rings of width 1.3 mm which leads to improved band width, radiation efficiency and reduced size. The proposed antenna size is 30*30*1.6 mm3 which operates over a frequency range of 2.6 to 13.5 GHz. The radiation pattern is consistent in UWB range which is bidirectional in elevation plane and omnidirectional in azimuth plane. The radiation efficiency of the proposed antenna is 94.6%.
{"title":"Design of planar multi-ring monopole antenna for UWB applications","authors":"M. Geethananda, Z. C. Alex, K. Shambavi","doi":"10.1109/ECS.2015.7124991","DOIUrl":"https://doi.org/10.1109/ECS.2015.7124991","url":null,"abstract":"A planar multi-ring monopole antenna for ultra wide band applications is presented in this paper. The proposed antenna is designed using concentric rings of width 1.3 mm which leads to improved band width, radiation efficiency and reduced size. The proposed antenna size is 30*30*1.6 mm3 which operates over a frequency range of 2.6 to 13.5 GHz. The radiation pattern is consistent in UWB range which is bidirectional in elevation plane and omnidirectional in azimuth plane. The radiation efficiency of the proposed antenna is 94.6%.","PeriodicalId":202856,"journal":{"name":"2015 2nd International Conference on Electronics and Communication Systems (ICECS)","volume":" 36","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120827387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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