Pub Date : 1994-07-18DOI: 10.1109/HKEDM.1994.395131
T. She, C. Shu
Optoelectronic exclusive-OR and exclusive-NOR gates have been demonstrated with a device structure incorporating a composite pair of GaAs photodetectors. Special optical pulse trains were constructed to test the functionality of the logic units. Electrical output from the devices was used to drive a pre-biased laser diode to produce an optical output signal. A time response faster than 400 ps with an on-off contrast ratio of 19 dB has been obtained. In addition, a 2 to 4 decoder was proposed as a means for high speed optical addressing.<>
{"title":"Optoelectronic logic devices implemented on GaAs photodetectors","authors":"T. She, C. Shu","doi":"10.1109/HKEDM.1994.395131","DOIUrl":"https://doi.org/10.1109/HKEDM.1994.395131","url":null,"abstract":"Optoelectronic exclusive-OR and exclusive-NOR gates have been demonstrated with a device structure incorporating a composite pair of GaAs photodetectors. Special optical pulse trains were constructed to test the functionality of the logic units. Electrical output from the devices was used to drive a pre-biased laser diode to produce an optical output signal. A time response faster than 400 ps with an on-off contrast ratio of 19 dB has been obtained. In addition, a 2 to 4 decoder was proposed as a means for high speed optical addressing.<<ETX>>","PeriodicalId":206109,"journal":{"name":"1994 IEEE Hong Kong Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130860050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-07-18DOI: 10.1109/HKEDM.1994.395136
T. Weng
A numerical method for calculating the I-V characteristics of a GaAs MESFET with ion implanted layer is presented. This method is based on the finding of the channel conductance as a function of the voltage drop across the metal-semiconductor junction which in turn is related to the depletion depth of the active layer through the solution of Poisson's equation.<>
{"title":"Calculation of I-V curves of a GaAs MESFET with nonuniform channel doping by means of numerical integration","authors":"T. Weng","doi":"10.1109/HKEDM.1994.395136","DOIUrl":"https://doi.org/10.1109/HKEDM.1994.395136","url":null,"abstract":"A numerical method for calculating the I-V characteristics of a GaAs MESFET with ion implanted layer is presented. This method is based on the finding of the channel conductance as a function of the voltage drop across the metal-semiconductor junction which in turn is related to the depletion depth of the active layer through the solution of Poisson's equation.<<ETX>>","PeriodicalId":206109,"journal":{"name":"1994 IEEE Hong Kong Electron Devices Meeting","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121227144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-07-18DOI: 10.1109/HKEDM.1994.395140
K. Wu, Philip C. H. Chan
We have developed a methodology to convert polygon-based full-custom bulk CMOS cells to SOI/CMOS. This methodology is implemented using the Cadence Design Systems Virtuoso environment. We have demonstrated the methodology by converting the Orbit Scalable CMOSN standard cells. The results are quite good for small cells. However, for complex and highly optimized cells, this methodology may lead to a slight increase in the cell area. We have also demonstrated that this methodology can also be applied to further reduce the cell areas if the SOI/CMOS cells are resigned to take advantage of the low-power and high-performance capability of SOI/CMOS.<>
我们开发了一种将基于多边形的全定制体CMOS电池转换为SOI/CMOS的方法。该方法是使用Cadence Design Systems Virtuoso环境实现的。我们通过转换轨道可扩展CMOSN标准单元来演示该方法。对于小细胞来说，结果相当不错。然而，对于复杂和高度优化的细胞，这种方法可能会导致细胞面积的轻微增加。我们还证明，如果SOI/CMOS电池能够利用SOI/CMOS的低功耗和高性能，那么这种方法也可以应用于进一步减小电池面积。
{"title":"A methodology for converting polygon based standard cell from bulk CMOS to SOI","authors":"K. Wu, Philip C. H. Chan","doi":"10.1109/HKEDM.1994.395140","DOIUrl":"https://doi.org/10.1109/HKEDM.1994.395140","url":null,"abstract":"We have developed a methodology to convert polygon-based full-custom bulk CMOS cells to SOI/CMOS. This methodology is implemented using the Cadence Design Systems Virtuoso environment. We have demonstrated the methodology by converting the Orbit Scalable CMOSN standard cells. The results are quite good for small cells. However, for complex and highly optimized cells, this methodology may lead to a slight increase in the cell area. We have also demonstrated that this methodology can also be applied to further reduce the cell areas if the SOI/CMOS cells are resigned to take advantage of the low-power and high-performance capability of SOI/CMOS.<<ETX>>","PeriodicalId":206109,"journal":{"name":"1994 IEEE Hong Kong Electron Devices Meeting","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124317426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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