Pub Date : 1900-01-01DOI: 10.2312/EGGH/EGGH87/239-249
M. Mériaux
The aim of this paper is to provide some refiexions and partial results about cellular architectures for image synthesis and graphics. As some steps of image synthesis involve a long processing time, quite incompatible with interactivity, a natural solution consists in parallel processing. Though a lot of work has been done about cellular hardware, only a little exists about cellular graphic algorithms and hardware.
{"title":"Cellular Architectures and Algorithms for Image Synthesis","authors":"M. Mériaux","doi":"10.2312/EGGH/EGGH87/239-249","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH87/239-249","url":null,"abstract":"The aim of this paper is to provide some refiexions and partial results about cellular architectures for image synthesis and graphics. As some steps of image synthesis involve a long processing time, quite incompatible with interactivity, a natural solution consists in parallel processing. Though a lot of work has been done about cellular hardware, only a little exists about cellular graphic algorithms and hardware.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131815746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.2312/EGGH/EGGH88/121-140
Bengt-Olaf Schneider, U. Claussen
This paper gives a short introduction into the field of computer image generation in hardware. It discusses the two main approaches, namely partitioning in Image space and In object space. Based on the object space partitioning approach we have defined the PROOF architecture. PROOF is a system that aims at high performance and high quality rendering of raster images. High performance means that up to 30 pictures are generated in one second. The pictures are shaded and anti-aliased, giving the images a high degree of realism. The architecture comprises tnree stages which are responsible for hidden surface removal, shading, and filtering respectively. The first of these stages is a pipeline of object processors. Each of these processors stores and scan converts one object Furthermore, It interpolates the depth and the normal vector across the Object. Each object processor is able to handle objects of a certain primitive type. The specialization of an object processor to a certain primitive type is encapsulated in a Single block called primitive processor. The output of the object processor pipeline is the input to a stage for shading. The illumination model employed takes into account both diffuse and specular reflections. The paper reviews Gouraud and Phong shading with regard to their suitability for a hardware implementation. The final stage of the PROOF system is formed by a stage for filtering the colours of those objects that contribute to a pixel. This done by constructing a subpixel mask and filtering across an area of 2×2 pixels. At the end the paper briefly reports on the current state of the project.
{"title":"PROOF: An Architecture for Rendering in Object Space","authors":"Bengt-Olaf Schneider, U. Claussen","doi":"10.2312/EGGH/EGGH88/121-140","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH88/121-140","url":null,"abstract":"This paper gives a short introduction into the field of computer image generation in hardware. It discusses the two main approaches, namely partitioning in Image space and In object space. Based on the object space partitioning approach we have defined the PROOF architecture. PROOF is a system that aims at high performance and high quality rendering of raster images. High performance means that up to 30 pictures are generated in one second. The pictures are shaded and anti-aliased, giving the images a high degree of realism. The architecture comprises tnree stages which are responsible for hidden surface removal, shading, and filtering respectively. \u0000 \u0000The first of these stages is a pipeline of object processors. Each of these processors stores and scan converts one object Furthermore, It interpolates the depth and the normal vector across the Object. Each object processor is able to handle objects of a certain primitive type. The specialization of an object processor to a certain primitive type is encapsulated in a Single block called primitive processor. \u0000 \u0000The output of the object processor pipeline is the input to a stage for shading. The illumination model employed takes into account both diffuse and specular reflections. The paper reviews Gouraud and Phong shading with regard to their suitability for a hardware implementation. \u0000 \u0000The final stage of the PROOF system is formed by a stage for filtering the colours of those objects that contribute to a pixel. This done by constructing a subpixel mask and filtering across an area of 2×2 pixels. \u0000 \u0000At the end the paper briefly reports on the current state of the project.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127946538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.2312/EGGH/EGGH88/171-182
S. Molnar
Described is a hardware architecture for combining the outputs of a number of z-buffer rendering engines to achieve higher performance than is possible with a single renderer. It allows a combination of renderers to achieve the same price/ performance ratio as the individual renderers that compose it, and can be extended to create systems with arbitrarily high performance. The described architecture is based on a fusion of scan-line rendering and the conventional z-buffer algorithm. The frame buffers of several z-buffer engines are modified to scan out z-values as well as color values. Multiplexing devices combine the z/color streams from each pair of frame-buffers. These z/color streams are then combined by further multiplexers, creating a binary tree that funnels the z/color information from the many conventional frame buffers into a single z/color stream. The color stream is then used to dnve a standard display device. The proposed architecture allows rendering rates of millions and even tens of millions of polygons per second. The basic architecture can be extended with additional hardware to perform antialiasing and texture-mapping.
{"title":"Combining Z-buffer Engines for Higher-Speed Rendering","authors":"S. Molnar","doi":"10.2312/EGGH/EGGH88/171-182","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH88/171-182","url":null,"abstract":"Described is a hardware architecture for combining the outputs of a number of z-buffer rendering engines to achieve higher performance than is possible with a single renderer. It allows a combination of renderers to achieve the same price/ performance ratio as the individual renderers that compose it, and can be extended to create systems with arbitrarily high performance. \u0000 \u0000The described architecture is based on a fusion of scan-line rendering and the conventional z-buffer algorithm. The frame buffers of several z-buffer engines are modified to scan out z-values as well as color values. Multiplexing devices combine the z/color streams from each pair of frame-buffers. These z/color streams are then combined by further multiplexers, creating a binary tree that funnels the z/color information from the many conventional frame buffers into a single z/color stream. The color stream is then used to dnve a standard display device. \u0000 \u0000The proposed architecture allows rendering rates of millions and even tens of millions of polygons per second. The basic architecture can be extended with additional hardware to perform antialiasing and texture-mapping.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116269983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.2312/EGGH/EGGH88/183-199
Christopher D. Shaw, Mark W. Green, J. Schaeffer
This paper describes a new parallel architecture for performing high-speed raster graphics. A central host broadcasts graphical objects to a number of identical graphics processors Each graphics processor produces a raster depicting Its graphical object on a transparent black background. and passes the raster to a leaf of a tree of VLSI processors called Compositors. Each Compositor combines a pair of rasters, performing anti-aliased hidden surface removal, and passes the composed raster to the next level of the tree, Appearing at the root of the tree is the final raster containing all objects at the correct depth with hidden surfaces removed. This paper gives an outline of the algorithm by Duff that the Compositor Will implement The algorithm proves to be too complex for our implementation technology, so a modification of Duff's algorithm is introduced. The high-level design of the dataflow part of the VLSI chip which implements this modified algorithm is then presented, followed by performance simulations and conclusions.
{"title":"A VLSI Architecture for Image Composition","authors":"Christopher D. Shaw, Mark W. Green, J. Schaeffer","doi":"10.2312/EGGH/EGGH88/183-199","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH88/183-199","url":null,"abstract":"This paper describes a new parallel architecture for performing high-speed raster graphics. A central host broadcasts graphical objects to a number of identical graphics processors Each graphics processor produces a raster depicting Its graphical object on a transparent black background. and passes the raster to a leaf of a tree of VLSI processors called Compositors. Each Compositor combines a pair of rasters, performing anti-aliased hidden surface removal, and passes the composed raster to the next level of the tree, Appearing at the root of the tree is the final raster containing all objects at the correct depth with hidden surfaces removed. \u0000 \u0000This paper gives an outline of the algorithm by Duff that the Compositor Will implement The algorithm proves to be too complex for our implementation technology, so a modification of Duff's algorithm is introduced. The high-level design of the dataflow part of the VLSI chip which implements this modified algorithm is then presented, followed by performance simulations and conclusions.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129708221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.2312/EGGH/EGGH91/157-174
H. Ackermann, C. Hornung
We present an architecture for a high-performance programmable rendering engine. This chip or chip-set will be able to deliver one Gouraud-shaded, z-buffered, texturemodulated and alpha-blended pixel every clock cycle. Focus of the paper is the derivation of the architecture of the pixel processing block from the applied algorithms.
{"title":"An Architecture for a High Performance Rendering Engine","authors":"H. Ackermann, C. Hornung","doi":"10.2312/EGGH/EGGH91/157-174","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH91/157-174","url":null,"abstract":"We present an architecture for a high-performance programmable rendering engine. This chip or chip-set will be able to deliver one Gouraud-shaded, z-buffered, texturemodulated and alpha-blended pixel every clock cycle. Focus of the paper is the derivation of the architecture of the pixel processing block from the applied algorithms.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"233 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123041015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.2312/EGGH/EGGH86/075-082
F. Jansen
Constructive Solid Geometry (CSG) is a solid modeling representation that defines objects as Boolean combinations of primitive solids. For the display of such objects, both the visibility problem and the problem of combining the primitive solids into one composite object have to be solved. Recently, several CSG hidden surface algorithms have been published that reduce these two problems to a combination of simple depth comparisons and logical operations at the pixel level that can be performed in VLSI hardware display systems. An overview of these algorithms is given. Furthermore, a CSG depth-buffer algorithm is presented that combines these algorithms.
{"title":"CSG Hidden Surface Algorithms for VLSI Hardware Systems","authors":"F. Jansen","doi":"10.2312/EGGH/EGGH86/075-082","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH86/075-082","url":null,"abstract":"Constructive Solid Geometry (CSG) is a solid modeling representation that defines objects as Boolean combinations of primitive solids. For the display of such objects, both the visibility problem and the problem of combining the primitive solids into one composite object have to be solved. Recently, several CSG hidden surface algorithms have been published that reduce these two problems to a combination of simple depth comparisons and logical operations at the pixel level that can be performed in VLSI hardware display systems. An overview of these algorithms is given. Furthermore, a CSG depth-buffer algorithm is presented that combines these algorithms.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128042618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.2312/EGGH/EGGH87/137-152
Varol Akman, P. Hagen, A. Kuijk
Raster graphics, while good at achieving realistic and cost-effective image generation, lacks useful (e.g. high-level) and fast (e.g. almost real-time) interaction facilities. One may try to speed up the entire classical image generation pipeline using much processing power but this would clearly lessen the advantages of raster workstations as popular, relatively inexpensive devices. This paper continues our work in restructuring the functional model (first formulated by Ingrid Carlbom) for high-performance architectures. Central to our approach is a visible concern about the underlying data structures used to represent the geometric objects. This originates from the conviction that only through careful design of appropriate graphics data structures and algorithms one can profitably map software tasks into hardware, specifically VLSI. Here we elaborate on a novel object description scheme called "pattern representation" and its envisioned usage. Our work is decidedly in contrast with several current research efforts in the area of graphics hardware where it is commonplace to simply put several processors into a cooperative effort to share the total burden, with each processor taking responsibility for part of the work.
{"title":"A Vector-like Architecture for Raster Graphics","authors":"Varol Akman, P. Hagen, A. Kuijk","doi":"10.2312/EGGH/EGGH87/137-152","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH87/137-152","url":null,"abstract":"Raster graphics, while good at achieving realistic and cost-effective image generation, lacks useful (e.g. high-level) and fast (e.g. almost real-time) interaction facilities. One may try to speed up the entire classical image generation pipeline using much processing power but this would clearly lessen the advantages of raster workstations as popular, relatively inexpensive devices. This paper continues our work in restructuring the functional model (first formulated by Ingrid Carlbom) for high-performance architectures. Central to our approach is a visible concern about the underlying data structures used to represent the geometric objects. This originates from the conviction that only through careful design of appropriate graphics data structures and algorithms one can profitably map software tasks into hardware, specifically VLSI. Here we elaborate on a novel object description scheme called \"pattern representation\" and its envisioned usage. Our work is decidedly in contrast with several current research efforts in the area of graphics hardware where it is commonplace to simply put several processors into a cooperative effort to share the total burden, with each processor taking responsibility for part of the work.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131682617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.2312/EGGH/EGGH87/065-073
F. Dévai
Parallel algorithms are given for the exact solution of the hidden-line problem. Most of the parallel algorithms proposed for visibility problems in the literature give approximate solutions. and thus cannot yield an upper bound on the complexity of the particular problem. The first algorithm proposed here is worth mentioning not only for its simplicity. but also from a practical point of view: a speed up of a factor P is achieved by using P processors. 1≤P≤N, where N is the number of edges used to describe a polygonal scene. Additionally. the problem of aliasing inherent with approximation methods is avoided. The significance of the second algorithm, which is based on the first one, is mainly on the theoretical level: it is used to establish the parallel complexity of the hidden-line problem. The sequential complexity of this problem has recently been proved to be Θ(N2), and now we can prove that in the parallel case the problem is in the complexity class NC, i.e., it can be solved in time polynomial in log N by using a number of processors polynomial in N, assuming any reasonable model of parallel computation. More particularly, an O (log N) parallel time solution is given which cannot be further improved even if arbitrarily many processors of a concurrent read, exclusive write parallel RAM model are available.
{"title":"An O(log N) Parallel Time Exact Hidden-Line Algorithm","authors":"F. Dévai","doi":"10.2312/EGGH/EGGH87/065-073","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH87/065-073","url":null,"abstract":"Parallel algorithms are given for the exact solution of the hidden-line problem. Most of the parallel algorithms proposed for visibility problems in the literature give approximate solutions. and thus cannot yield an upper bound on the complexity of the particular problem. The first algorithm proposed here is worth mentioning not only for its simplicity. but also from a practical point of view: a speed up of a factor P is achieved by using P processors. 1≤P≤N, where N is the number of edges used to describe a polygonal scene. Additionally. the problem of aliasing inherent with approximation methods is avoided. \u0000 \u0000The significance of the second algorithm, which is based on the first one, is mainly on the theoretical level: it is used to establish the parallel complexity of the hidden-line problem. The sequential complexity of this problem has recently been proved to be Θ(N2), and now we can prove that in the parallel case the problem is in the complexity class NC, i.e., it can be solved in time polynomial in log N by using a number of processors polynomial in N, assuming any reasonable model of parallel computation. More particularly, an O (log N) parallel time solution is given which cannot be further improved even if arbitrarily many processors of a concurrent read, exclusive write parallel RAM model are available.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115777931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.2312/EGGH/EGGH89/213-227
D. Jackel, H. Günther, B. Herwig, H. Rüsseler
This paper describes the architecture of a raster scan display for real-time visualisation of shaded polygons. A performance of 15-106 Phong shaded pixels per second is a primary goal of a pipelined rendering processor. The performance of the geometry processor, which is responsible for the geometrical transformations, the 3-d clipping and the perspective projection, will exceed 100,000 triangle shaped polygons. Following a survey of the entire 3-d real-time system, we will describe architectural details of the rendering processor. Finally, the main features enabled by the architecture are highlighted.
{"title":"A Real-Time Raster Scan Display for 3-D Graphics","authors":"D. Jackel, H. Günther, B. Herwig, H. Rüsseler","doi":"10.2312/EGGH/EGGH89/213-227","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH89/213-227","url":null,"abstract":"This paper describes the architecture of a raster scan display for real-time visualisation of shaded polygons. A performance of 15-106 Phong shaded pixels per second is a primary goal of a pipelined rendering processor. The performance of the geometry processor, which is responsible for the geometrical transformations, the 3-d clipping and the perspective projection, will exceed 100,000 triangle shaped polygons. \u0000 \u0000Following a survey of the entire 3-d real-time system, we will describe architectural details of the rendering processor. Finally, the main features enabled by the architecture are highlighted.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131495030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.2312/EGGH/EGGH91/141-156
Graham J. Dunnett, M. White, P. Lister, R. L. Grimsdale
We present a design and test strategy for Geometric Primitive Shadersintegrated circuits which perform rasterisation of primitives such as vectors and triangles. The design strategy proceeds through various levels of detail, and we describe the need for testing as the design advances. A suitable set of test are given for a typical shader. Our experiences in applying the strategy to a real device are discussed, together with the tests which we devised, and practical compromises which we had to make.
{"title":"Testing Geometric Primitive Shaders","authors":"Graham J. Dunnett, M. White, P. Lister, R. L. Grimsdale","doi":"10.2312/EGGH/EGGH91/141-156","DOIUrl":"https://doi.org/10.2312/EGGH/EGGH91/141-156","url":null,"abstract":"We present a design and test strategy for Geometric Primitive Shadersintegrated circuits which perform rasterisation of primitives such as vectors and triangles. The design strategy proceeds through various levels of detail, and we describe the need for testing as the design advances. A suitable set of test are given for a typical shader. Our experiences in applying the strategy to a real device are discussed, together with the tests which we devised, and practical compromises which we had to make.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131670798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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